Clocks

Introduction

Functions
void	SysCtl_pollSyncBusy (uint32_t mask)
static void	SysCtl_enableMCD (void)
static void	SysCtl_disableMCD (void)
static bool	SysCtl_isMCDClockFailureDetected (void)
static void	SysCtl_resetMCD (void)
static void	SysCtl_connectMCDClockSource (void)
static void	SysCtl_disconnectMCDClockSource (void)
static void	SysCtl_setXClk (SysCtl_XClkSource clksrc, SysCtl_XClkDivider divider)
static void	SysCtl_delay69Cycles (void)
static void	SysCtl_setMCANClock (SysCtl_MCANInstance mcanInst, SysCtl_MCANClkSource clksrc, SysCtl_MCANClkDivider divider)
static void	SysCtl_setCputimer2Clock (SysCtl_Cputimer2ClkSource source, SysCtl_Cputimer2ClkDivider divider)
static void	SysCtl_setEPWMClock (SysCtl_EPWMClkDivider divider)
static void	SysCtl_setEMIF1Clock (SysCtl_EMIFClkDivider divider)
static void	SysCtl_setLINAClock (SysCtl_LINClkDivider divider)
static void	SysCtl_setLINBClock (SysCtl_LINClkDivider divider)
static void	SysCtl_setECatClock (SysCtl_ECatClkDivider divider, SysCtl_ECatPhyClk phyEnable)
static void	SysCtl_setCLBClock (SysCtl_CLBClkDivider divider, SysCtl_CLBTClkDivider tdivider, uint32_t clkMode)
static void	SysCtl_setHSMClock (SysCtl_HSMClkDivider divider)
static uint16_t	SysCtl_getExternalOscCounterValue (void)
static void	SysCtl_clearExternalOscCounterValue (void)
static void	SysCtl_turnOnXTAL (void)
static void	SysCtl_turnOffXTAL (void)
uint32_t	SysCtl_getClock (uint32_t clockInHz)
bool	SysCtl_setClock (Sysctl_PLLClockSource oscSrc, Sysctl_PLLConfig pllConfig, Sysctl_PLLRefDiv refDiv, Sysctl_PLLIMult iMult, Sysctl_PLLODiv oDiv, Sysctl_PLLSysDiv sysDiv, uint32_t dccBase, uint32_t oscClk)
bool	SysCtl_selectOscSource (uint32_t oscSource, uint32_t oscClk, uint32_t dccBase)

Enumerations
enum	Sysctl_PLLClockSource { SYSCTL_OSCSRC_OSC2 = 0x00 , SYSCTL_OSCSRC_XTAL = 0x01 , SYSCTL_OSCSRC_XTAL_SE = 0x11 , SYSCTL_OSCSRC_OSC1 = 0x02 }
enum	Sysctl_PLLConfig { SYSCTL_PLL_ENABLE , SYSCTL_PLL_DISABLE , SYSCTL_PLL_BYPASS }
enum	Sysctl_PLLRefDiv {   SYSCTL_REFDIV_1 , SYSCTL_REFDIV_2 , SYSCTL_REFDIV_3 , SYSCTL_REFDIV_4 ,   SYSCTL_REFDIV_5 , SYSCTL_REFDIV_6 , SYSCTL_REFDIV_7 , SYSCTL_REFDIV_8 ,   SYSCTL_REFDIV_9 , SYSCTL_REFDIV_10 , SYSCTL_REFDIV_11 , SYSCTL_REFDIV_12 ,   SYSCTL_REFDIV_13 , SYSCTL_REFDIV_14 , SYSCTL_REFDIV_15 , SYSCTL_REFDIV_16 ,   SYSCTL_REFDIV_17 , SYSCTL_REFDIV_18 , SYSCTL_REFDIV_19 , SYSCTL_REFDIV_20 ,   SYSCTL_REFDIV_21 , SYSCTL_REFDIV_22 , SYSCTL_REFDIV_23 , SYSCTL_REFDIV_24 ,   SYSCTL_REFDIV_25 , SYSCTL_REFDIV_26 , SYSCTL_REFDIV_27 , SYSCTL_REFDIV_28 ,   SYSCTL_REFDIV_29 , SYSCTL_REFDIV_30 , SYSCTL_REFDIV_31 , SYSCTL_REFDIV_32 }
enum	Sysctl_PLLIMult {   SYSCTL_IMULT_4 = 4 , SYSCTL_IMULT_5 , SYSCTL_IMULT_6 , SYSCTL_IMULT_7 ,   SYSCTL_IMULT_8 , SYSCTL_IMULT_9 , SYSCTL_IMULT_10 , SYSCTL_IMULT_11 ,   SYSCTL_IMULT_12 , SYSCTL_IMULT_13 , SYSCTL_IMULT_14 , SYSCTL_IMULT_15 ,   SYSCTL_IMULT_16 , SYSCTL_IMULT_17 , SYSCTL_IMULT_18 , SYSCTL_IMULT_19 ,   SYSCTL_IMULT_20 , SYSCTL_IMULT_21 , SYSCTL_IMULT_22 , SYSCTL_IMULT_23 ,   SYSCTL_IMULT_24 , SYSCTL_IMULT_25 , SYSCTL_IMULT_26 , SYSCTL_IMULT_27 ,   SYSCTL_IMULT_28 , SYSCTL_IMULT_29 , SYSCTL_IMULT_30 , SYSCTL_IMULT_31 ,   SYSCTL_IMULT_32 , SYSCTL_IMULT_33 , SYSCTL_IMULT_34 , SYSCTL_IMULT_35 ,   SYSCTL_IMULT_36 , SYSCTL_IMULT_37 , SYSCTL_IMULT_38 , SYSCTL_IMULT_39 ,   SYSCTL_IMULT_40 , SYSCTL_IMULT_41 , SYSCTL_IMULT_42 , SYSCTL_IMULT_43 ,   SYSCTL_IMULT_44 , SYSCTL_IMULT_45 , SYSCTL_IMULT_46 , SYSCTL_IMULT_47 ,   SYSCTL_IMULT_48 , SYSCTL_IMULT_49 , SYSCTL_IMULT_50 , SYSCTL_IMULT_51 ,   SYSCTL_IMULT_52 , SYSCTL_IMULT_53 , SYSCTL_IMULT_54 , SYSCTL_IMULT_55 ,   SYSCTL_IMULT_56 , SYSCTL_IMULT_57 , SYSCTL_IMULT_58 , SYSCTL_IMULT_59 ,   SYSCTL_IMULT_60 , SYSCTL_IMULT_61 , SYSCTL_IMULT_62 , SYSCTL_IMULT_63 ,   SYSCTL_IMULT_64 , SYSCTL_IMULT_65 , SYSCTL_IMULT_66 , SYSCTL_IMULT_67 ,   SYSCTL_IMULT_68 , SYSCTL_IMULT_69 , SYSCTL_IMULT_70 , SYSCTL_IMULT_71 ,   SYSCTL_IMULT_72 , SYSCTL_IMULT_73 , SYSCTL_IMULT_74 , SYSCTL_IMULT_75 ,   SYSCTL_IMULT_76 , SYSCTL_IMULT_77 , SYSCTL_IMULT_78 , SYSCTL_IMULT_79 ,   SYSCTL_IMULT_80 , SYSCTL_IMULT_81 , SYSCTL_IMULT_82 , SYSCTL_IMULT_83 ,   SYSCTL_IMULT_84 , SYSCTL_IMULT_85 , SYSCTL_IMULT_86 , SYSCTL_IMULT_87 ,   SYSCTL_IMULT_88 , SYSCTL_IMULT_89 , SYSCTL_IMULT_90 , SYSCTL_IMULT_91 ,   SYSCTL_IMULT_92 , SYSCTL_IMULT_93 , SYSCTL_IMULT_94 , SYSCTL_IMULT_95 ,   SYSCTL_IMULT_96 , SYSCTL_IMULT_97 , SYSCTL_IMULT_98 , SYSCTL_IMULT_99 ,   SYSCTL_IMULT_100 , SYSCTL_IMULT_101 , SYSCTL_IMULT_102 , SYSCTL_IMULT_103 ,   SYSCTL_IMULT_104 , SYSCTL_IMULT_105 , SYSCTL_IMULT_106 , SYSCTL_IMULT_107 ,   SYSCTL_IMULT_108 , SYSCTL_IMULT_109 , SYSCTL_IMULT_110 , SYSCTL_IMULT_111 ,   SYSCTL_IMULT_112 , SYSCTL_IMULT_113 , SYSCTL_IMULT_114 , SYSCTL_IMULT_115 ,   SYSCTL_IMULT_116 , SYSCTL_IMULT_117 , SYSCTL_IMULT_118 , SYSCTL_IMULT_119 ,   SYSCTL_IMULT_120 , SYSCTL_IMULT_121 , SYSCTL_IMULT_122 , SYSCTL_IMULT_123 ,   SYSCTL_IMULT_124 , SYSCTL_IMULT_125 , SYSCTL_IMULT_126 , SYSCTL_IMULT_127 ,   SYSCTL_IMULT_128 , SYSCTL_IMULT_129 , SYSCTL_IMULT_130 , SYSCTL_IMULT_131 ,   SYSCTL_IMULT_132 , SYSCTL_IMULT_133 , SYSCTL_IMULT_134 , SYSCTL_IMULT_135 ,   SYSCTL_IMULT_136 , SYSCTL_IMULT_137 , SYSCTL_IMULT_138 , SYSCTL_IMULT_139 ,   SYSCTL_IMULT_140 , SYSCTL_IMULT_141 , SYSCTL_IMULT_142 , SYSCTL_IMULT_143 ,   SYSCTL_IMULT_144 , SYSCTL_IMULT_145 , SYSCTL_IMULT_146 , SYSCTL_IMULT_147 ,   SYSCTL_IMULT_148 , SYSCTL_IMULT_149 , SYSCTL_IMULT_150 , SYSCTL_IMULT_151 ,   SYSCTL_IMULT_152 , SYSCTL_IMULT_153 , SYSCTL_IMULT_154 , SYSCTL_IMULT_155 ,   SYSCTL_IMULT_156 , SYSCTL_IMULT_157 , SYSCTL_IMULT_158 , SYSCTL_IMULT_159 ,   SYSCTL_IMULT_160 , SYSCTL_IMULT_161 , SYSCTL_IMULT_162 , SYSCTL_IMULT_163 ,   SYSCTL_IMULT_164 , SYSCTL_IMULT_165 , SYSCTL_IMULT_166 , SYSCTL_IMULT_167 ,   SYSCTL_IMULT_168 , SYSCTL_IMULT_169 , SYSCTL_IMULT_170 , SYSCTL_IMULT_171 ,   SYSCTL_IMULT_172 , SYSCTL_IMULT_173 , SYSCTL_IMULT_174 , SYSCTL_IMULT_175 ,   SYSCTL_IMULT_176 , SYSCTL_IMULT_177 , SYSCTL_IMULT_178 , SYSCTL_IMULT_179 ,   SYSCTL_IMULT_180 , SYSCTL_IMULT_181 , SYSCTL_IMULT_182 , SYSCTL_IMULT_183 ,   SYSCTL_IMULT_184 , SYSCTL_IMULT_185 , SYSCTL_IMULT_186 , SYSCTL_IMULT_187 ,   SYSCTL_IMULT_188 , SYSCTL_IMULT_189 , SYSCTL_IMULT_190 , SYSCTL_IMULT_191 ,   SYSCTL_IMULT_192 , SYSCTL_IMULT_193 , SYSCTL_IMULT_194 , SYSCTL_IMULT_195 ,   SYSCTL_IMULT_196 , SYSCTL_IMULT_197 , SYSCTL_IMULT_198 , SYSCTL_IMULT_199 ,   SYSCTL_IMULT_200 , SYSCTL_IMULT_201 , SYSCTL_IMULT_202 , SYSCTL_IMULT_203 ,   SYSCTL_IMULT_204 , SYSCTL_IMULT_205 , SYSCTL_IMULT_206 , SYSCTL_IMULT_207 ,   SYSCTL_IMULT_208 , SYSCTL_IMULT_209 , SYSCTL_IMULT_210 , SYSCTL_IMULT_211 ,   SYSCTL_IMULT_212 , SYSCTL_IMULT_213 , SYSCTL_IMULT_214 , SYSCTL_IMULT_215 ,   SYSCTL_IMULT_216 , SYSCTL_IMULT_217 , SYSCTL_IMULT_218 , SYSCTL_IMULT_219 ,   SYSCTL_IMULT_220 , SYSCTL_IMULT_221 , SYSCTL_IMULT_222 , SYSCTL_IMULT_223 ,   SYSCTL_IMULT_224 , SYSCTL_IMULT_225 , SYSCTL_IMULT_226 , SYSCTL_IMULT_227 ,   SYSCTL_IMULT_228 , SYSCTL_IMULT_229 , SYSCTL_IMULT_230 , SYSCTL_IMULT_231 ,   SYSCTL_IMULT_232 , SYSCTL_IMULT_233 , SYSCTL_IMULT_234 , SYSCTL_IMULT_235 ,   SYSCTL_IMULT_236 , SYSCTL_IMULT_237 , SYSCTL_IMULT_238 , SYSCTL_IMULT_239 ,   SYSCTL_IMULT_240 , SYSCTL_IMULT_241 , SYSCTL_IMULT_242 , SYSCTL_IMULT_243 ,   SYSCTL_IMULT_244 , SYSCTL_IMULT_245 , SYSCTL_IMULT_246 , SYSCTL_IMULT_247 ,   SYSCTL_IMULT_248 , SYSCTL_IMULT_249 , SYSCTL_IMULT_250 , SYSCTL_IMULT_251 ,   SYSCTL_IMULT_252 , SYSCTL_IMULT_253 , SYSCTL_IMULT_254 , SYSCTL_IMULT_255 }
enum	Sysctl_PLLODiv {   SYSCTL_ODIV_1 , SYSCTL_ODIV_2 , SYSCTL_ODIV_3 , SYSCTL_ODIV_4 ,   SYSCTL_ODIV_5 , SYSCTL_ODIV_6 , SYSCTL_ODIV_7 , SYSCTL_ODIV_8 ,   SYSCTL_ODIV_9 , SYSCTL_ODIV_10 , SYSCTL_ODIV_11 , SYSCTL_ODIV_12 ,   SYSCTL_ODIV_13 , SYSCTL_ODIV_14 , SYSCTL_ODIV_15 , SYSCTL_ODIV_16 ,   SYSCTL_ODIV_17 , SYSCTL_ODIV_18 , SYSCTL_ODIV_19 , SYSCTL_ODIV_20 ,   SYSCTL_ODIV_21 , SYSCTL_ODIV_22 , SYSCTL_ODIV_23 , SYSCTL_ODIV_24 ,   SYSCTL_ODIV_25 , SYSCTL_ODIV_26 , SYSCTL_ODIV_27 , SYSCTL_ODIV_28 ,   SYSCTL_ODIV_29 , SYSCTL_ODIV_30 , SYSCTL_ODIV_31 , SYSCTL_ODIV_32 }
enum	Sysctl_PLLSysDiv {   SYSCTL_SYSDIV_1 , SYSCTL_SYSDIV_2 , SYSCTL_SYSDIV_3 , SYSCTL_SYSDIV_4 ,   SYSCTL_SYSDIV_5 , SYSCTL_SYSDIV_6 , SYSCTL_SYSDIV_7 , SYSCTL_SYSDIV_8 ,   SYSCTL_SYSDIV_9 , SYSCTL_SYSDIV_10 , SYSCTL_SYSDIV_11 , SYSCTL_SYSDIV_12 ,   SYSCTL_SYSDIV_13 , SYSCTL_SYSDIV_14 , SYSCTL_SYSDIV_15 , SYSCTL_SYSDIV_16 ,   SYSCTL_SYSDIV_17 , SYSCTL_SYSDIV_18 , SYSCTL_SYSDIV_19 , SYSCTL_SYSDIV_20 ,   SYSCTL_SYSDIV_21 , SYSCTL_SYSDIV_22 , SYSCTL_SYSDIV_23 , SYSCTL_SYSDIV_24 ,   SYSCTL_SYSDIV_25 , SYSCTL_SYSDIV_26 , SYSCTL_SYSDIV_27 , SYSCTL_SYSDIV_28 ,   SYSCTL_SYSDIV_29 , SYSCTL_SYSDIV_30 , SYSCTL_SYSDIV_31 , SYSCTL_SYSDIV_32 ,   SYSCTL_SYSDIV_33 , SYSCTL_SYSDIV_34 , SYSCTL_SYSDIV_35 , SYSCTL_SYSDIV_36 ,   SYSCTL_SYSDIV_37 , SYSCTL_SYSDIV_38 , SYSCTL_SYSDIV_39 , SYSCTL_SYSDIV_40 ,   SYSCTL_SYSDIV_41 , SYSCTL_SYSDIV_42 , SYSCTL_SYSDIV_43 , SYSCTL_SYSDIV_44 ,   SYSCTL_SYSDIV_45 , SYSCTL_SYSDIV_46 , SYSCTL_SYSDIV_47 , SYSCTL_SYSDIV_48 ,   SYSCTL_SYSDIV_49 , SYSCTL_SYSDIV_50 , SYSCTL_SYSDIV_51 , SYSCTL_SYSDIV_52 ,   SYSCTL_SYSDIV_53 , SYSCTL_SYSDIV_54 , SYSCTL_SYSDIV_55 , SYSCTL_SYSDIV_56 ,   SYSCTL_SYSDIV_57 , SYSCTL_SYSDIV_58 , SYSCTL_SYSDIV_59 , SYSCTL_SYSDIV_60 ,   SYSCTL_SYSDIV_61 , SYSCTL_SYSDIV_62 , SYSCTL_SYSDIV_63 , SYSCTL_SYSDIV_64 }
enum	SysCtl_XClkSource {   SYSCTL_XCLKOUT_SOURCE_PLLSYS = 0U , SYSCTL_XCLKOUT_SOURCE_CPU1CLK = 1U , SYSCTL_XCLKOUT_SOURCE_CPU2CLK = 2U , SYSCTL_XCLKOUT_SOURCE_CPU3CLK = 3U ,   SYSCTL_XCLKOUT_SOURCE_INTOSC1 = 5U , SYSCTL_XCLKOUT_SOURCE_INTOSC2 = 6U , SYSCTL_XCLKOUT_SOURCE_XTALOSC = 7U }
enum	SysCtl_XClkDivider { SYSCTL_XCLKOUT_DIV_1 = 0 , SYSCTL_XCLKOUT_DIV_2 = 1 , SYSCTL_XCLKOUT_DIV_4 = 2 , SYSCTL_XCLKOUT_DIV_8 = 3 }
enum	SysCtl_MCANInstance {   SYSCTL_MCAN_A , SYSCTL_MCAN_B , SYSCTL_MCAN_C , SYSCTL_MCAN_D ,   SYSCTL_MCAN_E , SYSCTL_MCAN_F }
enum	SysCtl_MCANClkSource { SYSCTL_MCANCLK_SOURCE_SYS = 0x0 , SYSCTL_MCANCLK_SOURCE_AUXIN = 0x2 , SYSCTL_MCANCLK_SOURCE_PLLRAW = 0x3 }
enum	SysCtl_MCANClkDivider {   SYSCTL_MCANCLK_DIV_1 = 0x0 , SYSCTL_MCANCLK_DIV_2 = 0x1 , SYSCTL_MCANCLK_DIV_3 = 0x2 , SYSCTL_MCANCLK_DIV_4 = 0x3 ,   SYSCTL_MCANCLK_DIV_5 = 0x4 , SYSCTL_MCANCLK_DIV_6 = 0x5 , SYSCTL_MCANCLK_DIV_7 = 0x6 , SYSCTL_MCANCLK_DIV_8 = 0x7 ,   SYSCTL_MCANCLK_DIV_9 = 0x8 , SYSCTL_MCANCLK_DIV_10 = 0x9 , SYSCTL_MCANCLK_DIV_11 = 0xA , SYSCTL_MCANCLK_DIV_12 = 0xB ,   SYSCTL_MCANCLK_DIV_13 = 0xC , SYSCTL_MCANCLK_DIV_14 = 0xD , SYSCTL_MCANCLK_DIV_15 = 0xE , SYSCTL_MCANCLK_DIV_16 = 0xF ,   SYSCTL_MCANCLK_DIV_17 = 0x10 , SYSCTL_MCANCLK_DIV_18 = 0x11 , SYSCTL_MCANCLK_DIV_19 = 0x12 , SYSCTL_MCANCLK_DIV_20 = 0x13 }
enum	SysCtl_Cputimer2ClkSource { SYSCTL_TIMER2CLK_SOURCE_SYSCLK = 0U , SYSCTL_TIMER2CLK_SOURCE_INTOSC1 = 1U , SYSCTL_TIMER2CLK_SOURCE_INTOSC2 = 2U , SYSCTL_TIMER2CLK_SOURCE_XTAL = 3U }
enum	SysCtl_Cputimer2ClkDivider {   SYSCTL_TIMER2CLK_DIV_1 = 0 , SYSCTL_TIMER2CLK_DIV_2 = 1 , SYSCTL_TIMER2CLK_DIV_4 = 2 , SYSCTL_TIMER2CLK_DIV_8 = 3 ,   SYSCTL_TIMER2CLK_DIV_16 = 4 }
enum	SysCtl_EPWMClkDivider { SYSCTL_EPWMCLK_DIV_1 , SYSCTL_EPWMCLK_DIV_2 }
enum	SysCtl_EMIFClkDivider { SYSCTL_EMIFCLK_DIV_1 , SYSCTL_EMIFCLK_DIV_2 , SYSCTL_EMIFCLK_DIV_4 }
enum	SysCtl_LINClkDivider { SYSCTL_LINCLK_DIV_1 , SYSCTL_LINCLK_DIV_2 , SYSCTL_LINCLK_DIV_4 }
enum	SysCtl_ECatClkDivider {   SYSCTL_ECATCLKOUT_DIV_1 , SYSCTL_ECATCLKOUT_DIV_2 , SYSCTL_ECATCLKOUT_DIV_3 , SYSCTL_ECATCLKOUT_DIV_4 ,   SYSCTL_ECATCLKOUT_DIV_5 , SYSCTL_ECATCLKOUT_DIV_6 , SYSCTL_ECATCLKOUT_DIV_7 , SYSCTL_ECATCLKOUT_DIV_8 }
enum	SysCtl_ECatPhyClk { SYSCTL_ECAT_PHYCLK_ENABLE = SYSCTL_ETHERCATCLKCTL_PHYCLKEN , SYSCTL_ECAT_PHYCLK_DISABLE = 0U }
enum	SysCtl_CLBClkDivider {   SYSCTL_CLBCLKOUT_DIV_1 , SYSCTL_CLBCLKOUT_DIV_2 , SYSCTL_CLBCLKOUT_DIV_3 , SYSCTL_CLBCLKOUT_DIV_4 ,   SYSCTL_CLBCLKOUT_DIV_5 , SYSCTL_CLBCLKOUT_DIV_6 , SYSCTL_CLBCLKOUT_DIV_7 , SYSCTL_CLBCLKOUT_DIV_8 }
enum	SysCtl_CLBTClkDivider { SYSCTL_CLBTCLKOUT_DIV_1 , SYSCTL_CLBTCLKOUT_DIV_2 }
enum	SysCtl_HSMClkDivider {   SYSCTL_HSMCLK_DIV_1 , SYSCTL_HSMCLK_DIV_2 , SYSCTL_HSMCLK_DIV_4 , SYSCTL_HSMCLK_DIV_8 ,   SYSCTL_HSMCLK_DIV_16 }

Macros
#define	SYSCTL_DEFAULT_OSC_FREQ   10000000U
#define	SYSCTL_CLB1CLKMODE_SYNC   0U
#define	SYSCTL_CLB1CLKMODE_ASYNC   SYSCTL_CLBCLKCTL_CLKMODECLB1
#define	SYSCTL_CLB2CLKMODE_SYNC   0U
#define	SYSCTL_CLB2CLKMODE_ASYNC   SYSCTL_CLBCLKCTL_CLKMODECLB2
#define	SYSCTL_CLB3CLKMODE_SYNC   0U
#define	SYSCTL_CLB3CLKMODE_ASYNC   SYSCTL_CLBCLKCTL_CLKMODECLB3
#define	SYSCTL_CLB4CLKMODE_SYNC   0U
#define	SYSCTL_CLB4CLKMODE_ASYNC   SYSCTL_CLBCLKCTL_CLKMODECLB4
#define	SYSCTL_CLB5CLKMODE_SYNC   0U
#define	SYSCTL_CLB5CLKMODE_ASYNC   SYSCTL_CLBCLKCTL_CLKMODECLB5
#define	SYSCTL_CLB6CLKMODE_SYNC   0U
#define	SYSCTL_CLB6CLKMODE_ASYNC   SYSCTL_CLBCLKCTL_CLKMODECLB6

Macro Definition Documentation

SYSCTL_DEFAULT_OSC_FREQ

#define SYSCTL_DEFAULT_OSC_FREQ   10000000U

SYSCTL_CLB1CLKMODE_SYNC

#define SYSCTL_CLB1CLKMODE_SYNC   0U

The following are values that can be passed to SysCtl_setCLBClock() as cpuInst parameter.

SYSCTL_CLB1CLKMODE_ASYNC

#define SYSCTL_CLB1CLKMODE_ASYNC   SYSCTL_CLBCLKCTL_CLKMODECLB1

SYSCTL_CLB2CLKMODE_SYNC

#define SYSCTL_CLB2CLKMODE_SYNC   0U

SYSCTL_CLB2CLKMODE_ASYNC

#define SYSCTL_CLB2CLKMODE_ASYNC   SYSCTL_CLBCLKCTL_CLKMODECLB2

SYSCTL_CLB3CLKMODE_SYNC

#define SYSCTL_CLB3CLKMODE_SYNC   0U

SYSCTL_CLB3CLKMODE_ASYNC

#define SYSCTL_CLB3CLKMODE_ASYNC   SYSCTL_CLBCLKCTL_CLKMODECLB3

SYSCTL_CLB4CLKMODE_SYNC

#define SYSCTL_CLB4CLKMODE_SYNC   0U

SYSCTL_CLB4CLKMODE_ASYNC

#define SYSCTL_CLB4CLKMODE_ASYNC   SYSCTL_CLBCLKCTL_CLKMODECLB4

SYSCTL_CLB5CLKMODE_SYNC

#define SYSCTL_CLB5CLKMODE_SYNC   0U

SYSCTL_CLB5CLKMODE_ASYNC

#define SYSCTL_CLB5CLKMODE_ASYNC   SYSCTL_CLBCLKCTL_CLKMODECLB5

SYSCTL_CLB6CLKMODE_SYNC

#define SYSCTL_CLB6CLKMODE_SYNC   0U

SYSCTL_CLB6CLKMODE_ASYNC

#define SYSCTL_CLB6CLKMODE_ASYNC   SYSCTL_CLBCLKCTL_CLKMODECLB6

Enumeration Type Documentation

Sysctl_PLLClockSource

enum Sysctl_PLLClockSource

The following are values that can be passed to Sysctl_setClock() as oscSrc parameter

Enumerator
SYSCTL_OSCSRC_OSC2
SYSCTL_OSCSRC_XTAL
SYSCTL_OSCSRC_XTAL_SE
SYSCTL_OSCSRC_OSC1

Sysctl_PLLConfig

enum Sysctl_PLLConfig

The following are values that can be passed to Sysctl_setClock() as pllConfig parameter

Enumerator
SYSCTL_PLL_ENABLE
SYSCTL_PLL_DISABLE
SYSCTL_PLL_BYPASS

Sysctl_PLLRefDiv

enum Sysctl_PLLRefDiv

The following are values that can be passed to Sysctl_setClock() as refdiv parameter

Enumerator
SYSCTL_REFDIV_1
SYSCTL_REFDIV_2
SYSCTL_REFDIV_3
SYSCTL_REFDIV_4
SYSCTL_REFDIV_5
SYSCTL_REFDIV_6
SYSCTL_REFDIV_7
SYSCTL_REFDIV_8
SYSCTL_REFDIV_9
SYSCTL_REFDIV_10
SYSCTL_REFDIV_11
SYSCTL_REFDIV_12
SYSCTL_REFDIV_13
SYSCTL_REFDIV_14
SYSCTL_REFDIV_15
SYSCTL_REFDIV_16
SYSCTL_REFDIV_17
SYSCTL_REFDIV_18
SYSCTL_REFDIV_19
SYSCTL_REFDIV_20
SYSCTL_REFDIV_21
SYSCTL_REFDIV_22
SYSCTL_REFDIV_23
SYSCTL_REFDIV_24
SYSCTL_REFDIV_25
SYSCTL_REFDIV_26
SYSCTL_REFDIV_27
SYSCTL_REFDIV_28
SYSCTL_REFDIV_29
SYSCTL_REFDIV_30
SYSCTL_REFDIV_31
SYSCTL_REFDIV_32

Sysctl_PLLIMult

enum Sysctl_PLLIMult

The following are values that can be passed to Sysctl_setClock() as imult parameter

Enumerator
SYSCTL_IMULT_4
SYSCTL_IMULT_5
SYSCTL_IMULT_6
SYSCTL_IMULT_7
SYSCTL_IMULT_8
SYSCTL_IMULT_9
SYSCTL_IMULT_10
SYSCTL_IMULT_11
SYSCTL_IMULT_12
SYSCTL_IMULT_13
SYSCTL_IMULT_14
SYSCTL_IMULT_15
SYSCTL_IMULT_16
SYSCTL_IMULT_17
SYSCTL_IMULT_18
SYSCTL_IMULT_19
SYSCTL_IMULT_20
SYSCTL_IMULT_21
SYSCTL_IMULT_22
SYSCTL_IMULT_23
SYSCTL_IMULT_24
SYSCTL_IMULT_25
SYSCTL_IMULT_26
SYSCTL_IMULT_27
SYSCTL_IMULT_28
SYSCTL_IMULT_29
SYSCTL_IMULT_30
SYSCTL_IMULT_31
SYSCTL_IMULT_32
SYSCTL_IMULT_33
SYSCTL_IMULT_34
SYSCTL_IMULT_35
SYSCTL_IMULT_36
SYSCTL_IMULT_37
SYSCTL_IMULT_38
SYSCTL_IMULT_39
SYSCTL_IMULT_40
SYSCTL_IMULT_41
SYSCTL_IMULT_42
SYSCTL_IMULT_43
SYSCTL_IMULT_44
SYSCTL_IMULT_45
SYSCTL_IMULT_46
SYSCTL_IMULT_47
SYSCTL_IMULT_48
SYSCTL_IMULT_49
SYSCTL_IMULT_50
SYSCTL_IMULT_51
SYSCTL_IMULT_52
SYSCTL_IMULT_53
SYSCTL_IMULT_54
SYSCTL_IMULT_55
SYSCTL_IMULT_56
SYSCTL_IMULT_57
SYSCTL_IMULT_58
SYSCTL_IMULT_59
SYSCTL_IMULT_60
SYSCTL_IMULT_61
SYSCTL_IMULT_62
SYSCTL_IMULT_63
SYSCTL_IMULT_64
SYSCTL_IMULT_65
SYSCTL_IMULT_66
SYSCTL_IMULT_67
SYSCTL_IMULT_68
SYSCTL_IMULT_69
SYSCTL_IMULT_70
SYSCTL_IMULT_71
SYSCTL_IMULT_72
SYSCTL_IMULT_73
SYSCTL_IMULT_74
SYSCTL_IMULT_75
SYSCTL_IMULT_76
SYSCTL_IMULT_77
SYSCTL_IMULT_78
SYSCTL_IMULT_79
SYSCTL_IMULT_80
SYSCTL_IMULT_81
SYSCTL_IMULT_82
SYSCTL_IMULT_83
SYSCTL_IMULT_84
SYSCTL_IMULT_85
SYSCTL_IMULT_86
SYSCTL_IMULT_87
SYSCTL_IMULT_88
SYSCTL_IMULT_89
SYSCTL_IMULT_90
SYSCTL_IMULT_91
SYSCTL_IMULT_92
SYSCTL_IMULT_93
SYSCTL_IMULT_94
SYSCTL_IMULT_95
SYSCTL_IMULT_96
SYSCTL_IMULT_97
SYSCTL_IMULT_98
SYSCTL_IMULT_99
SYSCTL_IMULT_100
SYSCTL_IMULT_101
SYSCTL_IMULT_102
SYSCTL_IMULT_103
SYSCTL_IMULT_104
SYSCTL_IMULT_105
SYSCTL_IMULT_106
SYSCTL_IMULT_107
SYSCTL_IMULT_108
SYSCTL_IMULT_109
SYSCTL_IMULT_110
SYSCTL_IMULT_111
SYSCTL_IMULT_112
SYSCTL_IMULT_113
SYSCTL_IMULT_114
SYSCTL_IMULT_115
SYSCTL_IMULT_116
SYSCTL_IMULT_117
SYSCTL_IMULT_118
SYSCTL_IMULT_119
SYSCTL_IMULT_120
SYSCTL_IMULT_121
SYSCTL_IMULT_122
SYSCTL_IMULT_123
SYSCTL_IMULT_124
SYSCTL_IMULT_125
SYSCTL_IMULT_126
SYSCTL_IMULT_127
SYSCTL_IMULT_128
SYSCTL_IMULT_129
SYSCTL_IMULT_130
SYSCTL_IMULT_131
SYSCTL_IMULT_132
SYSCTL_IMULT_133
SYSCTL_IMULT_134
SYSCTL_IMULT_135
SYSCTL_IMULT_136
SYSCTL_IMULT_137
SYSCTL_IMULT_138
SYSCTL_IMULT_139
SYSCTL_IMULT_140
SYSCTL_IMULT_141
SYSCTL_IMULT_142
SYSCTL_IMULT_143
SYSCTL_IMULT_144
SYSCTL_IMULT_145
SYSCTL_IMULT_146
SYSCTL_IMULT_147
SYSCTL_IMULT_148
SYSCTL_IMULT_149
SYSCTL_IMULT_150
SYSCTL_IMULT_151
SYSCTL_IMULT_152
SYSCTL_IMULT_153
SYSCTL_IMULT_154
SYSCTL_IMULT_155
SYSCTL_IMULT_156
SYSCTL_IMULT_157
SYSCTL_IMULT_158
SYSCTL_IMULT_159
SYSCTL_IMULT_160
SYSCTL_IMULT_161
SYSCTL_IMULT_162
SYSCTL_IMULT_163
SYSCTL_IMULT_164
SYSCTL_IMULT_165
SYSCTL_IMULT_166
SYSCTL_IMULT_167
SYSCTL_IMULT_168
SYSCTL_IMULT_169
SYSCTL_IMULT_170
SYSCTL_IMULT_171
SYSCTL_IMULT_172
SYSCTL_IMULT_173
SYSCTL_IMULT_174
SYSCTL_IMULT_175
SYSCTL_IMULT_176
SYSCTL_IMULT_177
SYSCTL_IMULT_178
SYSCTL_IMULT_179
SYSCTL_IMULT_180
SYSCTL_IMULT_181
SYSCTL_IMULT_182
SYSCTL_IMULT_183
SYSCTL_IMULT_184
SYSCTL_IMULT_185
SYSCTL_IMULT_186
SYSCTL_IMULT_187
SYSCTL_IMULT_188
SYSCTL_IMULT_189
SYSCTL_IMULT_190
SYSCTL_IMULT_191
SYSCTL_IMULT_192
SYSCTL_IMULT_193
SYSCTL_IMULT_194
SYSCTL_IMULT_195
SYSCTL_IMULT_196
SYSCTL_IMULT_197
SYSCTL_IMULT_198
SYSCTL_IMULT_199
SYSCTL_IMULT_200
SYSCTL_IMULT_201
SYSCTL_IMULT_202
SYSCTL_IMULT_203
SYSCTL_IMULT_204
SYSCTL_IMULT_205
SYSCTL_IMULT_206
SYSCTL_IMULT_207
SYSCTL_IMULT_208
SYSCTL_IMULT_209
SYSCTL_IMULT_210
SYSCTL_IMULT_211
SYSCTL_IMULT_212
SYSCTL_IMULT_213
SYSCTL_IMULT_214
SYSCTL_IMULT_215
SYSCTL_IMULT_216
SYSCTL_IMULT_217
SYSCTL_IMULT_218
SYSCTL_IMULT_219
SYSCTL_IMULT_220
SYSCTL_IMULT_221
SYSCTL_IMULT_222
SYSCTL_IMULT_223
SYSCTL_IMULT_224
SYSCTL_IMULT_225
SYSCTL_IMULT_226
SYSCTL_IMULT_227
SYSCTL_IMULT_228
SYSCTL_IMULT_229
SYSCTL_IMULT_230
SYSCTL_IMULT_231
SYSCTL_IMULT_232
SYSCTL_IMULT_233
SYSCTL_IMULT_234
SYSCTL_IMULT_235
SYSCTL_IMULT_236
SYSCTL_IMULT_237
SYSCTL_IMULT_238
SYSCTL_IMULT_239
SYSCTL_IMULT_240
SYSCTL_IMULT_241
SYSCTL_IMULT_242
SYSCTL_IMULT_243
SYSCTL_IMULT_244
SYSCTL_IMULT_245
SYSCTL_IMULT_246
SYSCTL_IMULT_247
SYSCTL_IMULT_248
SYSCTL_IMULT_249
SYSCTL_IMULT_250
SYSCTL_IMULT_251
SYSCTL_IMULT_252
SYSCTL_IMULT_253
SYSCTL_IMULT_254
SYSCTL_IMULT_255

Sysctl_PLLODiv

enum Sysctl_PLLODiv

The following are values that can be passed to Sysctl_setClock() as odiv parameter

Enumerator
SYSCTL_ODIV_1
SYSCTL_ODIV_2
SYSCTL_ODIV_3
SYSCTL_ODIV_4
SYSCTL_ODIV_5
SYSCTL_ODIV_6
SYSCTL_ODIV_7
SYSCTL_ODIV_8
SYSCTL_ODIV_9
SYSCTL_ODIV_10
SYSCTL_ODIV_11
SYSCTL_ODIV_12
SYSCTL_ODIV_13
SYSCTL_ODIV_14
SYSCTL_ODIV_15
SYSCTL_ODIV_16
SYSCTL_ODIV_17
SYSCTL_ODIV_18
SYSCTL_ODIV_19
SYSCTL_ODIV_20
SYSCTL_ODIV_21
SYSCTL_ODIV_22
SYSCTL_ODIV_23
SYSCTL_ODIV_24
SYSCTL_ODIV_25
SYSCTL_ODIV_26
SYSCTL_ODIV_27
SYSCTL_ODIV_28
SYSCTL_ODIV_29
SYSCTL_ODIV_30
SYSCTL_ODIV_31
SYSCTL_ODIV_32

Sysctl_PLLSysDiv

enum Sysctl_PLLSysDiv

The following are values that can be passed to Sysctl_setClock() as sysdiv parameter

Enumerator
SYSCTL_SYSDIV_1
SYSCTL_SYSDIV_2
SYSCTL_SYSDIV_3
SYSCTL_SYSDIV_4
SYSCTL_SYSDIV_5
SYSCTL_SYSDIV_6
SYSCTL_SYSDIV_7
SYSCTL_SYSDIV_8
SYSCTL_SYSDIV_9
SYSCTL_SYSDIV_10
SYSCTL_SYSDIV_11
SYSCTL_SYSDIV_12
SYSCTL_SYSDIV_13
SYSCTL_SYSDIV_14
SYSCTL_SYSDIV_15
SYSCTL_SYSDIV_16
SYSCTL_SYSDIV_17
SYSCTL_SYSDIV_18
SYSCTL_SYSDIV_19
SYSCTL_SYSDIV_20
SYSCTL_SYSDIV_21
SYSCTL_SYSDIV_22
SYSCTL_SYSDIV_23
SYSCTL_SYSDIV_24
SYSCTL_SYSDIV_25
SYSCTL_SYSDIV_26
SYSCTL_SYSDIV_27
SYSCTL_SYSDIV_28
SYSCTL_SYSDIV_29
SYSCTL_SYSDIV_30
SYSCTL_SYSDIV_31
SYSCTL_SYSDIV_32
SYSCTL_SYSDIV_33
SYSCTL_SYSDIV_34
SYSCTL_SYSDIV_35
SYSCTL_SYSDIV_36
SYSCTL_SYSDIV_37
SYSCTL_SYSDIV_38
SYSCTL_SYSDIV_39
SYSCTL_SYSDIV_40
SYSCTL_SYSDIV_41
SYSCTL_SYSDIV_42
SYSCTL_SYSDIV_43
SYSCTL_SYSDIV_44
SYSCTL_SYSDIV_45
SYSCTL_SYSDIV_46
SYSCTL_SYSDIV_47
SYSCTL_SYSDIV_48
SYSCTL_SYSDIV_49
SYSCTL_SYSDIV_50
SYSCTL_SYSDIV_51
SYSCTL_SYSDIV_52
SYSCTL_SYSDIV_53
SYSCTL_SYSDIV_54
SYSCTL_SYSDIV_55
SYSCTL_SYSDIV_56
SYSCTL_SYSDIV_57
SYSCTL_SYSDIV_58
SYSCTL_SYSDIV_59
SYSCTL_SYSDIV_60
SYSCTL_SYSDIV_61
SYSCTL_SYSDIV_62
SYSCTL_SYSDIV_63
SYSCTL_SYSDIV_64

SysCtl_XClkSource

enum SysCtl_XClkSource

The following are values that can be passed to SysCtl_selectClockOutSource() as the source parameter.

Enumerator
SYSCTL_XCLKOUT_SOURCE_PLLSYS	PLL System Clock post SYSCLKDIV.
SYSCTL_XCLKOUT_SOURCE_CPU1CLK	CPU1.CLOCK.
SYSCTL_XCLKOUT_SOURCE_CPU2CLK	CPU2.CLOCK.
SYSCTL_XCLKOUT_SOURCE_CPU3CLK	CPU3.CLOCK.
SYSCTL_XCLKOUT_SOURCE_INTOSC1	Internal Oscillator 1.
SYSCTL_XCLKOUT_SOURCE_INTOSC2	Internal Oscillator 2.
SYSCTL_XCLKOUT_SOURCE_XTALOSC	External Oscillator.

SysCtl_XClkDivider

enum SysCtl_XClkDivider

The following are values that can be passed to SysCtl_setXClk() as divider parameter.

Enumerator
SYSCTL_XCLKOUT_DIV_1	XCLKOUT = XCLKOUT source / 1.
SYSCTL_XCLKOUT_DIV_2	XCLKOUT = XCLKOUT source / 2.
SYSCTL_XCLKOUT_DIV_4	XCLKOUT = XCLKOUT source / 4.
SYSCTL_XCLKOUT_DIV_8	XCLKOUT = XCLKOUT source / 8.

SysCtl_MCANInstance

enum SysCtl_MCANInstance

The following are values that can be passed to SysCtl_setMCANClock() as mcanInst parameter.

Enumerator
SYSCTL_MCAN_A
SYSCTL_MCAN_B
SYSCTL_MCAN_C
SYSCTL_MCAN_D
SYSCTL_MCAN_E
SYSCTL_MCAN_F

SysCtl_MCANClkSource

enum SysCtl_MCANClkSource

The following are values that can be passed to SysCtl_setMCANClock() as clksrc parameter.

Enumerator
SYSCTL_MCANCLK_SOURCE_SYS
SYSCTL_MCANCLK_SOURCE_AUXIN	Peripheral System Clock Source.
SYSCTL_MCANCLK_SOURCE_PLLRAW	Auxiliary Clock Input Source (GPIO)

SysCtl_MCANClkDivider

enum SysCtl_MCANClkDivider

The following are values that can be passed to SysCtl_setMCANClock() as divider parameter.

Enumerator
SYSCTL_MCANCLK_DIV_1	MCAN clock = MCAN clock source / 1.
SYSCTL_MCANCLK_DIV_2	MCAN clock = MCAN clock source / 2.
SYSCTL_MCANCLK_DIV_3	MCAN clock = MCAN clock source / 3.
SYSCTL_MCANCLK_DIV_4	MCAN clock = MCAN clock source / 4.
SYSCTL_MCANCLK_DIV_5	MCAN clock = MCAN clock source / 5.
SYSCTL_MCANCLK_DIV_6	MCAN clock = MCAN clock source / 6.
SYSCTL_MCANCLK_DIV_7	MCAN clock = MCAN clock source / 7.
SYSCTL_MCANCLK_DIV_8	MCAN clock = MCAN clock source / 8.
SYSCTL_MCANCLK_DIV_9	MCAN clock = MCAN clock source / 9.
SYSCTL_MCANCLK_DIV_10	MCAN clock = MCAN clock source / 10.
SYSCTL_MCANCLK_DIV_11	MCAN clock = MCAN clock source / 11.
SYSCTL_MCANCLK_DIV_12	MCAN clock = MCAN clock source / 12.
SYSCTL_MCANCLK_DIV_13	MCAN clock = MCAN clock source / 13.
SYSCTL_MCANCLK_DIV_14	MCAN clock = MCAN clock source / 14.
SYSCTL_MCANCLK_DIV_15	MCAN clock = MCAN clock source / 15.
SYSCTL_MCANCLK_DIV_16	MCAN clock = MCAN clock source / 16.
SYSCTL_MCANCLK_DIV_17	MCAN clock = MCAN clock source / 17.
SYSCTL_MCANCLK_DIV_18	MCAN clock = MCAN clock source / 18.
SYSCTL_MCANCLK_DIV_19	MCAN clock = MCAN clock source / 19.
SYSCTL_MCANCLK_DIV_20	MCAN clock = MCAN clock source / 20.

SysCtl_Cputimer2ClkSource

enum SysCtl_Cputimer2ClkSource

The following are values that can be passed to SysCtl_setCputimer2Clock() as source parameter.

Enumerator
SYSCTL_TIMER2CLK_SOURCE_SYSCLK	System Clock.
SYSCTL_TIMER2CLK_SOURCE_INTOSC1	Internal Oscillator 1.
SYSCTL_TIMER2CLK_SOURCE_INTOSC2	Internal Oscillator 2.
SYSCTL_TIMER2CLK_SOURCE_XTAL	Crystal oscillator.

SysCtl_Cputimer2ClkDivider

enum SysCtl_Cputimer2ClkDivider

The following are values that can be passed to SysCtl_setCputimer2Clk() as divider parameter.

Enumerator
SYSCTL_TIMER2CLK_DIV_1	Cputimer2 clock = Cputimer2 clock / 1.
SYSCTL_TIMER2CLK_DIV_2	Cputimer2 clock = Cputimer2 clock / 2.
SYSCTL_TIMER2CLK_DIV_4	Cputimer2 clock = Cputimer2 clock / 4.
SYSCTL_TIMER2CLK_DIV_8	Cputimer2 clock = Cputimer2 clock / 8.
SYSCTL_TIMER2CLK_DIV_16	Cputimer2 clock = Cputimer2 clock / 16.

SysCtl_EPWMClkDivider

enum SysCtl_EPWMClkDivider

The following are values that can be passed to SysCtl_setEPWMClockDivider() as the divider parameter.

Enumerator
SYSCTL_EPWMCLK_DIV_1	EPWMCLK = PLLSYSCLK / 1.
SYSCTL_EPWMCLK_DIV_2	EPWMCLK = PLLSYSCLK / 2.

SysCtl_EMIFClkDivider

enum SysCtl_EMIFClkDivider

The following are values that can be passed to SysCtl_setEMIF1Clock() as the divider parameter.

Enumerator
SYSCTL_EMIFCLK_DIV_1	EMIF1CLK = PLLSYSCLK / 1.
SYSCTL_EMIFCLK_DIV_2	EMIF1CLK = PLLSYSCLK / 2.
SYSCTL_EMIFCLK_DIV_4	EMIF1CLK = PLLSYSCLK / 4.

SysCtl_LINClkDivider

enum SysCtl_LINClkDivider

The following are values that can be passed to SysCtl_setLINAClockDivider() as the divider parameter.

Enumerator
SYSCTL_LINCLK_DIV_1	LINACLK = PLLSYSCLK / 1.
SYSCTL_LINCLK_DIV_2	LINACLK = PLLSYSCLK / 2.
SYSCTL_LINCLK_DIV_4	LINACLK = PLLSYSCLK / 4.

SysCtl_ECatClkDivider

enum SysCtl_ECatClkDivider

The following are values that can be passed to SysCtl_setECatClock() as divider parameter.

Enumerator
SYSCTL_ECATCLKOUT_DIV_1	ECat clock = PLLCLK / 1.
SYSCTL_ECATCLKOUT_DIV_2	ECat clock = PLLCLK / 2.
SYSCTL_ECATCLKOUT_DIV_3	ECat clock = PLLCLK / 3.
SYSCTL_ECATCLKOUT_DIV_4	ECat clock = PLLCLK / 4.
SYSCTL_ECATCLKOUT_DIV_5	ECat clock = PLLCLK / 5.
SYSCTL_ECATCLKOUT_DIV_6	ECat clock = PLLCLK / 6.
SYSCTL_ECATCLKOUT_DIV_7	ECat clock = PLLCLK / 7.
SYSCTL_ECATCLKOUT_DIV_8	ECat clock = PLLCLK / 8.

SysCtl_ECatPhyClk

enum SysCtl_ECatPhyClk

The following are values that can be passed to SysCtl_setECatClock() as divider parameter.

Enumerator
SYSCTL_ECAT_PHYCLK_ENABLE
SYSCTL_ECAT_PHYCLK_DISABLE

SysCtl_CLBClkDivider

enum SysCtl_CLBClkDivider

The following are values that can be passed to SysCtl_setCLBClock() as divider parameter.

Enumerator
SYSCTL_CLBCLKOUT_DIV_1	CLB clock = CLB clock / 1.
SYSCTL_CLBCLKOUT_DIV_2	CLB clock = CLB clock / 2.
SYSCTL_CLBCLKOUT_DIV_3	CLB clock = CLB clock / 3.
SYSCTL_CLBCLKOUT_DIV_4	CLB clock = CLB clock / 4.
SYSCTL_CLBCLKOUT_DIV_5	CLB clock = CLB clock / 5.
SYSCTL_CLBCLKOUT_DIV_6	CLB clock = CLB clock / 6.
SYSCTL_CLBCLKOUT_DIV_7	CLB clock = CLB clock / 7.
SYSCTL_CLBCLKOUT_DIV_8	CLB clock = CLB clock / 8.

SysCtl_CLBTClkDivider

enum SysCtl_CLBTClkDivider

The following are values that can be passed to SysCtl_setCLBClock() as tdivider parameter.

Enumerator
SYSCTL_CLBTCLKOUT_DIV_1	CLBTCLKOUT = CLB clock / 1.
SYSCTL_CLBTCLKOUT_DIV_2	CLBTCLKOUT = CLB clock / 2.

SysCtl_HSMClkDivider

enum SysCtl_HSMClkDivider

The following are values that can be passed to SysCtl_setHSMClock() as divider parameter.

Enumerator
SYSCTL_HSMCLK_DIV_1	HSM Clock = HSM clock / 1.
SYSCTL_HSMCLK_DIV_2	HSM Clock = HSM clock / 2.
SYSCTL_HSMCLK_DIV_4	HSM Clock = HSM clock / 4.
SYSCTL_HSMCLK_DIV_8	HSM Clock = HSM clock / 8.
SYSCTL_HSMCLK_DIV_16	HSM Clock = HSM clock / 16.

Function Documentation

SysCtl_pollSyncBusy()

void SysCtl_pollSyncBusy ( uint32_t mask )

extern

SysCtl_enableMCD()

static void SysCtl_enableMCD ( void )

inlinestatic

Enable the missing clock detection (MCD) Logic

Returns

None.

SysCtl_disableMCD()

static void SysCtl_disableMCD ( void )

inlinestatic

Disable the missing clock detection (MCD) Logic

Returns

None.

SysCtl_isMCDClockFailureDetected()

static bool SysCtl_isMCDClockFailureDetected ( void )

inlinestatic

Get the missing clock detection Failure Status

Note

A failure means the oscillator clock is missing

Returns

Returns true if a failure is detected or false if a failure isn't detected

SysCtl_resetMCD()

static void SysCtl_resetMCD ( void )

inlinestatic

Reset the missing clock detection logic after clock failure

Returns

None.

SysCtl_connectMCDClockSource()

static void SysCtl_connectMCDClockSource ( void )

inlinestatic

Re-connect missing clock detection clock source to stop simulating clock failure

Returns

None.

SysCtl_disconnectMCDClockSource()

static void SysCtl_disconnectMCDClockSource ( void )

inlinestatic

Disconnect missing clock detection clock source to simulate clock failure. This is for testing the MCD functionality.

Returns

None.

SysCtl_setXClk()

static void SysCtl_setXClk ( SysCtl_XClkSource clksrc, SysCtl_XClkDivider divider )

inlinestatic

Sets up XCLK (External Clock out)

Parameters

clksrc	is the clock source to be used for the External Clock out
divider	is the clock divider to be used

This function configures the specified clock source to be muxed to an external clock out (XCLKOUT) GPIO pin.

The clksrc arameter can have one enumerated value from SysCtl_XClkSource The divider parameter can have one enumerated value from SysCtl_XClkDivider

Returns

None.

SysCtl_delay69Cycles()

static void SysCtl_delay69Cycles ( void )

inlinestatic

SysCtl_setMCANClock()

static void SysCtl_setMCANClock ( SysCtl_MCANInstance mcanInst, SysCtl_MCANClkSource clksrc, SysCtl_MCANClkDivider divider )

inlinestatic

Sets up MCAN Clock.

Parameters

mcanInst	is the MCAN instance
clksrc	is the clock source to be used for the MCAN instance
divider	is the clock divider to be used

This function sets up the MCANCLK divider. There is only one divider that scales MCAN clock.

The mcanInst parameter can have one enumerated value from SysCtl_MCANInstance The clksrc arameter can have one enumerated value from SysCtl_MCANClkSource The divider parameter can have one enumerated value from SysCtl_MCANClkDivider

Returns

None.

SysCtl_setCputimer2Clock()

static void SysCtl_setCputimer2Clock ( SysCtl_Cputimer2ClkSource source, SysCtl_Cputimer2ClkDivider divider )

inlinestatic

Sets up CPU Timer 2 Clock.

Parameters

divider	is the value that configures the divider.
source	is the source for the clock divider

This function sets up the CPU Timer 2 CLK divider based on the source that is selected. There is only one divider that scales the "source" to CPU Timer 2 CLK.

The divider parameter can have one enumerated value from SysCtl_Cputimer2ClkDivider The source parameter can have one enumerated value from SysCtl_Cputimer2ClkSource

Returns

None.

SysCtl_setEPWMClock()

static void SysCtl_setEPWMClock ( SysCtl_EPWMClkDivider divider )

inlinestatic

Sets the ePWM clock.

Parameters

divider

is the value by which PLLSYSCLK is divided

This function configures the clock rate of the EPWMCLK. The divider parameter is the value by which the SYSCLK rate is divided to get the EPWMCLK rate. For example, SYSCTL_EPWMCLK_DIV_2 will select an EPWMCLK rate that is half the PLLSYSCLK rate.

Returns

None.

SysCtl_setEMIF1Clock()

static void SysCtl_setEMIF1Clock ( SysCtl_EMIFClkDivider divider )

inlinestatic

Sets the EMIF1 clock.

Parameters

divider

is the value by which PLLSYSCLK (or CPU1.SYSCLK on a dual core device) is divided

This function configures the clock rate of the EMIF1CLK. The divider parameter is the value by which the SYSCLK rate is divided to get the EMIF1CLK rate.

Returns

None.

SysCtl_setLINAClock()

static void SysCtl_setLINAClock ( SysCtl_LINClkDivider divider )

inlinestatic

Sets the LINA clock divider.

Parameters

divider

is the value by which PLLSYSCLK is divided

This function configures the clock rate of the LINACLK. The divider parameter is the value by which the SYSCLK rate is divided to get the LINACLK rate.

Returns

None.

SysCtl_setLINBClock()

static void SysCtl_setLINBClock ( SysCtl_LINClkDivider divider )

inlinestatic

Sets the LINB clock.

Parameters

divider

is the value by which PLLSYSCLK is divided

This function configures the clock rate of the LINBCLK. The divider parameter is the value by which the SYSCLK rate is divided to get the LINBCLK rate.

Returns

None.

SysCtl_setECatClock()

static void SysCtl_setECatClock ( SysCtl_ECatClkDivider divider, SysCtl_ECatPhyClk phyEnable )

inlinestatic

Sets up Ethercat clock.

Parameters

divider	is the value that configures the divider.
phyEnable	enables/disables the etherCAT PHY clock

This function sets up the Ethercat CLK divider based on the source that is selected. There is only one divider that scales the "source" to Ethercat CLK. This also enables/disables the etherCAT PHY clock.

The divider parameter can have one enumerated value from SysCtl_ECatClkDivider The source parameter can have one enumerated value from SysCtl_PLLClockSource The enable parameter can be either of these values: 0x0U: etherCAT PHY clock is disabled 0x1U: etherCAT PHY clock is enabled

Returns

None.

SysCtl_setCLBClock()

static void SysCtl_setCLBClock ( SysCtl_CLBClkDivider divider, SysCtl_CLBTClkDivider tdivider, uint32_t clkMode )

inlinestatic

Sets the CLB clock divider.

Parameters

divider	is the CLB clock divider.
tdivider	is the CLB tile clock divider.
clkMode	is the mode for the clock for each of the instances

This function sets up the CLB CLK configurations based on the instance that is selected. There are 2 dividers that scales the "source" to CLB CLK. The first one is the divider & the other the tile divider.

The divider parameter can have one enumerated value from SysCtl_CLBClkDivider The tdivider parameter can have one enumerated value from SysCtl_CLBTClkDivider The clkMode parameter can be ORed value of :

• SYSCTL_CLB1CLKMODE_SYNC or SYSCTL_CLB1CLKMODE_ASYNC
• SYSCTL_CLB2CLKMODE_SYNC or SYSCTL_CLB2CLKMODE_ASYNC
• SYSCTL_CLB3CLKMODE_SYNC or SYSCTL_CLB3CLKMODE_ASYNC
• SYSCTL_CLB4CLKMODE_SYNC or SYSCTL_CLB4CLKMODE_ASYNC
• SYSCTL_CLB5CLKMODE_SYNC or SYSCTL_CLB5CLKMODE_ASYNC
• SYSCTL_CLB6CLKMODE_SYNC or SYSCTL_CLB6CLKMODE_ASYNC

Returns

None.

SysCtl_setHSMClock()

static void SysCtl_setHSMClock ( SysCtl_HSMClkDivider divider )

inlinestatic

Sets the HSM clock.

Parameters

divider

is the value by which PLLSYSCLK is divided

This function configures the clock rate of the HSMCLK. The divider parameter is the value by which the SYSCLK rate is divided to get the HSMCLK rate.

Returns

None.

SysCtl_getExternalOscCounterValue()

static uint16_t SysCtl_getExternalOscCounterValue ( void )

inlinestatic

Gets the external oscillator counter value.

This function returns the X1 clock counter value. When the return value reaches 0x3FF, it freezes. Before switching from INTOSC2 to an external oscillator (XTAL), an application should call this function to make sure the counter is saturated.

Returns

Returns the value of the 10-bit X1 clock counter.

SysCtl_clearExternalOscCounterValue()

static void SysCtl_clearExternalOscCounterValue ( void )

inlinestatic

Clears the external oscillator counter value.

Returns

None.

SysCtl_turnOnXTAL()

static void SysCtl_turnOnXTAL ( void )

inlinestatic

Turns on the the XTAL oscillator.

Returns

None.

SysCtl_turnOffXTAL()

static void SysCtl_turnOffXTAL ( void )

inlinestatic

Turns off the the XTAL oscillator.

Returns

None.

SysCtl_getClock()

uint32_t SysCtl_getClock ( uint32_t clockInHz )

extern

Calculates the system clock frequency (SYSCLK).

Parameters

clockInHz

is the frequency of the oscillator clock source (OSCCLK).

This function determines the frequency of the system clock based on the frequency of the oscillator clock source (from clockInHz) and the PLL and clock divider configuration registers.

Returns

Returns the system clock frequency. If a missing clock is detected, the function will return the INTOSC1 frequency. This needs to be corrected and cleared (see SysCtl_resetMCD()) before trying to call this function again.

SysCtl_setClock()

bool SysCtl_setClock ( Sysctl_PLLClockSource oscSrc, Sysctl_PLLConfig pllConfig, Sysctl_PLLRefDiv refDiv, Sysctl_PLLIMult iMult, Sysctl_PLLODiv oDiv, Sysctl_PLLSysDiv sysDiv, uint32_t dccBase, uint32_t oscClk )

extern

Configures the clocking of the device.

Parameters

config

is the required configuration of the device clocking.

This function configures the clocking of the device. The input crystal frequency, oscillator to be used, use of the PLL, and the system clock divider are all configured with this function.

Parameters

oscSrc	PLL Source. Can be one of the following values : SYSCTL_OSCSRC_OSC2 - Internal Oscillator 2 SYSCTL_OSCSRC_XTAL - External XTAL SYSCTL_OSCSRC_XTAL_SE - External XTAL Single-ended mode SYSCTL_OSCSRC_OSC1 - Internal Oscillator 1
pllConfig	PLL configuration. Can be one fo the following values : SYSCTL_PLL_ENABLE - This is to Enable the PLL Clock to the System SYSCTL_PLL_BYPASS - This is to Bypass the PLLCLK from the System, this will also power up the PLL if the user desires to power up the PLL but not use it for System. SYSCTL_PLL_DISABLE - This is to Power Down the PLL and Bypass the PLLCLK to the System.
refDiv	Reference Clock Divider. Use Enum SYSCTL_REFDIV_1..32
iMult	Multiplier. Use Enum SYSCTL_IMULT_4..255
oDiv	Output Clock Divider. Use Enum SYSCTL_ODIV_1..32
sysDiv	SYSCLK Divider. Use Enum SYSCTL_SYSDIV_1..64
dccBase	Base address of DCC module for PLL output validation

This function uses the DCC to check that the PLLRAWCLK is running at the expected rate. If you are using the DCC, you must back up its configuration before calling this function and restore it afterward. Locking PLL sequence is only done if the multipliers are updated.

Note

See your device errata for more details about locking the PLL.

Returns

Returns false if a missing clock error is detected. This needs to be cleared (see SysCtl_resetMCD()) before trying to call this function again. Also, returns false if the PLLRAWCLK is not running at its expected rate. Otherwise, returns true.

SysCtl_selectOscSource()

bool SysCtl_selectOscSource ( uint32_t oscSource, uint32_t oscClk, uint32_t dccBase )

extern

Selects the oscillator to be used for the clocking of the device.

Parameters

oscSource

is the oscillator source to be configured.

This function configures the oscillator to be used in the clocking of the device. The oscSource parameter may take a value of SYSCTL_OSCSRC_OSC2, SYSCTL_OSCSRC_XTAL, SYSCTL_OSCSRC_XTAL_SE, or SYSCTL_OSCSRC_OSC1.

See also

SysCtl_turnOnOsc()

Returns

None.