Introduction

Functions
static bool	CLB_isBaseValid (uint32_t base)

static bool	CLB_isAddressValid (uint32_t address)

static void	CLB_enableCLB (uint32_t base)

static void	CLB_disableCLB (uint32_t base)

static void	CLB_enableNMI (uint32_t base)

static void	CLB_disableNMI (uint32_t base)

static void	CLB_configureClockPrescalar (uint32_t base, uint16_t prescl)

static void	CLB_configureStrobeMode (uint32_t base, uint16_t strb)

static void	CLB_writeSWReleaseControl (uint32_t base, CLB_SWReleaseCtrl inID, bool val)

static void	CLB_writeSWGateControl (uint32_t base, CLB_SWGateCtrl inID, bool val)

static void	CLB_configCounterTapSelects (uint32_t base, uint32_t tapSel)

static void	CLB_configAOC (uint32_t base, CLB_AOCs aocID, uint32_t aocCfg)

static void	CLB_enableLock (uint32_t base)

static void	CLB_writeInterface (uint32_t base, uint32_t address, uint32_t value)

static void	CLB_selectInputFilter (uint32_t base, CLB_Inputs inID, CLB_FilterType filterType)

static void	CLB_enableSynchronization (uint32_t base, CLB_Inputs inID)

static void	CLB_disableSynchronization (uint32_t base, CLB_Inputs inID)

static void	CLB_configGPInputMux (uint32_t base, CLB_Inputs inID, CLB_GPInputMux gpMuxCfg)

static void	CLB_setGPREG (uint32_t base, uint32_t gpRegVal)

static uint32_t	CLB_getGPREG (uint32_t base)

static void	CLB_configLocalInputMux (uint32_t base, CLB_Inputs inID, CLB_LocalInputMux localMuxCfg)

static void	CLB_configGlobalInputMux (uint32_t base, CLB_Inputs inID, CLB_GlobalInputMux globalMuxCfg)

static void	CLB_setOutputMask (uint32_t base, uint32_t outputMask, bool enable)

static uint16_t	CLB_getInterruptTag (uint32_t base)

static void	CLB_clearInterruptTag (uint32_t base)

static void	CLB_selectLUT4Inputs (uint32_t base, uint32_t lut4In0, uint32_t lut4In1, uint32_t lut4In2, uint32_t lut4In3)

static void	CLB_configLUT4Function (uint32_t base, uint32_t lut4Fn10, uint32_t lut4Fn2)

static void	CLB_selectFSMInputs (uint32_t base, uint32_t external0, uint32_t external1, uint32_t extra0, uint32_t extra1)

static void	CLB_configFSMLUTFunction (uint32_t base, uint32_t fsmLutFn10, uint32_t fsmLutFn2)

static void	CLB_configFSMNextState (uint32_t base, uint32_t nextState0, uint32_t nextState1, uint32_t nextState2)

static void	CLB_selectCounterInputs (uint32_t base, uint32_t reset, uint32_t event, uint32_t mode0, uint32_t mode1)

static void	CLB_configMiscCtrlModes (uint32_t base, uint32_t miscCtrl)

static void	CLB_configOutputLUT (uint32_t base, CLB_Outputs outID, uint32_t outputCfg)

static void	CLB_configHLCEventSelect (uint32_t base, uint32_t eventSel)

static void	CLB_programHLCInstruction (uint32_t base, uint32_t instructionNum, uint32_t instruction)

static void	CLB_setHLCRegisters (uint32_t base, uint32_t r0Init, uint32_t r1Init, uint32_t r2Init, uint32_t r3Init)

static uint32_t	CLB_getRegister (uint32_t base, CLB_Register registerID)

static uint32_t	CLB_getOutputStatus (uint32_t base)

static void	CLB_enablePipelineMode (uint32_t base)

static void	CLB_disablePipelineMode (uint32_t base)

static void	CLB_disableOutputMaskUpdates (uint32_t base)

static void	CLB_enableOutputMaskUpdates (uint32_t base)

static void	CLB_enableInputPipelineMode (uint32_t base, CLB_Inputs inID)

static void	CLB_disableInputPipelineMode (uint32_t base, CLB_Inputs inID)

static void	CLB_disableSPIBufferAccess (uint32_t base)

static void	CLB_enableSPIBufferAccess (uint32_t base)

static void	CLB_configSPIBufferLoadSignal (uint32_t base, uint16_t eventSel)

static void	CLB_configSPIBufferShift (uint32_t base, uint16_t shiftVal)

static void	CLB_enableSPIStrobeDelay (uint32_t base)

static void	CLB_disableSPIStrobeDelay (uint32_t base)

void	CLB_configCounterLoadMatch (uint32_t base, CLB_Counters counterID, uint32_t load, uint32_t match1, uint32_t match2)

void	CLB_clearFIFOs (uint32_t base)

void	CLB_writeFIFOs (uint32_t base, const uint32_t pullData[])

void	CLB_readFIFOs (uint32_t base, uint32_t pushData[])

Enumerations
enum	CLB_Inputs { CLB_IN0 = 0 , CLB_IN1 = 1 , CLB_IN2 = 2 , CLB_IN3 = 3 , CLB_IN4 = 4 , CLB_IN5 = 5 , CLB_IN6 = 6 , CLB_IN7 = 7 }
	Values that can be passed to select CLB input signal. More...

enum	CLB_Outputs { CLB_OUT0 = 0 , CLB_OUT1 = 1 , CLB_OUT2 = 2 , CLB_OUT3 = 3 , CLB_OUT4 = 4 , CLB_OUT5 = 5 , CLB_OUT6 = 6 , CLB_OUT7 = 7 }

enum	CLB_AOCs { CLB_AOC0 = 0 , CLB_AOC1 = 1 , CLB_AOC2 = 2 , CLB_AOC3 = 3 , CLB_AOC4 = 4 , CLB_AOC5 = 5 , CLB_AOC6 = 6 , CLB_AOC7 = 7 }

enum	CLB_SWReleaseCtrl { CLB_SW_RLS_CTRL0 = 0 , CLB_SW_RLS_CTRL1 = 1 , CLB_SW_RLS_CTRL2 = 2 , CLB_SW_RLS_CTRL3 = 3 , CLB_SW_RLS_CTRL4 = 4 , CLB_SW_RLS_CTRL5 = 5 , CLB_SW_RLS_CTRL6 = 6 , CLB_SW_RLS_CTRL7 = 7 }

enum	CLB_SWGateCtrl { CLB_SW_GATE_CTRL0 = 0 , CLB_SW_GATE_CTRL1 = 1 , CLB_SW_GATE_CTRL2 = 2 , CLB_SW_GATE_CTRL3 = 3 , CLB_SW_GATE_CTRL4 = 4 , CLB_SW_GATE_CTRL5 = 5 , CLB_SW_GATE_CTRL6 = 6 , CLB_SW_GATE_CTRL7 = 7 }

enum	CLB_Counters { CLB_CTR0 = 0 , CLB_CTR1 = 1 , CLB_CTR2 = 2 }

enum	CLB_Register { CLB_REG_HLC_R0 = CLB_O_DBG_R0 , CLB_REG_HLC_R1 = CLB_O_DBG_R1 , CLB_REG_HLC_R2 = CLB_O_DBG_R2 , CLB_REG_HLC_R3 = CLB_O_DBG_R3 , CLB_REG_CTR_C0 = CLB_O_DBG_C0 , CLB_REG_CTR_C1 = CLB_O_DBG_C1 , CLB_REG_CTR_C2 = CLB_O_DBG_C2 }

enum	CLB_FilterType { CLB_FILTER_NONE = 0 , CLB_FILTER_RISING_EDGE = 1 , CLB_FILTER_FALLING_EDGE = 2 , CLB_FILTER_ANY_EDGE = 3 }

enum	CLB_GPInputMux { CLB_GP_IN_MUX_EXTERNAL = 0 , CLB_GP_IN_MUX_GP_REG = 1 }

enum	CLB_LocalInputMux { CLB_LOCAL_IN_MUX_GLOBAL_IN = 0 , CLB_LOCAL_IN_MUX_EPWM_DCAEVT1 = 1 , CLB_LOCAL_IN_MUX_EPWM_DCAEVT2 = 2 , CLB_LOCAL_IN_MUX_EPWM_DCBEVT1 = 3 , CLB_LOCAL_IN_MUX_EPWM_DCBEVT2 = 4 , CLB_LOCAL_IN_MUX_EPWM_DCAH = 5 , CLB_LOCAL_IN_MUX_EPWM_DCAL = 6 , CLB_LOCAL_IN_MUX_EPWM_DCBH = 7 , CLB_LOCAL_IN_MUX_EPWM_DCBL = 8 , CLB_LOCAL_IN_MUX_EPWM_OST = 9 , CLB_LOCAL_IN_MUX_EPWM_CBC = 10 , CLB_LOCAL_IN_MUX_ECAP_ECAPIN = 11 , CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT = 12 , CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT_EN = 13 , CLB_LOCAL_IN_MUX_ECAP_CEVT1 = 14 , CLB_LOCAL_IN_MUX_ECAP_CEVT2 = 15 , CLB_LOCAL_IN_MUX_ECAP_CEVT3 = 16 , CLB_LOCAL_IN_MUX_ECAP_CEVT4 = 17 , CLB_LOCAL_IN_MUX_EQEP_EQEPA = 18 , CLB_LOCAL_IN_MUX_FSI_DATA_PKT_RCVD = 18 , CLB_LOCAL_IN_MUX_EQEP_EQEPB = 19 , CLB_LOCAL_IN_MUX_FSI_ERROR_PKT_RCVD = 19 , CLB_LOCAL_IN_MUX_EQEP_EQEPI = 20 , CLB_LOCAL_IN_MUX_FSI_PING_PKT_RCVD = 20 , CLB_LOCAL_IN_MUX_EQEP_EQEPS = 21 , CLB_LOCAL_IN_MUX_CPU3_HALT = 21 , CLB_LOCAL_IN_MUX_CPU1_TBCLKSYNC = 22 , CLB_LOCAL_IN_MUX_CPU3_TBCLKSYNC = 23 , CLB_LOCAL_IN_MUX_CPU2_TBCLKSYNC = 23 , CLB_LOCAL_IN_MUX_CPU1_HALT = 24 , CLB_LOCAL_IN_MUX_SPIPICO_CONTROLLER = 25 , CLB_LOCAL_IN_MUX_SPICLK = 26 , CLB_LOCAL_IN_MUX_SPIPICO_PERIPHERAL = 27 , CLB_LOCAL_IN_MUX_SPIPTE = 28 , CLB_LOCAL_IN_MUX_SPIPOCI_OUT = 30 , CLB_LOCAL_IN_MUX_CLB_PSCLK = 31 , CLB_LOCAL_IN_MUX_EPWM9A = 32 , CLB_LOCAL_IN_MUX_ECAP5_ECAPIN = 32 , CLB_LOCAL_IN_MUX_ECAP6_ECAPIN = 32 , CLB_LOCAL_IN_MUX_EPWM9A_OE = 33 , CLB_LOCAL_IN_MUX_ECAP5_ECAP_OUT = 33 , CLB_LOCAL_IN_MUX_ECAP6_ECAP_OUT = 33 , CLB_LOCAL_IN_MUX_EPWM9B = 34 , CLB_LOCAL_IN_MUX_ECAP5_ECAP_OUT_EN = 34 , CLB_LOCAL_IN_MUX_ECAP6_ECAP_OUT_EN = 34 , CLB_LOCAL_IN_MUX_EPWM9B_OE = 35 , CLB_LOCAL_IN_MUX_ECAP5_CEVT1 = 35 , CLB_LOCAL_IN_MUX_ECAP6_CEVT1 = 35 , CLB_LOCAL_IN_MUX_EPWM10A = 36 , CLB_LOCAL_IN_MUX_ECAP5_CEVT2 = 36 , CLB_LOCAL_IN_MUX_ECAP6_CEVT2 = 36 , CLB_LOCAL_IN_MUX_EPWM10A_OE = 37 , CLB_LOCAL_IN_MUX_ECAP5_CEVT3 = 37 , CLB_LOCAL_IN_MUX_ECAP6_CEVT3 = 37 , CLB_LOCAL_IN_MUX_EPWM10B = 38 , CLB_LOCAL_IN_MUX_ECAP5_CEVT4 = 38 , CLB_LOCAL_IN_MUX_ECAP6_CEVT4 = 38 , CLB_LOCAL_IN_MUX_EPWM10B_OE = 39 , CLB_LOCAL_IN_MUX_ECAP5_ECAPIN0 = 39 , CLB_LOCAL_IN_MUX_ECAP6_ECAPIN0 = 39 , CLB_LOCAL_IN_MUX_EPWM11A = 40 , CLB_LOCAL_IN_MUX_EQEP5_EQEPA = 40 , CLB_LOCAL_IN_MUX_EQEP6_EQEPA = 40 , CLB_LOCAL_IN_MUX_EPWM11A_OE = 41 , CLB_LOCAL_IN_MUX_EQEP5_EQEPB = 41 , CLB_LOCAL_IN_MUX_EQEP6_EQEPB = 41 , CLB_LOCAL_IN_MUX_EPWM11B = 42 , CLB_LOCAL_IN_MUX_EQEP5_EQEPI = 42 , CLB_LOCAL_IN_MUX_EQEP6_EQEPI = 42 , CLB_LOCAL_IN_MUX_EPWM11B_OE = 43 , CLB_LOCAL_IN_MUX_EQEP5_EQEPS = 43 , CLB_LOCAL_IN_MUX_EQEP6_EQEPS = 43 , CLB_LOCAL_IN_MUX_EPWM12A = 44 , CLB_LOCAL_IN_MUX_EPWM16A = 44 , CLB_LOCAL_IN_MUX_EPWM12A_OE = 45 , CLB_LOCAL_IN_MUX_EPWM16A_OE = 45 , CLB_LOCAL_IN_MUX_EPWM12B = 46 , CLB_LOCAL_IN_MUX_EPWM16B = 46 , CLB_LOCAL_IN_MUX_EPWM12B_OE = 47 , CLB_LOCAL_IN_MUX_EPWM16B_OE = 47 , CLB_LOCAL_IN_MUX_INPUT17 = 48 , CLB_LOCAL_IN_MUX_INPUT18 = 49 , CLB_LOCAL_IN_MUX_INPUT19 = 50 , CLB_LOCAL_IN_MUX_INPUT20 = 51 , CLB_LOCAL_IN_MUX_INPUT21 = 52 , CLB_LOCAL_IN_MUX_INPUT22 = 53 , CLB_LOCAL_IN_MUX_INPUT23 = 54 , CLB_LOCAL_IN_MUX_INPUT24 = 55 , CLB_LOCAL_IN_MUX_INPUT25 = 56 , CLB_LOCAL_IN_MUX_INPUT26 = 57 , CLB_LOCAL_IN_MUX_INPUT27 = 58 , CLB_LOCAL_IN_MUX_INPUT28 = 59 , CLB_LOCAL_IN_MUX_INPUT29 = 60 , CLB_LOCAL_IN_MUX_INPUT30 = 61 , CLB_LOCAL_IN_MUX_INPUT31 = 62 , CLB_LOCAL_IN_MUX_INPUT32 = 63 }

enum	CLB_GlobalInputMux { CLB_GLOBAL_IN_MUX_EPWM1A = 0 , CLB_GLOBAL_IN_MUX_EPWM5A = 0 , CLB_GLOBAL_IN_MUX_EPWM1A_OE = 1 , CLB_GLOBAL_IN_MUX_EPWM5A_OE = 1 , CLB_GLOBAL_IN_MUX_EPWM1B = 2 , CLB_GLOBAL_IN_MUX_EPWM5B = 2 , CLB_GLOBAL_IN_MUX_EPWM1B_OE = 3 , CLB_GLOBAL_IN_MUX_EPWM5B_OE = 3 , CLB_GLOBAL_IN_MUX_EPWM1_CTR_ZERO = 4 , CLB_GLOBAL_IN_MUX_EPWM5_CTR_ZERO = 4 , CLB_GLOBAL_IN_MUX_EPWM1_CTR_PRD = 5 , CLB_GLOBAL_IN_MUX_EPWM5_CTR_PRD = 5 , CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR = 6 , CLB_GLOBAL_IN_MUX_EPWM5_CTRDIR = 6 , CLB_GLOBAL_IN_MUX_EPWM1_TBCLK = 7 , CLB_GLOBAL_IN_MUX_EPWM5_TBCLK = 7 , CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPA = 8 , CLB_GLOBAL_IN_MUX_EPWM5_CTR_CMPA = 8 , CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPB = 9 , CLB_GLOBAL_IN_MUX_EPWM5_CTR_CMPB = 9 , CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPC = 10 , CLB_GLOBAL_IN_MUX_EPWM5_CTR_CMPC = 10 , CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPD = 11 , CLB_GLOBAL_IN_MUX_EPWM5_CTR_CMPD = 11 , CLB_GLOBAL_IN_MUX_EPWM1A_AQ = 12 , CLB_GLOBAL_IN_MUX_EPWM5A_AQ = 12 , CLB_GLOBAL_IN_MUX_EPWM1B_AQ = 13 , CLB_GLOBAL_IN_MUX_EPWM5B_AQ = 13 , CLB_GLOBAL_IN_MUX_EPWM1A_DB = 14 , CLB_GLOBAL_IN_MUX_EPWM5A_DB = 14 , CLB_GLOBAL_IN_MUX_EPWM1B_DB = 15 , CLB_GLOBAL_IN_MUX_EPWM5B_DB = 15 , CLB_GLOBAL_IN_MUX_EPWM2A = 16 , CLB_GLOBAL_IN_MUX_EPWM6A = 16 , CLB_GLOBAL_IN_MUX_EPWM2A_OE = 17 , CLB_GLOBAL_IN_MUX_EPWM6A_OE = 17 , CLB_GLOBAL_IN_MUX_EPWM2B = 18 , CLB_GLOBAL_IN_MUX_EPWM6B = 18 , CLB_GLOBAL_IN_MUX_EPWM2B_OE = 19 , CLB_GLOBAL_IN_MUX_EPWM6B_OE = 19 , CLB_GLOBAL_IN_MUX_EPWM2_CTR_ZERO = 20 , CLB_GLOBAL_IN_MUX_EPWM6_CTR_ZERO = 20 , CLB_GLOBAL_IN_MUX_EPWM2_CTR_PRD = 21 , CLB_GLOBAL_IN_MUX_EPWM6_CTR_PRD = 21 , CLB_GLOBAL_IN_MUX_EPWM2_CTRDIR = 22 , CLB_GLOBAL_IN_MUX_EPWM6_CTRDIR = 22 , CLB_GLOBAL_IN_MUX_EPWM2_TBCLK = 23 , CLB_GLOBAL_IN_MUX_EPWM6_TBCLK = 23 , CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPA = 24 , CLB_GLOBAL_IN_MUX_EPWM6_CTR_CMPA = 24 , CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPB = 25 , CLB_GLOBAL_IN_MUX_EPWM6_CTR_CMPB = 25 , CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPC = 26 , CLB_GLOBAL_IN_MUX_EPWM6_CTR_CMPC = 26 , CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPD = 27 , CLB_GLOBAL_IN_MUX_EPWM6_CTR_CMPD = 27 , CLB_GLOBAL_IN_MUX_EPWM2A_AQ = 28 , CLB_GLOBAL_IN_MUX_EPWM6A_AQ = 28 , CLB_GLOBAL_IN_MUX_EPWM2B_AQ = 29 , CLB_GLOBAL_IN_MUX_EPWM6B_AQ = 29 , CLB_GLOBAL_IN_MUX_EPWM2A_DB = 30 , CLB_GLOBAL_IN_MUX_EPWM6A_DB = 30 , CLB_GLOBAL_IN_MUX_EPWM2B_DB = 31 , CLB_GLOBAL_IN_MUX_EPWM6B_DB = 31 , CLB_GLOBAL_IN_MUX_EPWM3A = 32 , CLB_GLOBAL_IN_MUX_EPWM7A = 32 , CLB_GLOBAL_IN_MUX_EPWM3A_OE = 33 , CLB_GLOBAL_IN_MUX_EPWM7A_OE = 33 , CLB_GLOBAL_IN_MUX_EPWM3B = 34 , CLB_GLOBAL_IN_MUX_EPWM7B = 34 , CLB_GLOBAL_IN_MUX_EPWM3B_OE = 35 , CLB_GLOBAL_IN_MUX_EPWM7B_OE = 35 , CLB_GLOBAL_IN_MUX_EPWM3_CTR_ZERO = 36 , CLB_GLOBAL_IN_MUX_EPWM7_CTR_ZERO = 36 , CLB_GLOBAL_IN_MUX_EPWM3_CTR_PRD = 37 , CLB_GLOBAL_IN_MUX_EPWM7_CTR_PRD = 37 , CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR = 38 , CLB_GLOBAL_IN_MUX_EPWM7_CTRDIR = 38 , CLB_GLOBAL_IN_MUX_EPWM3_TBCLK = 39 , CLB_GLOBAL_IN_MUX_EPWM7_TBCLK = 39 , CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPA = 40 , CLB_GLOBAL_IN_MUX_EPWM7_CTR_CMPA = 40 , CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPB = 41 , CLB_GLOBAL_IN_MUX_EPWM7_CTR_CMPB = 41 , CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPC = 42 , CLB_GLOBAL_IN_MUX_EPWM7_CTR_CMPC = 42 , CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPD = 43 , CLB_GLOBAL_IN_MUX_EPWM7_CTR_CMPD = 43 , CLB_GLOBAL_IN_MUX_EPWM3A_AQ = 44 , CLB_GLOBAL_IN_MUX_EPWM7A_AQ = 44 , CLB_GLOBAL_IN_MUX_EPWM3B_AQ = 45 , CLB_GLOBAL_IN_MUX_EPWM7B_AQ = 45 , CLB_GLOBAL_IN_MUX_EPWM3A_DB = 46 , CLB_GLOBAL_IN_MUX_EPWM7A_DB = 46 , CLB_GLOBAL_IN_MUX_EPWM3B_DB = 47 , CLB_GLOBAL_IN_MUX_EPWM7B_DB = 47 , CLB_GLOBAL_IN_MUX_EPWM4A = 48 , CLB_GLOBAL_IN_MUX_EPWM8A = 48 , CLB_GLOBAL_IN_MUX_EPWM4A_OE = 49 , CLB_GLOBAL_IN_MUX_EPWM8A_OE = 49 , CLB_GLOBAL_IN_MUX_EPWM4B = 50 , CLB_GLOBAL_IN_MUX_EPWM8B = 50 , CLB_GLOBAL_IN_MUX_EPWM4B_OE = 51 , CLB_GLOBAL_IN_MUX_EPWM8B_OE = 51 , CLB_GLOBAL_IN_MUX_EPWM4_CTR_ZERO = 52 , CLB_GLOBAL_IN_MUX_EPWM8_CTR_ZERO = 52 , CLB_GLOBAL_IN_MUX_EPWM4_CTR_PRD = 53 , CLB_GLOBAL_IN_MUX_EPWM8_CTR_PRD = 53 , CLB_GLOBAL_IN_MUX_EPWM4_CTRDIR = 54 , CLB_GLOBAL_IN_MUX_EPWM8_CTRDIR = 54 , CLB_GLOBAL_IN_MUX_EPWM4_TBCLK = 55 , CLB_GLOBAL_IN_MUX_EPWM8_TBCLK = 55 , CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPA = 56 , CLB_GLOBAL_IN_MUX_EPWM8_CTR_CMPA = 56 , CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPB = 57 , CLB_GLOBAL_IN_MUX_EPWM8_CTR_CMPB = 57 , CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPC = 58 , CLB_GLOBAL_IN_MUX_EPWM8_CTR_CMPC = 58 , CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPD = 59 , CLB_GLOBAL_IN_MUX_EPWM8_CTR_CMPD = 59 , CLB_GLOBAL_IN_MUX_EPWM4A_AQ = 60 , CLB_GLOBAL_IN_MUX_EPWM8A_AQ = 60 , CLB_GLOBAL_IN_MUX_EPWM4B_AQ = 61 , CLB_GLOBAL_IN_MUX_EPWM8B_AQ = 61 , CLB_GLOBAL_IN_MUX_EPWM4A_DB = 62 , CLB_GLOBAL_IN_MUX_EPWM8A_DB = 62 , CLB_GLOBAL_IN_MUX_EPWM4B_DB = 63 , CLB_GLOBAL_IN_MUX_EPWM8B_DB = 63 , CLB_GLOBAL_IN_MUX_CLB_AUXSIG0 = 64 , CLB_GLOBAL_IN_MUX_CLB_AUXSIG1 = 65 , CLB_GLOBAL_IN_MUX_CLB_AUXSIG2 = 66 , CLB_GLOBAL_IN_MUX_CLB_AUXSIG3 = 67 , CLB_GLOBAL_IN_MUX_CLB_AUXSIG4 = 68 , CLB_GLOBAL_IN_MUX_CLB_AUXSIG5 = 69 , CLB_GLOBAL_IN_MUX_CLB_AUXSIG6 = 70 , CLB_GLOBAL_IN_MUX_CLB_AUXSIG7 = 71 , CLB_GLOBAL_IN_MUX_CLB1_OUT16 = 72 , CLB_GLOBAL_IN_MUX_CLB5_OUT16 = 72 , CLB_GLOBAL_IN_MUX_CLB1_OUT17 = 73 , CLB_GLOBAL_IN_MUX_CLB5_OUT17 = 73 , CLB_GLOBAL_IN_MUX_CLB1_OUT18 = 74 , CLB_GLOBAL_IN_MUX_CLB5_OUT18 = 74 , CLB_GLOBAL_IN_MUX_CLB1_OUT19 = 75 , CLB_GLOBAL_IN_MUX_CLB5_OUT19 = 75 , CLB_GLOBAL_IN_MUX_CLB1_OUT20 = 76 , CLB_GLOBAL_IN_MUX_CLB5_OUT20 = 76 , CLB_GLOBAL_IN_MUX_CLB1_OUT21 = 77 , CLB_GLOBAL_IN_MUX_CLB5_OUT21 = 77 , CLB_GLOBAL_IN_MUX_CLB1_OUT22 = 78 , CLB_GLOBAL_IN_MUX_CLB5_OUT22 = 78 , CLB_GLOBAL_IN_MUX_CLB1_OUT23 = 79 , CLB_GLOBAL_IN_MUX_CLB5_OUT23 = 79 , CLB_GLOBAL_IN_MUX_CLB2_OUT16 = 80 , CLB_GLOBAL_IN_MUX_CLB6_OUT16 = 80 , CLB_GLOBAL_IN_MUX_CLB2_OUT17 = 81 , CLB_GLOBAL_IN_MUX_CLB6_OUT17 = 81 , CLB_GLOBAL_IN_MUX_CLB2_OUT18 = 82 , CLB_GLOBAL_IN_MUX_CLB6_OUT18 = 82 , CLB_GLOBAL_IN_MUX_CLB2_OUT19 = 83 , CLB_GLOBAL_IN_MUX_CLB6_OUT19 = 83 , CLB_GLOBAL_IN_MUX_CLB2_OUT20 = 84 , CLB_GLOBAL_IN_MUX_CLB6_OUT20 = 84 , CLB_GLOBAL_IN_MUX_CLB2_OUT21 = 85 , CLB_GLOBAL_IN_MUX_CLB6_OUT21 = 85 , CLB_GLOBAL_IN_MUX_CLB2_OUT22 = 86 , CLB_GLOBAL_IN_MUX_CLB6_OUT22 = 86 , CLB_GLOBAL_IN_MUX_CLB2_OUT23 = 87 , CLB_GLOBAL_IN_MUX_CLB6_OUT23 = 87 , CLB_GLOBAL_IN_MUX_CLB3_OUT16 = 88 , CLB_GLOBAL_IN_MUX_CLB3_OUT17 = 89 , CLB_GLOBAL_IN_MUX_CLB3_OUT18 = 90 , CLB_GLOBAL_IN_MUX_CLB3_OUT19 = 91 , CLB_GLOBAL_IN_MUX_CLB3_OUT20 = 92 , CLB_GLOBAL_IN_MUX_CLB3_OUT21 = 93 , CLB_GLOBAL_IN_MUX_CLB3_OUT22 = 94 , CLB_GLOBAL_IN_MUX_CLB3_OUT23 = 95 , CLB_GLOBAL_IN_MUX_CLB4_OUT16 = 96 , CLB_GLOBAL_IN_MUX_CLB4_OUT17 = 97 , CLB_GLOBAL_IN_MUX_CLB4_OUT18 = 98 , CLB_GLOBAL_IN_MUX_CLB4_OUT19 = 99 , CLB_GLOBAL_IN_MUX_CLB4_OUT20 = 100 , CLB_GLOBAL_IN_MUX_CLB4_OUT21 = 101 , CLB_GLOBAL_IN_MUX_CLB4_OUT22 = 102 , CLB_GLOBAL_IN_MUX_CLB4_OUT23 = 103 , CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT0 = 104 , CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT0 = 104 , CLB_GLOBAL_IN_MUX_CPU1_ERAD_SEC_EVENT0 = 104 , CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT0 = 104 , CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT1 = 105 , CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT1 = 105 , CLB_GLOBAL_IN_MUX_CPU1_ERAD_SEC_EVENT1 = 105 , CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT1 = 105 , CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT2 = 106 , CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT2 = 106 , CLB_GLOBAL_IN_MUX_CPU1_ERAD_SEC_EVENT2 = 106 , CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT2 = 106 , CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT3 = 107 , CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT3 = 107 , CLB_GLOBAL_IN_MUX_CPU1_ERAD_SEC_EVENT3 = 107 , CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT3 = 107 , CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT4 = 108 , CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT4 = 108 , CLB_GLOBAL_IN_MUX_CPU2_ERAD_SEC_EVENT0 = 108 , CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT4 = 108 , CLB_GLOBAL_IN_MUX_CPU3_ERAD_SEC_EVENT0 = 108 , CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT5 = 109 , CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT5 = 109 , CLB_GLOBAL_IN_MUX_CPU2_ERAD_SEC_EVENT1 = 109 , CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT5 = 109 , CLB_GLOBAL_IN_MUX_CPU3_ERAD_SEC_EVENT1 = 109 , CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT6 = 110 , CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT6 = 110 , CLB_GLOBAL_IN_MUX_CPU2_ERAD_SEC_EVENT2 = 110 , CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT6 = 110 , CLB_GLOBAL_IN_MUX_CPU3_ERAD_SEC_EVENT2 = 110 , CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT7 = 111 , CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT7 = 111 , CLB_GLOBAL_IN_MUX_CPU2_ERAD_SEC_EVENT3 = 111 , CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT7 = 111 , CLB_GLOBAL_IN_MUX_CPU3_ERAD_SEC_EVENT3 = 111 , CLB_GLOBAL_IN_MUX_FSIRXA_DATA_PACKET_RCVD = 112 , CLB_GLOBAL_IN_MUX_FSIRXA_PING_TAG_MATCH2 = 112 , CLB_GLOBAL_IN_MUX_FSIRXA_ERROR_PACKET_RCVD = 113 , CLB_GLOBAL_IN_MUX_FSIRXA_CLB5_CLB6_DATA_TAG_MATCH2 = 113 , CLB_GLOBAL_IN_MUX_FSIRXA_PING_PACKET_RCVD = 114 , CLB_GLOBAL_IN_MUX_FSIRXA_ERROR_TAG_MATCH2 = 114 , CLB_GLOBAL_IN_MUX_FSIRXA_OUTPUT_FRAME_DONE = 115 , CLB_GLOBAL_IN_MUX_FSIRXB_PING_TAG_MATCH = 115 , CLB_GLOBAL_IN_MUX_FSIRXA_PING_TAG_MATCH1 = 116 , CLB_GLOBAL_IN_MUX_FSIRXB_DATA_TAG_MATCH = 116 , CLB_GLOBAL_IN_MUX_FSIRXA_CLB1_CLB4_DATA_TAG_MATCH2 = 117 , CLB_GLOBAL_IN_MUX_FSIRXB_ERROR_TAG_MATCH = 117 , CLB_GLOBAL_IN_MUX_FSIRXA_ERROR_TAG_MATCH1 = 118 , CLB_GLOBAL_IN_MUX_ECAT_SOF = 118 , CLB_GLOBAL_IN_MUX_FSIRXA_RX_TRIG2 = 119 , CLB_GLOBAL_IN_MUX_ECAT_EOF = 119 , CLB_GLOBAL_IN_MUX_SPI1_SPICLK = 120 , CLB_GLOBAL_IN_MUX_SPI1_SPIPOCI_CONTROLLER = 121 , CLB_GLOBAL_IN_MUX_SPI1_SPIPTE = 122 , CLB_GLOBAL_IN_MUX_SPI2_SPICLK = 123 , CLB_GLOBAL_IN_MUX_SPI2_SPIPOCI_CONTROLLER = 124 , CLB_GLOBAL_IN_MUX_SPI2_SPIPTE = 125 , CLB_GLOBAL_IN_MUX_CPU3_HALT = 126 , CLB_GLOBAL_IN_MUX_ECAT_SYNC0 = 126 , CLB_GLOBAL_IN_MUX_FSIRXA_RX_TRIG3 = 127 , CLB_GLOBAL_IN_MUX_ECAT_SYNC1 = 127 }

Macros
#define	CLB_LOGICCTL 0x0200U

#define	CLB_DATAEXCH 0x0300U

#define	CLB_ADDR_COUNTER_0_LOAD 0x0U

#define	CLB_ADDR_COUNTER_1_LOAD 0x1U

#define	CLB_ADDR_COUNTER_2_LOAD 0x2U

#define	CLB_ADDR_COUNTER_0_MATCH1 0x4U

#define	CLB_ADDR_COUNTER_1_MATCH1 0x5U

#define	CLB_ADDR_COUNTER_2_MATCH1 0x6U

#define	CLB_ADDR_COUNTER_0_MATCH2 0x8U

#define	CLB_ADDR_COUNTER_1_MATCH2 0x9U

#define	CLB_ADDR_COUNTER_2_MATCH2 0xAU

#define	CLB_ADDR_HLC_R0 0xCU

#define	CLB_ADDR_HLC_R1 0xDU

#define	CLB_ADDR_HLC_R2 0xEU

#define	CLB_ADDR_HLC_R3 0xFU

#define	CLB_ADDR_HLC_BASE 0x20U

#define	CLB_NUM_HLC_INSTR 31U

#define	CLB_FIFO_SIZE 4U

#define	CLB_LOCK_KEY 0x5A5AU

#define	CLB_LCL_MUX_SEL_MISC_INPUT_SEL_M 0x20U

#define	CLB_LCL_MUX_SEL_MISC_INPUT_SEL_S 28U

#define	CLB_LCL_MUX_SEL_MISC_INPUT_SEL_BITM (uint32_t)1U

#define	CLB_OUTPUT_00 0x00000001U
	Mask for CLB OUTPUT ENABLE/DISABLE 0.

#define	CLB_OUTPUT_01 0x00000002U
	Mask for CLB OUTPUT ENABLE/DISABLE 1.

#define	CLB_OUTPUT_02 0x00000004U
	Mask for CLB OUTPUT ENABLE/DISABLE 2.

#define	CLB_OUTPUT_03 0x00000008U
	Mask for CLB OUTPUT ENABLE/DISABLE 3.

#define	CLB_OUTPUT_04 0x00000010U
	Mask for CLB OUTPUT ENABLE/DISABLE 4.

#define	CLB_OUTPUT_05 0x00000020U
	Mask for CLB OUTPUT ENABLE/DISABLE 5.

#define	CLB_OUTPUT_06 0x00000040U
	Mask for CLB OUTPUT ENABLE/DISABLE 6.

#define	CLB_OUTPUT_07 0x00000080U
	Mask for CLB OUTPUT ENABLE/DISABLE 7.

#define	CLB_OUTPUT_08 0x00000100U
	Mask for CLB OUTPUT ENABLE/DISABLE 8.

#define	CLB_OUTPUT_09 0x00000200U
	Mask for CLB OUTPUT ENABLE/DISABLE 9.

#define	CLB_OUTPUT_10 0x00000400U
	Mask for CLB OUTPUT ENABLE/DISABLE 10.

#define	CLB_OUTPUT_11 0x00000800U
	Mask for CLB OUTPUT ENABLE/DISABLE 11.

#define	CLB_OUTPUT_12 0x00001000U
	Mask for CLB OUTPUT ENABLE/DISABLE 12.

#define	CLB_OUTPUT_13 0x00002000U
	Mask for CLB OUTPUT ENABLE/DISABLE 13.

#define	CLB_OUTPUT_14 0x00004000U
	Mask for CLB OUTPUT ENABLE/DISABLE 14.

#define	CLB_OUTPUT_15 0x00008000U
	Mask for CLB OUTPUT ENABLE/DISABLE 15.

#define	CLB_OUTPUT_16 0x00010000U
	Mask for CLB OUTPUT ENABLE/DISABLE 16.

#define	CLB_OUTPUT_17 0x00020000U
	Mask for CLB OUTPUT ENABLE/DISABLE 17.

#define	CLB_OUTPUT_18 0x00040000U
	Mask for CLB OUTPUT ENABLE/DISABLE 18.

#define	CLB_OUTPUT_19 0x00080000U
	Mask for CLB OUTPUT ENABLE/DISABLE 19.

#define	CLB_OUTPUT_20 0x00100000U
	Mask for CLB OUTPUT ENABLE/DISABLE 20.

#define	CLB_OUTPUT_21 0x00200000U
	Mask for CLB OUTPUT ENABLE/DISABLE 21.

#define	CLB_OUTPUT_22 0x00400000U
	Mask for CLB OUTPUT ENABLE/DISABLE 22.

#define	CLB_OUTPUT_23 0x00800000U
	Mask for CLB OUTPUT ENABLE/DISABLE 23.

#define	CLB_OUTPUT_24 0x01000000U
	Mask for CLB OUTPUT ENABLE/DISABLE 24.

#define	CLB_OUTPUT_25 0x02000000U
	Mask for CLB OUTPUT ENABLE/DISABLE 25.

#define	CLB_OUTPUT_26 0x04000000U
	Mask for CLB OUTPUT ENABLE/DISABLE 26.

#define	CLB_OUTPUT_27 0x08000000U
	Mask for CLB OUTPUT ENABLE/DISABLE 27.

#define	CLB_OUTPUT_28 0x10000000U
	Mask for CLB OUTPUT ENABLE/DISABLE 28.

#define	CLB_OUTPUT_29 0x20000000U
	Mask for CLB OUTPUT ENABLE/DISABLE 29.

#define	CLB_OUTPUT_30 0x40000000U
	Mask for CLB OUTPUT ENABLE/DISABLE 30.

#define	CLB_OUTPUT_31 0x80000000U
	Mask for CLB OUTPUT ENABLE/DISABLE 31.

Macro Definition Documentation

◆ CLB_LOGICCTL

#define CLB_LOGICCTL 0x0200U

◆ CLB_DATAEXCH

#define CLB_DATAEXCH 0x0300U

◆ CLB_ADDR_COUNTER_0_LOAD

#define CLB_ADDR_COUNTER_0_LOAD 0x0U

◆ CLB_ADDR_COUNTER_1_LOAD

#define CLB_ADDR_COUNTER_1_LOAD 0x1U

◆ CLB_ADDR_COUNTER_2_LOAD

#define CLB_ADDR_COUNTER_2_LOAD 0x2U

◆ CLB_ADDR_COUNTER_0_MATCH1

#define CLB_ADDR_COUNTER_0_MATCH1 0x4U

◆ CLB_ADDR_COUNTER_1_MATCH1

#define CLB_ADDR_COUNTER_1_MATCH1 0x5U

◆ CLB_ADDR_COUNTER_2_MATCH1

#define CLB_ADDR_COUNTER_2_MATCH1 0x6U

◆ CLB_ADDR_COUNTER_0_MATCH2

#define CLB_ADDR_COUNTER_0_MATCH2 0x8U

◆ CLB_ADDR_COUNTER_1_MATCH2

#define CLB_ADDR_COUNTER_1_MATCH2 0x9U

◆ CLB_ADDR_COUNTER_2_MATCH2

#define CLB_ADDR_COUNTER_2_MATCH2 0xAU

◆ CLB_ADDR_HLC_R0

#define CLB_ADDR_HLC_R0 0xCU

◆ CLB_ADDR_HLC_R1

#define CLB_ADDR_HLC_R1 0xDU

◆ CLB_ADDR_HLC_R2

#define CLB_ADDR_HLC_R2 0xEU

◆ CLB_ADDR_HLC_R3

#define CLB_ADDR_HLC_R3 0xFU

◆ CLB_ADDR_HLC_BASE

#define CLB_ADDR_HLC_BASE 0x20U

◆ CLB_NUM_HLC_INSTR

#define CLB_NUM_HLC_INSTR 31U

◆ CLB_FIFO_SIZE

#define CLB_FIFO_SIZE 4U

◆ CLB_LOCK_KEY

#define CLB_LOCK_KEY 0x5A5AU

◆ CLB_LCL_MUX_SEL_MISC_INPUT_SEL_M

#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_M 0x20U

◆ CLB_LCL_MUX_SEL_MISC_INPUT_SEL_S

#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_S 28U

◆ CLB_LCL_MUX_SEL_MISC_INPUT_SEL_BITM

#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_BITM (uint32_t)1U

◆ CLB_OUTPUT_00

#define CLB_OUTPUT_00 0x00000001U

Mask for CLB OUTPUT ENABLE/DISABLE 0.

Values that can be passed to control the CLB output enable signal. It can be passed to CLB_setOutputMask() as the outputMask parameter.

◆ CLB_OUTPUT_01

#define CLB_OUTPUT_01 0x00000002U

Mask for CLB OUTPUT ENABLE/DISABLE 1.

◆ CLB_OUTPUT_02

#define CLB_OUTPUT_02 0x00000004U

Mask for CLB OUTPUT ENABLE/DISABLE 2.

◆ CLB_OUTPUT_03

#define CLB_OUTPUT_03 0x00000008U

Mask for CLB OUTPUT ENABLE/DISABLE 3.

◆ CLB_OUTPUT_04

#define CLB_OUTPUT_04 0x00000010U

Mask for CLB OUTPUT ENABLE/DISABLE 4.

◆ CLB_OUTPUT_05

#define CLB_OUTPUT_05 0x00000020U

Mask for CLB OUTPUT ENABLE/DISABLE 5.

◆ CLB_OUTPUT_06

#define CLB_OUTPUT_06 0x00000040U

Mask for CLB OUTPUT ENABLE/DISABLE 6.

◆ CLB_OUTPUT_07

#define CLB_OUTPUT_07 0x00000080U

Mask for CLB OUTPUT ENABLE/DISABLE 7.

◆ CLB_OUTPUT_08

#define CLB_OUTPUT_08 0x00000100U

Mask for CLB OUTPUT ENABLE/DISABLE 8.

◆ CLB_OUTPUT_09

#define CLB_OUTPUT_09 0x00000200U

Mask for CLB OUTPUT ENABLE/DISABLE 9.

◆ CLB_OUTPUT_10

#define CLB_OUTPUT_10 0x00000400U

Mask for CLB OUTPUT ENABLE/DISABLE 10.

◆ CLB_OUTPUT_11

#define CLB_OUTPUT_11 0x00000800U

Mask for CLB OUTPUT ENABLE/DISABLE 11.

◆ CLB_OUTPUT_12

#define CLB_OUTPUT_12 0x00001000U

Mask for CLB OUTPUT ENABLE/DISABLE 12.

◆ CLB_OUTPUT_13

#define CLB_OUTPUT_13 0x00002000U

Mask for CLB OUTPUT ENABLE/DISABLE 13.

◆ CLB_OUTPUT_14

#define CLB_OUTPUT_14 0x00004000U

Mask for CLB OUTPUT ENABLE/DISABLE 14.

◆ CLB_OUTPUT_15

#define CLB_OUTPUT_15 0x00008000U

Mask for CLB OUTPUT ENABLE/DISABLE 15.

◆ CLB_OUTPUT_16

#define CLB_OUTPUT_16 0x00010000U

Mask for CLB OUTPUT ENABLE/DISABLE 16.

◆ CLB_OUTPUT_17

#define CLB_OUTPUT_17 0x00020000U

Mask for CLB OUTPUT ENABLE/DISABLE 17.

◆ CLB_OUTPUT_18

#define CLB_OUTPUT_18 0x00040000U

Mask for CLB OUTPUT ENABLE/DISABLE 18.

◆ CLB_OUTPUT_19

#define CLB_OUTPUT_19 0x00080000U

Mask for CLB OUTPUT ENABLE/DISABLE 19.

◆ CLB_OUTPUT_20

#define CLB_OUTPUT_20 0x00100000U

Mask for CLB OUTPUT ENABLE/DISABLE 20.

◆ CLB_OUTPUT_21

#define CLB_OUTPUT_21 0x00200000U

Mask for CLB OUTPUT ENABLE/DISABLE 21.

◆ CLB_OUTPUT_22

#define CLB_OUTPUT_22 0x00400000U

Mask for CLB OUTPUT ENABLE/DISABLE 22.

◆ CLB_OUTPUT_23

#define CLB_OUTPUT_23 0x00800000U

Mask for CLB OUTPUT ENABLE/DISABLE 23.

◆ CLB_OUTPUT_24

#define CLB_OUTPUT_24 0x01000000U

Mask for CLB OUTPUT ENABLE/DISABLE 24.

◆ CLB_OUTPUT_25

#define CLB_OUTPUT_25 0x02000000U

Mask for CLB OUTPUT ENABLE/DISABLE 25.

◆ CLB_OUTPUT_26

#define CLB_OUTPUT_26 0x04000000U

Mask for CLB OUTPUT ENABLE/DISABLE 26.

◆ CLB_OUTPUT_27

#define CLB_OUTPUT_27 0x08000000U

Mask for CLB OUTPUT ENABLE/DISABLE 27.

◆ CLB_OUTPUT_28

#define CLB_OUTPUT_28 0x10000000U

Mask for CLB OUTPUT ENABLE/DISABLE 28.

◆ CLB_OUTPUT_29

#define CLB_OUTPUT_29 0x20000000U

Mask for CLB OUTPUT ENABLE/DISABLE 29.

◆ CLB_OUTPUT_30

#define CLB_OUTPUT_30 0x40000000U

Mask for CLB OUTPUT ENABLE/DISABLE 30.

◆ CLB_OUTPUT_31

#define CLB_OUTPUT_31 0x80000000U

Mask for CLB OUTPUT ENABLE/DISABLE 31.

Enumeration Type Documentation

◆ CLB_Inputs

enum CLB_Inputs

Values that can be passed to select CLB input signal.

Enumerator
CLB_IN0	Input 0.
CLB_IN1	Input 1.
CLB_IN2	Input 2.
CLB_IN3	Input 3.
CLB_IN4	Input 4.
CLB_IN5	Input 5.
CLB_IN6	Input 6.
CLB_IN7	Input 7.

◆ CLB_Outputs

enum CLB_Outputs

Values that can be passed to select CLB output signal. It can be passed to CLB_configOutputLUT() as the outID parameter.

Enumerator
CLB_OUT0	Output 0.
CLB_OUT1	Output 1.
CLB_OUT2	Output 2.
CLB_OUT3	Output 3.
CLB_OUT4	Output 4.
CLB_OUT5	Output 5.
CLB_OUT6	Output 6.
CLB_OUT7	Output 7.

◆ CLB_AOCs

enum CLB_AOCs

Values that can be passed to select CLB AOC signal. It can be passed to CLB_configAOC() as the aocID parameter. AOC is the Asynchronous Output Conditioning block.

Enumerator
CLB_AOC0	AOC 0.
CLB_AOC1	AOC 1.
CLB_AOC2	AOC 2.
CLB_AOC3	AOC 3.
CLB_AOC4	AOC 4.
CLB_AOC5	AOC 5.
CLB_AOC6	AOC 6.
CLB_AOC7	AOC 7.

◆ CLB_SWReleaseCtrl

enum CLB_SWReleaseCtrl

Values that can be passed to set/clear CLB SW release signals. It can be passed to CLB_writeSWReleaseControl() as the inID parameter.

Enumerator
CLB_SW_RLS_CTRL0	SW RLS CTRL 0.
CLB_SW_RLS_CTRL1	SW RLS CTRL 1.
CLB_SW_RLS_CTRL2	SW RLS CTRL 2.
CLB_SW_RLS_CTRL3	SW RLS CTRL 3.
CLB_SW_RLS_CTRL4	SW RLS CTRL 4.
CLB_SW_RLS_CTRL5	SW RLS CTRL 5.
CLB_SW_RLS_CTRL6	SW RLS CTRL 6.
CLB_SW_RLS_CTRL7	SW RLS CTRL 7.

◆ CLB_SWGateCtrl

enum CLB_SWGateCtrl

Values that can be passed to set/clear CLB SW release signals. It can be passed to CLB_writeSWGateControl() as the inID parameter.

Enumerator
CLB_SW_GATE_CTRL0	SW GATE CTRL 0.
CLB_SW_GATE_CTRL1	SW GATE CTRL 1.
CLB_SW_GATE_CTRL2	SW GATE CTRL 2.
CLB_SW_GATE_CTRL3	SW GATE CTRL 3.
CLB_SW_GATE_CTRL4	SW GATE CTRL 4.
CLB_SW_GATE_CTRL5	SW GATE CTRL 5.
CLB_SW_GATE_CTRL6	SW GATE CTRL 6.
CLB_SW_GATE_CTRL7	SW GATE CTRL 7.

◆ CLB_Counters

enum CLB_Counters

Values that can be passed to select CLB counter. It can be passed to CLB_configCounterLoadMatch() as the counterID parameter.

Enumerator
CLB_CTR0	Counter 0.
CLB_CTR1	Counter 1.
CLB_CTR2	Counter 2.

◆ CLB_Register

enum CLB_Register

Values that can be passed to CLB_getRegister() as the registerID parameter.

Enumerator
CLB_REG_HLC_R0	HLC R0 register.
CLB_REG_HLC_R1	HLC R1 register.
CLB_REG_HLC_R2	HLC R2 register.
CLB_REG_HLC_R3	HLC R3 register.
CLB_REG_CTR_C0	Counter 0 register.
CLB_REG_CTR_C1	Counter 1 register.
CLB_REG_CTR_C2	Counter 2 register.

◆ CLB_FilterType

enum CLB_FilterType

Values that can be passed to CLB_selectInputFilter() as the filterType parameter.

Enumerator
CLB_FILTER_NONE	No filtering.
CLB_FILTER_RISING_EDGE	Rising edge detect.
CLB_FILTER_FALLING_EDGE	Falling edge detect.
CLB_FILTER_ANY_EDGE	Any edge detect.

◆ CLB_GPInputMux

enum CLB_GPInputMux

Values that can be passed to CLB_configGPInputMux() as the gpMuxCfg parameter.

Enumerator
CLB_GP_IN_MUX_EXTERNAL	Use external input path.
CLB_GP_IN_MUX_GP_REG	Use CLB_GP_REG bit value as input.

◆ CLB_LocalInputMux

enum CLB_LocalInputMux

Values that can be passed to CLB_configLocalInputMux() as the localMuxCfg parameter.

Enumerator
CLB_LOCAL_IN_MUX_GLOBAL_IN
CLB_LOCAL_IN_MUX_EPWM_DCAEVT1	Global input mux selection.
CLB_LOCAL_IN_MUX_EPWM_DCAEVT2	EPWMx DCAEVT1.
CLB_LOCAL_IN_MUX_EPWM_DCBEVT1	EPWMx DCAEVT2.
CLB_LOCAL_IN_MUX_EPWM_DCBEVT2	EPWMx DCBEVT1.
CLB_LOCAL_IN_MUX_EPWM_DCAH	EPWMx DCBEVT2.
CLB_LOCAL_IN_MUX_EPWM_DCAL	EPWMx DCAH.
CLB_LOCAL_IN_MUX_EPWM_DCBH	EPWMx DCAL.
CLB_LOCAL_IN_MUX_EPWM_DCBL	EPWMx DCBH.
CLB_LOCAL_IN_MUX_EPWM_OST	EPWMx DCBL.
CLB_LOCAL_IN_MUX_EPWM_CBC	EPWMx OST.
CLB_LOCAL_IN_MUX_ECAP_ECAPIN	EPWMx CBC.
CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT	ECAPx ECAPIN.
CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT_EN	ECAPx ECAP_OUT.
CLB_LOCAL_IN_MUX_ECAP_CEVT1	ECAPx ECAP_OUT_EN.
CLB_LOCAL_IN_MUX_ECAP_CEVT2	ECAPx CEVT1.
CLB_LOCAL_IN_MUX_ECAP_CEVT3	ECAPx CEVT2.
CLB_LOCAL_IN_MUX_ECAP_CEVT4	ECAPx CEVT3.
CLB_LOCAL_IN_MUX_EQEP_EQEPA	ECAPx CEVT4.
CLB_LOCAL_IN_MUX_FSI_DATA_PKT_RCVD	EQEPx EQEPA (CLB 1-4)
CLB_LOCAL_IN_MUX_EQEP_EQEPB	FSI_DATA_PKT_RCVD(CLB 5-6)
CLB_LOCAL_IN_MUX_FSI_ERROR_PKT_RCVD	EQEPx EQEPB (CLB 1-4)
CLB_LOCAL_IN_MUX_EQEP_EQEPI	FSI_ERROR_PKT_RCVD(CLB 5-6)
CLB_LOCAL_IN_MUX_FSI_PING_PKT_RCVD	EQEPx EQEPI (CLB 1-4)
CLB_LOCAL_IN_MUX_EQEP_EQEPS	FSI_PING_PKT_RCVD(CLB 5-6)
CLB_LOCAL_IN_MUX_CPU3_HALT	EQEPx EQEPS (CLB 1-4)
CLB_LOCAL_IN_MUX_CPU1_TBCLKSYNC	CPU3.HALT (CLB 5-6)
CLB_LOCAL_IN_MUX_CPU3_TBCLKSYNC	CPU1.TBCLKSYNC.
CLB_LOCAL_IN_MUX_CPU2_TBCLKSYNC	CPU3.TBCLKSYNC.
CLB_LOCAL_IN_MUX_CPU1_HALT	CPU2.TBCLKSYNC.
CLB_LOCAL_IN_MUX_SPIPICO_CONTROLLER	CPU1.HALT (CLB 1-2)
CLB_LOCAL_IN_MUX_SPICLK	SPIPICO Controller Output.
CLB_LOCAL_IN_MUX_SPIPICO_PERIPHERAL	SPI Clock.
CLB_LOCAL_IN_MUX_SPIPTE	SPIPICO Peripheral Input.
CLB_LOCAL_IN_MUX_SPIPOCI_OUT	SPI PTE.
CLB_LOCAL_IN_MUX_CLB_PSCLK	SPIPOCI(OUT)
CLB_LOCAL_IN_MUX_EPWM9A	CLB prescaled clock.
CLB_LOCAL_IN_MUX_ECAP5_ECAPIN	EPWM9A (CLB 1-4)
CLB_LOCAL_IN_MUX_ECAP6_ECAPIN	ECAP5 ECAPIN (CLB 5-6)
CLB_LOCAL_IN_MUX_EPWM9A_OE	ECAPx ECAPIN.
CLB_LOCAL_IN_MUX_ECAP5_ECAP_OUT	EPWM9A trip output (CLB 1-4)
CLB_LOCAL_IN_MUX_ECAP6_ECAP_OUT	ECAP5 ECAP_OUT(CLB 5-6)
CLB_LOCAL_IN_MUX_EPWM9B	ECAPx ECAP_OUT.
CLB_LOCAL_IN_MUX_ECAP5_ECAP_OUT_EN	EPWM9B (CLB 1-4)
CLB_LOCAL_IN_MUX_ECAP6_ECAP_OUT_EN	ECAP5 ECAP_OUT_EN(CLB 5-6)
CLB_LOCAL_IN_MUX_EPWM9B_OE	ECAPx ECAP_OUT_EN.
CLB_LOCAL_IN_MUX_ECAP5_CEVT1	EPWM9B trip output (CLB 1-4)
CLB_LOCAL_IN_MUX_ECAP6_CEVT1	ECAP5 CEVT1 (CLB 5-6)
CLB_LOCAL_IN_MUX_EPWM10A	ECAPx CEVT1.
CLB_LOCAL_IN_MUX_ECAP5_CEVT2	EPWM10A (CLB 1-4)
CLB_LOCAL_IN_MUX_ECAP6_CEVT2	ECAP5 CEVT2 (CLB 5-6)
CLB_LOCAL_IN_MUX_EPWM10A_OE	ECAPx CEVT2.
CLB_LOCAL_IN_MUX_ECAP5_CEVT3	EPWM10A trip output (CLB 1-4)
CLB_LOCAL_IN_MUX_ECAP6_CEVT3	ECAP5 CEVT3 (CLB 5-6)
CLB_LOCAL_IN_MUX_EPWM10B	ECAPx CEVT3.
CLB_LOCAL_IN_MUX_ECAP5_CEVT4	EPWM10B (CLB 1-4)
CLB_LOCAL_IN_MUX_ECAP6_CEVT4	ECAP5 CEVT4 (CLB 5-6)
CLB_LOCAL_IN_MUX_EPWM10B_OE	ECAPx CEVT4.
CLB_LOCAL_IN_MUX_ECAP5_ECAPIN0	EPWM10B trip output (CLB 1-4)
CLB_LOCAL_IN_MUX_ECAP6_ECAPIN0	ECAP5 ECAPIN (CLB 5-6)
CLB_LOCAL_IN_MUX_EPWM11A	ECAPx ECAPIN.
CLB_LOCAL_IN_MUX_EQEP5_EQEPA	EPWM11A (CLB 1-4)
CLB_LOCAL_IN_MUX_EQEP6_EQEPA	EQEP5 EQEPA (CLB 5)
CLB_LOCAL_IN_MUX_EPWM11A_OE	EQEP6 EQEPA (CLB 6)
CLB_LOCAL_IN_MUX_EQEP5_EQEPB	EPWM11A trip output (CLB 1-4)
CLB_LOCAL_IN_MUX_EQEP6_EQEPB	EQEP5 EQEPB (CLB 5)
CLB_LOCAL_IN_MUX_EPWM11B	EQEP6 EQEPB (CLB 6)
CLB_LOCAL_IN_MUX_EQEP5_EQEPI	EPWM11B (CLB 1-4)
CLB_LOCAL_IN_MUX_EQEP6_EQEPI	EQEP5 EQEPI (CLB 5)
CLB_LOCAL_IN_MUX_EPWM11B_OE	EQEP6 EQEPI (CLB 6)
CLB_LOCAL_IN_MUX_EQEP5_EQEPS	EPWM11B trip output (CLB 1-4)
CLB_LOCAL_IN_MUX_EQEP6_EQEPS	EQEP5 EQEPS (CLB 5)
CLB_LOCAL_IN_MUX_EPWM12A	EQEP6 EQEPS (CLB 6)
CLB_LOCAL_IN_MUX_EPWM16A	EPWM12A (CLB 1-4)
CLB_LOCAL_IN_MUX_EPWM12A_OE	EPWM16A (CLB 5-6)
CLB_LOCAL_IN_MUX_EPWM16A_OE	EPWM12A trip output (CLB 1-4)
CLB_LOCAL_IN_MUX_EPWM12B	EPWM16A trip output (CLB 5-6)
CLB_LOCAL_IN_MUX_EPWM16B	EPWM12B (CLB 1-4)
CLB_LOCAL_IN_MUX_EPWM12B_OE	EPWM16B (CLB 5-6)
CLB_LOCAL_IN_MUX_EPWM16B_OE	EPWM12B trip output (CLB 1-4)
CLB_LOCAL_IN_MUX_INPUT17	EPWM16B trip output (CLB 5-6)
CLB_LOCAL_IN_MUX_INPUT18	INPUTXBAR INPUT17.
CLB_LOCAL_IN_MUX_INPUT19	INPUTXBAR INPUT18.
CLB_LOCAL_IN_MUX_INPUT20	INPUTXBAR INPUT19.
CLB_LOCAL_IN_MUX_INPUT21	INPUTXBAR INPUT20.
CLB_LOCAL_IN_MUX_INPUT22	INPUTXBAR INPUT21.
CLB_LOCAL_IN_MUX_INPUT23	INPUTXBAR INPUT22.
CLB_LOCAL_IN_MUX_INPUT24	INPUTXBAR INPUT23.
CLB_LOCAL_IN_MUX_INPUT25	INPUTXBAR INPUT24.
CLB_LOCAL_IN_MUX_INPUT26	INPUTXBAR INPUT25.
CLB_LOCAL_IN_MUX_INPUT27	INPUTXBAR INPUT26.
CLB_LOCAL_IN_MUX_INPUT28	INPUTXBAR INPUT27.
CLB_LOCAL_IN_MUX_INPUT29	INPUTXBAR INPUT28.
CLB_LOCAL_IN_MUX_INPUT30	INPUTXBAR INPUT29.
CLB_LOCAL_IN_MUX_INPUT31	INPUTXBAR INPUT30.
CLB_LOCAL_IN_MUX_INPUT32	INPUTXBAR INPUT31.

◆ CLB_GlobalInputMux

enum CLB_GlobalInputMux

Values that can be passed to CLB_configGlobalInputMux() as the globalMuxCfg parameter.

Enumerator
CLB_GLOBAL_IN_MUX_EPWM1A
CLB_GLOBAL_IN_MUX_EPWM5A	EPWM1A (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1A_OE	EPWM5A (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5A_OE	EPWM1A trip output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1B	EPWM5A trip output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5B	EPWM1B (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1B_OE	EPWM5B (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5B_OE	EPWM1B trip output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1_CTR_ZERO	EPWM5B trip output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5_CTR_ZERO	EPWM1 TBCTR = Zero (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1_CTR_PRD	EPWM5 TBCTR = Zero (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5_CTR_PRD	EPWM1 TBCTR = TBPRD (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR	EPWM5 TBCTR = TBPRD (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5_CTRDIR	EPWM1 CTRDIR (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1_TBCLK	EPWM5 CTRDIR (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5_TBCLK	EPWM1 TBCLK (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPA	EPWM5 TBCLK (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5_CTR_CMPA	EPWM1 TBCTR = CMPA (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPB	EPWM5 TBCTR = CMPA (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5_CTR_CMPB	EPWM1 TBCTR = CMPB (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPC	EPWM5 TBCTR = CMPB (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5_CTR_CMPC	EPWM1 TBCTR = CMPC (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPD	EPWM5 TBCTR = CMPC (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5_CTR_CMPD	EPWM1 TBCTR = CMPD (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1A_AQ	EPWM5 TBCTR = CMPD (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5A_AQ	EPWM1A AQ submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1B_AQ	EPWM5A AQ submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5B_AQ	EPWM1B AQ submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1A_DB	EPWM5B AQ submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5A_DB	EPWM1A DB submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM1B_DB	EPWM5A DB submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM5B_DB	EPWM1B DB submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2A	EPWM5B DB submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6A	EPWM2A (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2A_OE	EPWM6A (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6A_OE	EPWM2A trip output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2B	EPWM6A trip output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6B	EPWM2B (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2B_OE	EPWM6B (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6B_OE	EPWM2B trip output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2_CTR_ZERO	EPWM6B trip output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6_CTR_ZERO	EPWM2 TBCTR = Zero (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2_CTR_PRD	EPWM6 TBCTR = Zero (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6_CTR_PRD	EPWM2 TBCTR = TBPRD (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2_CTRDIR	EPWM6 TBCTR = TBPRD (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6_CTRDIR	EPWM2 CTRDIR (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2_TBCLK	EPWM6 CTRDIR (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6_TBCLK	EPWM2 TBCLK (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPA	EPWM6 TBCLK (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6_CTR_CMPA	EPWM2 TBCTR = CMPA (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPB	EPWM6 TBCTR = CMPA (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6_CTR_CMPB	EPWM2 TBCTR = CMPB (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPC	EPWM6 TBCTR = CMPB (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6_CTR_CMPC	EPWM2 TBCTR = CMPC (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPD	EPWM6 TBCTR = CMPC (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6_CTR_CMPD	EPWM2 TBCTR = CMPD (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2A_AQ	EPWM6 TBCTR = CMPD (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6A_AQ	EPWM2A AQ submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2B_AQ	EPWM6A AQ submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6B_AQ	EPWM2B AQ submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2A_DB	EPWM6B AQ submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6A_DB	EPWM2A DB submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM2B_DB	EPWM6A DB submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM6B_DB	EPWM2B DB submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3A	EPWM6B DB submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7A	EPWM3A (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3A_OE	EPWM7A (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7A_OE	EPWM3A trip output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3B	EPWM7A trip output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7B	EPWM3B (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3B_OE	EPWM7B (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7B_OE	EPWM3B trip output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3_CTR_ZERO	EPWM7B trip output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7_CTR_ZERO	EPWM3 TBCTR = Zero (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3_CTR_PRD	EPWM7 TBCTR = Zero (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7_CTR_PRD	EPWM3 TBCTR = TBPRD (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR	EPWM7 TBCTR = TBPRD (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7_CTRDIR	EPWM3 CTRDIR (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3_TBCLK	EPWM7 CTRDIR (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7_TBCLK	EPWM3 TBCLK (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPA	EPWM7 TBCLK (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7_CTR_CMPA	EPWM3 TBCTR = CMPA (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPB	EPWM7 TBCTR = CMPA (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7_CTR_CMPB	EPWM3 TBCTR = CMPB (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPC	EPWM7 TBCTR = CMPB (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7_CTR_CMPC	EPWM3 TBCTR = CMPC (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPD	EPWM7 TBCTR = CMPC (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7_CTR_CMPD	EPWM3 TBCTR = CMPD (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3A_AQ	EPWM7 TBCTR = CMPD (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7A_AQ	EPWM3A AQ submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3B_AQ	EPWM7A AQ submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7B_AQ	EPWM3B AQ submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3A_DB	EPWM7B AQ submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7A_DB	EPWM3A DB submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM3B_DB	EPWM7A DB submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM7B_DB	EPWM3B DB submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4A	EPWM7B DB submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8A	EPWM4A (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4A_OE	EPWM8A (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8A_OE	EPWM4A trip output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4B	EPWM8A trip output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8B	EPWM4B (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4B_OE	EPWM8B (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8B_OE	EPWM4B trip output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4_CTR_ZERO	EPWM8B trip output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8_CTR_ZERO	EPWM4 TBCTR = Zero (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4_CTR_PRD	EPWM8 TBCTR = Zero (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8_CTR_PRD	EPWM4 TBCTR = TBPRD (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4_CTRDIR	EPWM8 TBCTR = TBPRD (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8_CTRDIR	EPWM4 CTRDIR (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4_TBCLK	EPWM8 CTRDIR (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8_TBCLK	EPWM4 TBCLK (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPA	EPWM8 TBCLK (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8_CTR_CMPA	EPWM4 TBCTR = CMPA (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPB	EPWM8 TBCTR = CMPA (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8_CTR_CMPB	EPWM4 TBCTR = CMPB (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPC	EPWM8 TBCTR = CMPB (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8_CTR_CMPC	EPWM4 TBCTR = CMPC (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPD	EPWM8 TBCTR = CMPC (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8_CTR_CMPD	EPWM4 TBCTR = CMPD (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4A_AQ	EPWM8 TBCTR = CMPD (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8A_AQ	EPWM4A AQ submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4B_AQ	EPWM8A AQ submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8B_AQ	EPWM4B AQ submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4A_DB	EPWM8B AQ submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8A_DB	EPWM4A DB submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_EPWM4B_DB	EPWM8A DB submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_EPWM8B_DB	EPWM4B DB submodule output (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB_AUXSIG0	EPWM8B DB submodule output (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB_AUXSIG1	CLB X-BAR AUXSIG0.
CLB_GLOBAL_IN_MUX_CLB_AUXSIG2	CLB X-BAR AUXSIG1.
CLB_GLOBAL_IN_MUX_CLB_AUXSIG3	CLB X-BAR AUXSIG2.
CLB_GLOBAL_IN_MUX_CLB_AUXSIG4	CLB X-BAR AUXSIG3.
CLB_GLOBAL_IN_MUX_CLB_AUXSIG5	CLB X-BAR AUXSIG4.
CLB_GLOBAL_IN_MUX_CLB_AUXSIG6	CLB X-BAR AUXSIG5.
CLB_GLOBAL_IN_MUX_CLB_AUXSIG7	CLB X-BAR AUXSIG6.
CLB_GLOBAL_IN_MUX_CLB1_OUT16	CLB X-BAR AUXSIG7.
CLB_GLOBAL_IN_MUX_CLB5_OUT16	CLB1 OUT16 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB1_OUT17	CLB5 OUT16 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB5_OUT17	CLB1 OUT17 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB1_OUT18	CLB5 OUT17 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB5_OUT18	CLB1 OUT18 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB1_OUT19	CLB5 OUT18 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB5_OUT19	CLB1 OUT19 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB1_OUT20	CLB5 OUT19 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB5_OUT20	CLB1 OUT20 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB1_OUT21	CLB5 OUT20 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB5_OUT21	CLB1 OUT21 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB1_OUT22	CLB5 OUT21 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB5_OUT22	CLB1 OUT22 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB1_OUT23	CLB5 OUT22 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB5_OUT23	CLB1 OUT23 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB2_OUT16	CLB5 OUT23 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB6_OUT16	CLB2 OUT16 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB2_OUT17	CLB6 OUT16 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB6_OUT17	CLB2 OUT17 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB2_OUT18	CLB6 OUT17 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB6_OUT18	CLB2 OUT18 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB2_OUT19	CLB6 OUT18 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB6_OUT19	CLB2 OUT19 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB2_OUT20	CLB6 OUT19 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB6_OUT20	CLB2 OUT20 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB2_OUT21	CLB6 OUT20 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB6_OUT21	CLB2 OUT21 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB2_OUT22	CLB6 OUT21 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB6_OUT22	CLB2 OUT22 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB2_OUT23	CLB6 OUT22 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB6_OUT23	CLB2 OUT23 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB3_OUT16	CLB6 OUT23 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CLB3_OUT17	CLB3 OUT16 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB3_OUT18	CLB3 OUT17 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB3_OUT19	CLB3 OUT18 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB3_OUT20	CLB3 OUT19 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB3_OUT21	CLB3 OUT20 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB3_OUT22	CLB3 OUT21 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB3_OUT23	CLB3 OUT22 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB4_OUT16	CLB3 OUT23 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB4_OUT17	CLB4 OUT16 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB4_OUT18	CLB4 OUT17 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB4_OUT19	CLB4 OUT18 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB4_OUT20	CLB4 OUT19 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB4_OUT21	CLB4 OUT20 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB4_OUT22	CLB4 OUT21 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CLB4_OUT23	CLB4 OUT22 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT0	CLB4 OUT23 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT0	CPU1 ERAD Event 0 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU1_ERAD_SEC_EVENT0	CPU2 ERAD Event 0 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT0	CPU1 ERAD SEC Event 0 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT1	CPU3 ERAD Event 0 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT1	CPU1 ERAD Event 1 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU1_ERAD_SEC_EVENT1	CPU2 ERAD Event 1 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT1	CPU1 ERAD SEC Event 1 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT2	CPU3 ERAD Event 1 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT2	CPU1 ERAD Event 2 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU1_ERAD_SEC_EVENT2	CPU2 ERAD Event 2 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT2	CPU1 ERAD SEC Event 2 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT3	CPU3 ERAD Event 2 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT3	CPU1 ERAD Event 3 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU1_ERAD_SEC_EVENT3	CPU2 ERAD Event 3 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT3	CPU1 ERAD SEC Event 3 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT4	CPU3 ERAD Event 3 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT4	CPU1 ERAD Event 4 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU2_ERAD_SEC_EVENT0	CPU2 ERAD Event 4 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT4	CPU2 ERAD SEC Event 0 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU3_ERAD_SEC_EVENT0	CPU3 ERAD Event 4 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT5	CPU3 ERAD SEC Event 0 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT5	CPU1 ERAD Event 5 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU2_ERAD_SEC_EVENT1	CPU2 ERAD Event 5 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT5	CPU2 ERAD SEC Event 1 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU3_ERAD_SEC_EVENT1	CPU3 ERAD Event 5 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT6	CPU3 ERAD SEC Event 1 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT6	CPU1 ERAD Event 6 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU2_ERAD_SEC_EVENT2	CPU2 ERAD Event 6 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT6	CPU2 ERAD SEC Event 2 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU3_ERAD_SEC_EVENT2	CPU3 ERAD Event 6 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT7	CPU3 ERAD SEC Event 2 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU2_ERAD_EVENT7	CPU1 ERAD Event 7 (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU2_ERAD_SEC_EVENT3	CPU2 ERAD Event 7 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU3_ERAD_EVENT7	CPU2 ERAD SEC Event 3 (CLB 5-6)
CLB_GLOBAL_IN_MUX_CPU3_ERAD_SEC_EVENT3	CPU3 ERAD Event 7 (CLB 5-6)
CLB_GLOBAL_IN_MUX_FSIRXA_DATA_PACKET_RCVD	CPU3 ERAD SEC Event 3 (CLB 5-6)
CLB_GLOBAL_IN_MUX_FSIRXA_PING_TAG_MATCH2	FSIRXA Data Packet Received (CLB 1-4)
CLB_GLOBAL_IN_MUX_FSIRXA_ERROR_PACKET_RCVD	FSIRXA PING TAG Match2 (CLB 5-6)
CLB_GLOBAL_IN_MUX_FSIRXA_CLB5_CLB6_DATA_TAG_MATCH2	FSIRXA Error Packet Received (CLB 1-4)
CLB_GLOBAL_IN_MUX_FSIRXA_PING_PACKET_RCVD	FSIRXA DATA TAG Match2 (CLB 5-6)
CLB_GLOBAL_IN_MUX_FSIRXA_ERROR_TAG_MATCH2	FSIRXA PING Packet Received (CLB 1-4)
CLB_GLOBAL_IN_MUX_FSIRXA_OUTPUT_FRAME_DONE	FSIRXA ERROR TAG Match2 (CLB 5-6)
CLB_GLOBAL_IN_MUX_FSIRXB_PING_TAG_MATCH	FSIRXA Output Frame Done (CLB 1-4)
CLB_GLOBAL_IN_MUX_FSIRXA_PING_TAG_MATCH1	FSIRXB PING TAG Match (CLB 5-6)
CLB_GLOBAL_IN_MUX_FSIRXB_DATA_TAG_MATCH	FSIRXA PING TAG Match2 (CLB 1-4)
CLB_GLOBAL_IN_MUX_FSIRXA_CLB1_CLB4_DATA_TAG_MATCH2	FSIRXB DATA TAG Match (CLB 5-6)
CLB_GLOBAL_IN_MUX_FSIRXB_ERROR_TAG_MATCH	FSIRXA DATA TAG Match2 (CLB 1-4)
CLB_GLOBAL_IN_MUX_FSIRXA_ERROR_TAG_MATCH1	FSIRXB ERROR TAG Match (CLB 5-6)
CLB_GLOBAL_IN_MUX_ECAT_SOF	FSIRXA ERROR TAG Match2 (CLB 1-4)
CLB_GLOBAL_IN_MUX_FSIRXA_RX_TRIG2	ECAT Start of Frame (CLB 5-6)
CLB_GLOBAL_IN_MUX_ECAT_EOF	FSIRXA RX Trig 2 (CLB 1-4)
CLB_GLOBAL_IN_MUX_SPI1_SPICLK	ECAT End of Frame (CLB 5-6)
CLB_GLOBAL_IN_MUX_SPI1_SPIPOCI_CONTROLLER	SPI1 SPICLK OUT (CLB 1-4)
CLB_GLOBAL_IN_MUX_SPI1_SPIPTE	SPI1 SPIPOCI Controller IN (CLB 1-4)
CLB_GLOBAL_IN_MUX_SPI2_SPICLK	SPI1 SPIPTE OUT (CLB 1-4)
CLB_GLOBAL_IN_MUX_SPI2_SPIPOCI_CONTROLLER	SPI2 SPICLK OUT (CLB 1-4)
CLB_GLOBAL_IN_MUX_SPI2_SPIPTE	SPI2 SPIPOCI Controller IN (CLB 1-4)
CLB_GLOBAL_IN_MUX_CPU3_HALT	SPI2 SPIPTE OUT (CLB 1-4)
CLB_GLOBAL_IN_MUX_ECAT_SYNC0	CPU3 HALT (CLB 1-4)
CLB_GLOBAL_IN_MUX_FSIRXA_RX_TRIG3	ECAT Sync 0 (CLB 5-6)
CLB_GLOBAL_IN_MUX_ECAT_SYNC1	FSIRXA RX Trig 3 (CLB 1-4)

Function Documentation

◆ CLB_isBaseValid()

static bool CLB_isBaseValid ( uint32_t base )

inlinestatic

Checks the CLB base address.

Parameters

base	is the base address of a CLB tile's logic config register.

This function determines if a CLB base address is valid.

Returns: Returns true if the base address is valid and false otherwise.

◆ CLB_isAddressValid()

static bool CLB_isAddressValid ( uint32_t address )

inlinestatic

Checks the CLB internal memory address.

Parameters

base	is the base address of a CLB tile's logic config register.

This function determines if a CLB base address is valid.

Returns: Returns true if the address is valid and false otherwise.

◆ CLB_enableCLB()

static void CLB_enableCLB ( uint32_t base )

inlinestatic

Set global enable.

Parameters

base	is the base address of a CLB tile's logic config register.

This function enables the CLB via global enable register.

Returns: None.

◆ CLB_disableCLB()

static void CLB_disableCLB ( uint32_t base )

inlinestatic

Clear global enable.

Parameters

base	is the base address of a CLB tile's logic config register.

This function disables the CLB via global enable register.

Returns: None.

◆ CLB_enableNMI()

static void CLB_enableNMI ( uint32_t base )

inlinestatic

Enable HLC NMI.

Parameters

base	is the base address of a CLB tile's logic config register.

This function enables the CLB HLC NMI.

Returns: None.

◆ CLB_disableNMI()

static void CLB_disableNMI ( uint32_t base )

inlinestatic

Disable HLC NMI.

Parameters

base	is the base address of a CLB tile's logic config register.

This function disables the CLB HLC NMI.

Returns: None.

◆ CLB_configureClockPrescalar()

static void CLB_configureClockPrescalar	(	uint32_t	base,
		uint16_t	prescl )

inlinestatic

Configure Clock Prescalar.

Parameters

base	is the base address of a CLB tile's logic config register.

This function enables and configures the CLB Clock Precalar.

Returns: None.

◆ CLB_configureStrobeMode()

static void CLB_configureStrobeMode	(	uint32_t	base,
		uint16_t	strb )

inlinestatic

Configures Clock Precalar Strobe Mode.

Parameters

base	is the base address of a CLB tile's logic config register.

This function enables and configures the CLB Clock Precalar Strobe Mode.

Returns: None.

◆ CLB_writeSWReleaseControl()

static void CLB_writeSWReleaseControl	(	uint32_t	base,
		CLB_SWReleaseCtrl	inID,
		bool	val )

inlinestatic

Configures the general purpose SW release control value.

Parameters

base	is the base address of a CLB tile's logic config register.
inID	is the specified CLB SW Release input signal.
val	is the value of the SW RLS control.

This function configures the general purpose SW release control value. The inID parameter can have one enumeration value from CLB_SWReleaseCtrl.

Returns: None.

◆ CLB_writeSWGateControl()

static void CLB_writeSWGateControl	(	uint32_t	base,
		CLB_SWGateCtrl	inID,
		bool	val )

inlinestatic

Configures the general purpose SW gate control value.

Parameters

base	is the base address of a CLB tile's logic config register.
inID	is the specified CLB SW Release input signal.
val	is the value of the SW GATE control.

This function configures the general purpose SW release control value. The inID parameter can have one enumeration value from CLB_SWGateCtrl.

Returns: None.

◆ CLB_configCounterTapSelects()

static void CLB_configCounterTapSelects	(	uint32_t	base,
		uint32_t	tapSel )

inlinestatic

Configures Counter TAP Selects.

Parameters

base	is the base address of a CLB tile's logic config register.
miscCtrl	is the value to represent counter tap selects. Generated by tool as TILEx_CFG_TAP_SELL.

This function configures the counter tap selects.

Returns: None.

◆ CLB_configAOC()

static void CLB_configAOC	(	uint32_t	base,
		CLB_AOCs	aocID,
		uint32_t	aocCfg )

inlinestatic

Configures AOC (Asynchronous Output Conditioning) functions.

Parameters

base	is the base address of a CLB tile's logic config register.
aocID	is the specified CLB tile AOC signal.
aocCfg	is the value for the AOC signal function and input signal selections. Generated by tool as TILEx_OUTPUT_COND_CTR_n where n is the output number.

This function configures the input signals and equations of the aoc LUT corresponding to the /e aocID parameter.

Returns: None.

◆ CLB_enableLock()

static void CLB_enableLock ( uint32_t base )

inlinestatic

Enable CLB lock.

Parameters

base	is the base address of a CLB tile's logic config register.

This function enables the lock bit of the lock register. The lock can only be set once and can only be cleared by a device reset.

Returns: None.

◆ CLB_writeInterface()

static void CLB_writeInterface	(	uint32_t	base,
		uint32_t	address,
		uint32_t	value )

inlinestatic

Write value to address.

Parameters

base	is the base address of a CLB tile's logic config register.
address	is the address of CLB internal memory.
value	is the value to write to specified address.

This function writes the specified value to CLB internal memory.

Returns: None.

◆ CLB_selectInputFilter()

static void CLB_selectInputFilter	(	uint32_t	base,
		CLB_Inputs	inID,
		CLB_FilterType	filterType )

inlinestatic

Select input filter type.

Parameters

base	is the base address of a CLB tile's logic config register.
inID	is the specified CLB tile input signal.
filterType	is the selected type of filter applied to the input.

This function configures the filter selection for the specified input. The inID parameter can have one enumeration value from CLB_Inputs. The filterType parameter can have one enumeration value from CLB_FilterType.

Returns: None.

◆ CLB_enableSynchronization()

static void CLB_enableSynchronization	(	uint32_t	base,
		CLB_Inputs	inID )

inlinestatic

Enables synchronization of an input signal.

Parameters

base	is the base address of a CLB tile's logic config register.
inID	is the specified CLB tile input signal.

This function enables synchronization on the specified input signal. The inID parameter can have one enumeration value from CLB_Inputs.

Returns: None.

◆ CLB_disableSynchronization()

static void CLB_disableSynchronization	(	uint32_t	base,
		CLB_Inputs	inID )

inlinestatic

Disables synchronization of an input signal.

Parameters

base	is the base address of a CLB tile's logic config register.
inID	is the specified CLB tile input signal.

This function disables synchronization on the specified input signal. The inID parameter can have one enumeration value from CLB_Inputs.

Returns: None.

◆ CLB_configGPInputMux()

static void CLB_configGPInputMux	(	uint32_t	base,
		CLB_Inputs	inID,
		CLB_GPInputMux	gpMuxCfg )

inlinestatic

Configures the general purpose input mux.

Parameters

base	is the base address of a CLB tile's logic config register.
inID	is the specified CLB tile input signal.
gpMuxCfg	is the mux selection for the general purpose input mux.

This function configures the general purpose input mux. The gpMuxCfg parameter can select either the use of an external input signal (CLB_GP_IN_MUX_EXTERNAL) or the use of the corresponding CLB_GP_REG bit as an input (CLB_GP_IN_MUX_GP_REG). The inID parameter can have one enumeration value from CLB_Inputs.

See also: CLB_setGPREG() to write to the CLB_GP_REG.

Returns: None.

◆ CLB_setGPREG()

static void CLB_setGPREG	(	uint32_t	base,
		uint32_t	gpRegVal )

inlinestatic

Sets the CLB_GP_REG register value.

Parameters

base	is the base address of a CLB tile's logic config register.
gpRegVal	is the value to be written to CLB_GP_REG.

This function writes to the CLB_GP_REG register. When the general purpose input mux is configured to use CLB_GP_REG, each bit in gpRegVal corresponds to an input signal (bit 0 to Input 0, bit 1 to Input 1, and so on).

See also: CLB_configGPInputMux() to select the CLB_GP_REG as the source for an input signal.

Returns: None.

◆ CLB_getGPREG()

static uint32_t CLB_getGPREG ( uint32_t base )

inlinestatic

Gets the CLB_GP_REG register value.

Parameters

base	is the base address of a CLB tile's logic config register.

This function writes to the CLB_GP_REG register. When the general purpose input mux is configured to use CLB_GP_REG, each bit in gpRegVal corresponds to an input signal (bit 0 to Input 0, bit 1 to Input 1, and so on).

See also: CLB_configGPInputMux() to select the CLB_GP_REG as the source for an input signal.

Returns: CLB_GP_REG value.

◆ CLB_configLocalInputMux()

static void CLB_configLocalInputMux	(	uint32_t	base,
		CLB_Inputs	inID,
		CLB_LocalInputMux	localMuxCfg )

inlinestatic

Configures the local input mux.

Parameters

base	is the base address of a CLB tile's logic config register.
inID	is the specified CLB tile input signal.
localMuxCfg	is the mux selection for the local input mux.

This function configures the local input mux for the specified input signal.

The inID parameter can have one enumeration value from CLB_Inputs. The localMuxCfg parameter can have one enumeration value from CLB_LocalInputMux.

Note: The local input mux options' peripheral sources depend on which instance of the CLB (base) you are using. For example, for CLB1 the EPWM signal selections come from EPWM1 but for CLB2 they come from EPWM2. See your technical reference manual for details.

Returns: None.

◆ CLB_configGlobalInputMux()

static void CLB_configGlobalInputMux	(	uint32_t	base,
		CLB_Inputs	inID,
		CLB_GlobalInputMux	globalMuxCfg )

inlinestatic

Configures the global input mux.

Parameters

base	is the base address of a CLB tile's logic config register.
inID	is the specified CLB tile input signal.
globalMuxCfg	is the mux selection for the global input mux.

This function configures the global input mux for the specified input signal. The inID parameter can have one enumeration value from CLB_Inputs. The globalMuxCfg parameter can have one enumeration value from CLB_GlobalInputMux.

Note: The global input mux options' peripheral sources depend on which instance of the CLB (base) you are using. For example, for CLB1 the EPWM signal selections come from EPWM1 but for CLB2 they come from EPWM2. See your technical reference manual for details.

Returns: None.

◆ CLB_setOutputMask()

static void CLB_setOutputMask	(	uint32_t	base,
		uint32_t	outputMask,
		bool	enable )

inlinestatic

Controls the output enable.

Parameters

base	is the base address of a CLB tile's logic config register.
outputMask	is a mask of the outputs to be enabled.
enable	is a switch to decide if the CLB outputs need to be enabled or not.

This function is used to enable and disable CLB outputs by writing a mask to CLB_OUT_EN. Each bit corresponds to a CLB output. When a bit is 1, the corresponding output is enabled; when a bit is 0, the output is disabled.

The outputMask parameter takes a logical OR of any of the CLB_OUTPUT_0x values that correspond to the CLB OUTPUT ENABLE for the respective outputs. The enable parameter can have one of the values from: false: Disable the respective CLB outputs true: Enable the respective CLB outputs

Note: Note that the 8 CLB outputs are replicated to create more output paths. See your technical reference manual for more details. If no further modifications are expected, then it is advised to set the block writes bit of the MISC_ACCESS_CTRL Register. This will prevent accidental writes.

Returns: None.

◆ CLB_getInterruptTag()

static uint16_t CLB_getInterruptTag ( uint32_t base )

inlinestatic

Reads the interrupt tag register.

Parameters

base	is the base address of a CLB tile's logic config register.

Returns: Returns the value in the interrupt tag register which is a 6-bit constant set by the HLC.

◆ CLB_clearInterruptTag()

static void CLB_clearInterruptTag ( uint32_t base )

inlinestatic

Clears the interrupt tag register.

Parameters

base	is the base address of a CLB tile's logic config register.

This function clears the interrupt tag register, setting it to 0.

Returns: None.

◆ CLB_selectLUT4Inputs()

static void CLB_selectLUT4Inputs	(	uint32_t	base,
		uint32_t	lut4In0,
		uint32_t	lut4In1,
		uint32_t	lut4In2,
		uint32_t	lut4In3 )

inlinestatic

Selects LUT4 inputs.

Parameters

base	is the base address of a CLB tile's logic config register.
lut4In0	is the value for LUT4 input signal 0. Generated by tool as TILEx_CFG_LUT4_IN0.
lut4In1	is the value for LUT4 input signal 1. Generated by tool as TILEx_CFG_LUT4_IN1.
lut4In2	is the value for LUT4 input signal 2. Generated by tool as TILEx_CFG_LUT4_IN2.
lut4In3	is the value for LUT4 input signal 3. Generated by tool as TILEx_CFG_LUT4_IN3.

This function configures the LUT4 block's input signals.

Returns: None.

◆ CLB_configLUT4Function()

static void CLB_configLUT4Function	(	uint32_t	base,
		uint32_t	lut4Fn10,
		uint32_t	lut4Fn2 )

inlinestatic

Configures LUT4 functions.

Parameters

base	is the base address of a CLB tile's logic config register.
lut4Fn10	is the equation value for LUT4 blocks 0 and 1. Generated by tool as TILEx_CFG_LUT4_FN10.
lut4Fn2	is the equation value for LUT4 block2. Generated by tool as TILEx_CFG_LUT4_FN2.

This function configures the LUT4 block's equations.

Returns: None.

◆ CLB_selectFSMInputs()

static void CLB_selectFSMInputs	(	uint32_t	base,
		uint32_t	external0,
		uint32_t	external1,
		uint32_t	extra0,
		uint32_t	extra1 )

inlinestatic

Selects FSM inputs.

Parameters

base	is the base address of a CLB tile's logic config register.
external0	is the value for FSM external 0 input. Generated by tool as TILEx_CFG_FSM_EXT_IN0.
external1	is the value for FSM external 1 input. Generated by tool as TILEx_CFG_FSM_EXT_IN1.
extra0	is the value for FSM extra 0 input. Generated by tool as TILEx_CFG_FSM_EXTRA_IN0.
extra1	is the value for FSM extra 1 input. Generated by tool as TILEx_CFG_FSM_EXTRA_IN1.

This function configures the FSM block's external inputs and extra external inputs.

Returns: None.

◆ CLB_configFSMLUTFunction()

static void CLB_configFSMLUTFunction	(	uint32_t	base,
		uint32_t	fsmLutFn10,
		uint32_t	fsmLutFn2 )

inlinestatic

Configures FSM LUT function.

Parameters

base	is the base address of a CLB tile's logic config register.
fsmLutFn10	is the value for FSM 0 & FSM 1 LUT function. Generated by tool as TILEx_CFG_FSM_LUT_FN10.
fsmLutFn2	is the value for FSM 2 LUT function. Generated by tool as TILEx_CFG_FSM_LUT_FN2.

This function configures the FSM block's LUT equations.

Returns: None.

◆ CLB_configFSMNextState()

static void CLB_configFSMNextState	(	uint32_t	base,
		uint32_t	nextState0,
		uint32_t	nextState1,
		uint32_t	nextState2 )

inlinestatic

Configures FSM next state.

Parameters

base	is the base address of a CLB tile's logic config register.
nextState0	is the value for FSM 0's next state. Generated by tool as TILEx_CFG_FSM_NEXT_STATE_0.
nextState1	is the value for FSM 1's next state. Generated by tool as TILEx_CFG_FSM_NEXT_STATE_1.
nextState2	is the value for FSM 2's next state. Generated by tool as TILEx_CFG_FSM_NEXT_STATE_2.

This function configures the FSM's next state equation.

Returns: None.

◆ CLB_selectCounterInputs()

static void CLB_selectCounterInputs	(	uint32_t	base,
		uint32_t	reset,
		uint32_t	event,
		uint32_t	mode0,
		uint32_t	mode1 )

inlinestatic

Selects Counter inputs.

Parameters

base	is the base address of a CLB tile's logic config register.
reset	is the value for counter's reset inputs. Generated by tool as TILEx_CFG_COUNTER_RESET.
event	is the value for counter's event inputs. Generated by tool as TILEx_CFG_COUNTER_EVENT.
mode0	is the value for counter's mode 0 inputs. Generated by tool as TILEx_CFG_COUNTER_MODE_0.
mode1	is the value for counter's mode 1 inputs. Generated by tool as TILEx_CFG_COUNTER_MODE_1.

This function selects the input signals to the counter block.

Returns: None.

◆ CLB_configMiscCtrlModes()

static void CLB_configMiscCtrlModes	(	uint32_t	base,
		uint32_t	miscCtrl )

inlinestatic

Configures Counter and FSM modes.

Parameters

base	is the base address of a CLB tile's logic config register.
miscCtrl	is the value to represent counter and FSM modes. Generated by tool as TILEx_CFG_MISC_CONTROL.

This function configures the counter mode, particularly add/shift, load modes. The function also configures whether the FSM should use state inputs or an extra external input.

Returns: None.

◆ CLB_configOutputLUT()

static void CLB_configOutputLUT	(	uint32_t	base,
		CLB_Outputs	outID,
		uint32_t	outputCfg )

inlinestatic

Configures Output LUT functions.

Parameters

base	is the base address of a CLB tile's logic config register.
outID	is the specified CLB tile output signal.
outputCfg	is the value for the output LUT signal function and input signal selections. Generated by tool as TILEx_CFG_OUTLUT_n where n is the output number.

This function configures the input signals and equations of the output LUT corresponding to the /e outID parameter.

Returns: None.

◆ CLB_configHLCEventSelect()

static void CLB_configHLCEventSelect	(	uint32_t	base,
		uint32_t	eventSel )

inlinestatic

Configures HLC event selection.

Parameters

base	is the base address of a CLB tile's logic config register.
eventSel	is the value for HLC event selection. Generated by tool as TILEx_HLC_EVENT_SEL.

This function configures the event selection for the High Level Controller.

Returns: None.

◆ CLB_programHLCInstruction()

static void CLB_programHLCInstruction	(	uint32_t	base,
		uint32_t	instructionNum,
		uint32_t	instruction )

inlinestatic

Program HLC instruction.

Parameters

base	is the base address of a CLB tile's logic config register.
instructionNum	is the index into the HLC instruction memory. For example, a value of 0 corresponds to instruction 0 of event 0, a value of 1 corresponds to instruction 1 of event 0, and so on up to a value of 31 which corresponds to instruction 7 of event 3.
instruction	is the instruction to be programmed. Generated by tool as TILEx_HLCINSTR_n where n is the instruction number.

This function configures the CLB internal memory corresponding to the specified HLC instruction number with the given instruction.

Returns: None.

◆ CLB_setHLCRegisters()

static void CLB_setHLCRegisters	(	uint32_t	base,
		uint32_t	r0Init,
		uint32_t	r1Init,
		uint32_t	r2Init,
		uint32_t	r3Init )

inlinestatic

Set HLC registers.

Parameters

base	is the base address of a CLB tile's logic config register.
r0Init	is the value to write to HLC register R0. Generated by tool as TILEx_HLC_R0_INIT.
r1Init	is the value to write to HLC register R1. Generated by tool as TILEx_HLC_R1_INIT.
r2Init	is the value to write to HLC register R2. Generated by tool as TILEx_HLC_R2_INIT.
r3Init	is the value to write to HLC register R3. Generated by tool as TILEx_HLC_R3_INIT.

This function configures the CLB internal memory corresponding to the HLC registers R0-R3 with the specified values.

Returns: None.

◆ CLB_getRegister()

static uint32_t CLB_getRegister	(	uint32_t	base,
		CLB_Register	registerID )

inlinestatic

Get HLC or counter register values.

Parameters

base	is the base address of a CLB tile's logic config register.
registerID	is the internal register from which to read. Can be either an HLC register (CLB_REG_HLC_Rn) or a counter value (CLB_REG_CTR_Cn).

Returns: Returns the value in the specified HLC register or counter.

◆ CLB_getOutputStatus()

static uint32_t CLB_getOutputStatus ( uint32_t base )

inlinestatic

Get output status.

Parameters

base	is the base address of a CLB tile's logic config register.

Returns: Returns the output status of various components within the CLB tile such as a counter match or LUT output. Use the CLB_DBG_OUT_* masks from hw_clb.h to decode the bits.

◆ CLB_enablePipelineMode()

static void CLB_enablePipelineMode ( uint32_t base )

inlinestatic

Enable CLB Pipeline Mode.

Parameters

base	is the base address of a CLB tile's logic config register.

This function enables the CLB Pipeline Mode

Returns: None.

◆ CLB_disablePipelineMode()

static void CLB_disablePipelineMode ( uint32_t base )

inlinestatic

Disable CLB Pipeline Mode.

Parameters

base	is the base address of a CLB tile's logic config register.

This function disables the CLB Pipeline Mode.

Returns: None.

◆ CLB_disableOutputMaskUpdates()

static void CLB_disableOutputMaskUpdates ( uint32_t base )

inlinestatic

Disable CLB Output Mask Updates.

Parameters

base	is the base address of a CLB tile's logic config register.

This function disables the CLB Output Mask updates

Returns: None.

◆ CLB_enableOutputMaskUpdates()

static void CLB_enableOutputMaskUpdates ( uint32_t base )

inlinestatic

Enable CLB Output Mask Updates.

Parameters

base	is the base address of a CLB tile's logic config register.

This function enables the CLB Output Mask updates

Returns: None.

◆ CLB_enableInputPipelineMode()

static void CLB_enableInputPipelineMode	(	uint32_t	base,
		CLB_Inputs	inID )

inlinestatic

Enable Input Pipeline Mode.

Parameters

base	is the base address of a CLB tile's logic config register.

This function enables the CLB Input Pipeline mode

Returns: None.

◆ CLB_disableInputPipelineMode()

static void CLB_disableInputPipelineMode	(	uint32_t	base,
		CLB_Inputs	inID )

inlinestatic

Disable Input Pipeline Mode.

Parameters

base	is the base address of a CLB tile's logic config register.

This function disables the CLB Input Pipeline mode

Returns: None.

◆ CLB_disableSPIBufferAccess()

static void CLB_disableSPIBufferAccess ( uint32_t base )

inlinestatic

Disable SPI RX Buffer Access.

Parameters

base	is the base address of a CLB tile's logic config register.

This function disables the CLB SPI RX Buffer access

Returns: None.

◆ CLB_enableSPIBufferAccess()

static void CLB_enableSPIBufferAccess ( uint32_t base )

inlinestatic

Enable SPI RX Buffer Access.

Parameters

base	is the base address of a CLB tile's logic config register.

This function enables the CLB SPI RX Buffer access

Returns: None.

◆ CLB_configSPIBufferLoadSignal()

static void CLB_configSPIBufferLoadSignal	(	uint32_t	base,
		uint16_t	eventSel )

inlinestatic

Configures SPI RX Buffer Load Signal event selection.

Parameters

base	is the base address of a CLB tile's logic config register.
eventSel	is the value for HLC event selection. Generated by tool as TILEx_SPI_BUF_EVENT_SEL.

This function configures the event selection for the SPI RX Buffer.

Returns: None.

◆ CLB_configSPIBufferShift()

static void CLB_configSPIBufferShift	(	uint32_t	base,
		uint16_t	shiftVal )

inlinestatic

Configures SPI Export HLC R0 Shift value.

Parameters

base	is the base address of a CLB tile's logic config register.
shiftVal	is the value for SPI export HLC R0 bit range selection.

This function configures the SPI Export HLC R0 Shift value.

Returns: None.

◆ CLB_enableSPIStrobeDelay()

static void CLB_enableSPIStrobeDelay ( uint32_t base )

inlinestatic

Enables strobe delay event for SPI.

Parameters

base	is the base address of a CLB tile's logic config register.

This function enables the delay for selected strobe event by 4-CLB clock cycles to SPI module.

Returns: None.

◆ CLB_disableSPIStrobeDelay()

static void CLB_disableSPIStrobeDelay ( uint32_t base )

inlinestatic

Disables strobe delay event for SPI.

Parameters

base	is the base address of a CLB tile's logic config register.

This function disables the delay for selected strobe event.

Returns: None.

◆ CLB_configCounterLoadMatch()

void CLB_configCounterLoadMatch	(	uint32_t	base,
		CLB_Counters	counterID,
		uint32_t	load,
		uint32_t	match1,
		uint32_t	match2 )

extern

Configures Counter load and match.

Parameters

base	is the base address of a CLB tile's logic config register.
counterID	is the specified counter unit.
load	is the value for counter's load mode. Generated by tool as TILEx_COUNTER_n_LOAD_VAL where n is the counter number.
match1	is the value for counter's match 1. Generated by tool as TILEx_COUNTER_n_MATCH1_VAL where n is the counter number.
match2	is the value for counter's match 2. Generated by tool as TILEx_COUNTER_n_MATCH2_VAL where n is the counter number.

This function configures the CLB internal memory corresponding to the counter block's load and match values.

Returns: None.

◆ CLB_clearFIFOs()

void CLB_clearFIFOs ( uint32_t base )

extern

Clear FIFO registers.

Parameters

base	is the base address of a CLB tile's logic config register.

This function clears the PUSH/PULL FIFOs as well as its pointers.

Returns: None.

◆ CLB_writeFIFOs()

void CLB_writeFIFOs	(	uint32_t	base,
		const uint32_t	pullData[] )

extern

Configure the FIFO registers.

Parameters

base	is the base address of a CLB tile's logic config register.
pullData[]	is a pointer to an array of bytes which needs to be written into the FIFO. The 0th FIFO data is in the 0th index.

This function writes to the PULL FIFO. This also clears the FIFOs and its pointer using the CLB_clearFIFOs() API prior to writing to the FIFO.

Returns: None.

◆ CLB_readFIFOs()

void CLB_readFIFOs	(	uint32_t	base,
		uint32_t	pushData[] )

extern

Read FIFO registers.

Parameters

base	is the base address of a CLB tile's logic config register.
pushData[]	is a pointer to an array of bytes which needs to be read from the FIFO.

This function reads from the PUSH FIFO. The 0th FIFO data would be in the 0th index.

Returns: None.

Introduction

Functions

Enumerations

Macros

Macro Definition Documentation

◆ CLB_LOGICCTL

◆ CLB_DATAEXCH

◆ CLB_ADDR_COUNTER_0_LOAD

◆ CLB_ADDR_COUNTER_1_LOAD

◆ CLB_ADDR_COUNTER_2_LOAD

◆ CLB_ADDR_COUNTER_0_MATCH1

◆ CLB_ADDR_COUNTER_1_MATCH1

◆ CLB_ADDR_COUNTER_2_MATCH1

◆ CLB_ADDR_COUNTER_0_MATCH2

◆ CLB_ADDR_COUNTER_1_MATCH2

◆ CLB_ADDR_COUNTER_2_MATCH2

◆ CLB_ADDR_HLC_R0

◆ CLB_ADDR_HLC_R1

◆ CLB_ADDR_HLC_R2

◆ CLB_ADDR_HLC_R3

◆ CLB_ADDR_HLC_BASE

◆ CLB_NUM_HLC_INSTR

◆ CLB_FIFO_SIZE

◆ CLB_LOCK_KEY

◆ CLB_LCL_MUX_SEL_MISC_INPUT_SEL_M

◆ CLB_LCL_MUX_SEL_MISC_INPUT_SEL_S

◆ CLB_LCL_MUX_SEL_MISC_INPUT_SEL_BITM

◆ CLB_OUTPUT_00

◆ CLB_OUTPUT_01

◆ CLB_OUTPUT_02

◆ CLB_OUTPUT_03

◆ CLB_OUTPUT_04

◆ CLB_OUTPUT_05

◆ CLB_OUTPUT_06

◆ CLB_OUTPUT_07

◆ CLB_OUTPUT_08

◆ CLB_OUTPUT_09

◆ CLB_OUTPUT_10

◆ CLB_OUTPUT_11

◆ CLB_OUTPUT_12

◆ CLB_OUTPUT_13

◆ CLB_OUTPUT_14

◆ CLB_OUTPUT_15

◆ CLB_OUTPUT_16

◆ CLB_OUTPUT_17

◆ CLB_OUTPUT_18

◆ CLB_OUTPUT_19

◆ CLB_OUTPUT_20

◆ CLB_OUTPUT_21

◆ CLB_OUTPUT_22

◆ CLB_OUTPUT_23

◆ CLB_OUTPUT_24

◆ CLB_OUTPUT_25

◆ CLB_OUTPUT_26

◆ CLB_OUTPUT_27

◆ CLB_OUTPUT_28

◆ CLB_OUTPUT_29

◆ CLB_OUTPUT_30

◆ CLB_OUTPUT_31

Enumeration Type Documentation

◆ CLB_Inputs

◆ CLB_Outputs

◆ CLB_AOCs

◆ CLB_SWReleaseCtrl

◆ CLB_SWGateCtrl

◆ CLB_Counters

◆ CLB_Register

◆ CLB_FilterType

◆ CLB_GPInputMux

◆ CLB_LocalInputMux

◆ CLB_GlobalInputMux

Function Documentation

◆ CLB_isBaseValid()

◆ CLB_isAddressValid()

◆ CLB_enableCLB()

◆ CLB_disableCLB()

◆ CLB_enableNMI()

◆ CLB_disableNMI()

◆ CLB_configureClockPrescalar()

◆ CLB_configureStrobeMode()