An I2C master controls the clock speed and provides SCL on the line. It is possible for the slave device to “stretch” or hold the clock and alt the data or commands transmission from the master. Clock stretching is mainly used to hold the master device when the slave device is swamped. An I2C slave device can use clock stretching to push the master device into a wait state. When a slave device requires longer time to manage data, such as store received data or prepare to transmit another byte of data, it may execute clock stretching. This usually happens after the slave device has acknowledged receiving a byte of data.

The clock stretching pauses the transaction by holding the SCL line LOW. The data transaction cannot be completed until SCL line held HIGH. Clock stretching is optional and in fact, most target devices do not include an SCL driver, so they are unable to stretch the clock.

A device may be able to receive bytes of data quickly at the byte level, but it takes longer to store a received byte or prepare another byte for transmission. After receiving and acknowledging a byte, targets can keep the SCL line LOW to force the controller into a wait state until the target is ready for the next byte transfer, like a handshake operation.

A device, such as a microcontroller with or without limited I2C-bus hardware, can slow down the bus clock by lengthening each clock LOW period on the bit level. Any controller’s speed is adjusted to the device’s internal operating rate.

‍This program uses the extended clock stretching mode of the I2C module. Both the TX and RX I2C Non-FIFOs and their interrupts are used.

‍A stream of data is sent and then compared to the received stream.