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The file implements the register level functions for HMAC/HASH module using SHA/MD5 algorithms. No validations are performed on input parameters. The caller of the APIs need to ensure the input parameters are valid. More...
#include <stdint.h>
#include <string.h>
#include <ti/drivers/osal/MemoryP.h>
#include <ti/drivers/crypto/include/crypto_internal.h>
#include <ti/common/hw_types.h>
Macros | |
#define | P_EIP57T_INTERRUPT_MASK (0x00000007U) |
Functions | |
void | HMAC_init (DTHERegs *dtheBaseAddress, SHARegs *hmacBaseAddress) |
void | HMAC_setConfig (SHARegs *hmacBaseAddress, uint32_t cryptoMode, uint8_t useAlgoConstant, uint8_t closeHash, uint8_t useHMACKey, uint8_t HMACOuterHash) |
uint32_t | HMAC_isReady (const SHARegs *hmacBaseAddress, uint32_t flag) |
void | HMAC_setDataLength (SHARegs *hmacBaseAddress, uint32_t dataLength) |
void | HMAC_writeData (SHARegs *hmacBaseAddress, const uint8_t *ptrData) |
uint32_t | HMAC_getDigestSize (uint32_t config) |
void | HMAC_readResult (SHARegs *hmacBaseAddress, uint8_t *ptrData) |
void | HMAC_writeResult (SHARegs *hmacBaseAddress, uint8_t *ptrData) |
uint32_t | HMAC_readDigestCount (SHARegs *hmacBaseAddress) |
void | HMAC_writeDigestCount (SHARegs *hmacBaseAddress, uint32_t digestCount) |
void | HMAC_setHMACKey (SHARegs *hmacBaseAddress, const uint8_t *ptrKey) |
void | HMAC_setHMACPPKey (SHARegs *hmacBaseAddress, const uint8_t *ptrKey) |
void | HMAC_enableInterrupt (DTHERegs *dtheBaseAddress, SHARegs *hmacBaseAddress, uint32_t intFlags) |
void | HMAC_disableInterrupt (DTHERegs *dtheBaseAddress, SHARegs *hmacBaseAddress, uint32_t intFlags) |
void | HMAC_clearInterrupt (DTHERegs *dtheBaseAddress, uint32_t intFlags) |
uint32_t | HMAC_getInterruptStatus (DTHERegs *dtheBaseAddress, SHARegs *hmacBaseAddress, uint8_t masked) |
The file implements the register level functions for HMAC/HASH module using SHA/MD5 algorithms. No validations are performed on input parameters. The caller of the APIs need to ensure the input parameters are valid.
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#define P_EIP57T_INTERRUPT_MASK (0x00000007U) |
Interrupt masks