Resource Management UDMAP TISCI Message Description¶
Introduction¶
This chapter provides information on usage of the RM UDMAP management TISCI message API parameters.
UDMAP Valid Parameters Field Usage¶
Some UDMAP TISCI message APIs make use of a valid_params bit field. Bits within the valid_params field define whether or not individual TISCI message parameters are valid. When a bit corresponding to a parameter is set (to 1) the parameter is considered valid and will be programmed into its corresponding register field, assuming validation of the parameter passes. When a valid_params bit is not set, i.e. a value of 0, the corresponding register field is read and used within the validation process of the request. The register field for a parameter is not programmed if the corresponding valid_params bit is not set.
TISCI_MSG_RM_UDMAP_TX_CH_CFG - UDMAP Transmit Channel Configure¶
UDMAP Transmit Channel Configure Request¶
The UDMAP tx channel cfg TISCI message API is used to configure SoC Navigator Subsystem UDMAP transmit channels. The API only allows configuration of a transmit channel by passing the tx channel index and the Navigator SoC device ID in which the channel is located. Only the non-real-time transmit channel registers are programmed as part of the channel configuration. The host is granted access to the transmit channel real-time registers via the SoC channelized firewalls based on the RM board configuration. The OS can access the channel real-time registers directly after transmit channel configuration is complete.
The UDMAP global invalid receive flow event and per transmit channel output event (OES) and error output event (EOES) registers are not programmed as part of the UDMAP tx channel cfg API. They’re programmed internally via the RM IRQ Set message.
The UDMAP tx channel cfg API can be used to configure transmit channels within any Navigator Subsystem UDMAP on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_TX_CH_CFG (0x1205U)
RM TISCI message to configure a Navigator Subsystem UDMAP transmit channel
UDMAP Transmit Channel Configure Message Parameters¶
| Parameter | Type | Valid Values | Description |
|---|---|---|---|
| hdr | Generic TISCI message header (8 bytes) | Valid Host IDs | Generic TISCI message header. Contains the message ID, host ID, sequence number, and any flags |
| valid_params | u32 | UDMAP Transmit Channel Configuration Valid Parameters | Bitfield defining validity of UDMAP transmit channel configuration parameters. The channel configuration fields are not valid, and will not be used, if their corresponding valid bit is zero. |
| nav_id | u16 | Valid Navigator Subsystem UDMAP Device IDs | The SoC-specific Device ID of the Navigator subsystem UDMAP in which the transmit channel is located. |
| index | u16 | Valid Navigator Subsystem Transmit Channel Indices | Specifies the requested transmit channel index for configuration |
| tx_pause_on_err | u8 |
|
Transmit channel pause on error configuration. The register field is programmed if tx_pause_on_err’s valid bit is set. |
| tx_filt_einfo | u8 |
|
Transmit channel extended packet information. The register field is programmed if tx_filt_einfo’s valid bit is set. |
| tx_filt_pswords | u8 |
|
Transmit channel protocol specific word passing. The register field is programmed if tx_filt_pswords’s valid bit is set. |
| tx_atype | u8 |
|
Transmit channel non Ring Accelerator access pointer interpretation configuration. The register field is programmed if tx_atype’s valid bit is set. |
| tx_chan_type | u8 | (2) - Packet transfers using pass by reference rings, (10) - 3rd party DMA transfers using pass by reference rings, (11) - 3rd party DMA transfers using pass by value rings, (12) - 3rd party block copy DMA transfers using pass by reference rings, (13) - 3rd party block copy DMA transfers using pass by value rings | Transmit channel functional channel type and work passing mechanism. | Transmit channel functional channel type and work passing mechanism. The parameter is valid if tx_chan_type’s valid bit is set. |
| tx_supr_tdpkt | u8 |
|
Transmit channel tear down packet generation suppression. The register field is programmed if tx_supr_tdpkt’s valid bit is set. |
| tx_fetch_size | u16 | Cannot be greater than 127 | Transmit channel number of 32-bit descriptor words to fetch. The user must make sure to set the maximum word count that can pass through the channel for any allowed descriptor type. The register field is programmed if tx_fetch_size’s valid bit is set. |
| tx_credit_count | u8 | Cannot be greater than 7 | Transmit channel transfer request credit count. Specifies how many credits for complete TRs are available. This field is only used when configuring a transmit channel of external type. The register field is programmed if tx_credit_count’s valid bit is set. |
| txcq_qnum | u16 | Valid, assigned ring | Transmit channel completion queue. The specified completion queue must be assigned to the host, or a subordinate of the host, requesting configuration of the transmit channel. The register field is programmed if txcq_qnum’s valid bit is set. |
| tx_priority | u8 | Transmit channel transmit priority | The register field is programmed if tx_priority’s valid bit is set. |
| tx_qos | u8 | Transmit channel QoS value | Transmit channel transmit qos value. The register field is programmed if tx_qos’s valid bit is set. |
| tx_orderid | u8 | Transmit channel bus order ID | Transmit channel bus order id. The register field is programmed if tx_orderid’s valid bit is set. |
| fdepth | u16 | Check the UDMAP section of the TRM for restrictions regarding this parameter. Reset value is 0x400. | Channel FIFO depth configuration. Sets the number of Tx FIFO bytes which are allowed to be stored for the channel. The TISCI message is rejected if a non-zero, valid, value is provided during external channel configuration. The register field is programmed if fdepth’s valid bit is set. |
| tx_sched_priority | u8 |
|
Tx scheduling priority configuration. The register field is programmed if tx_sched_priority’s valid bit is set. |
| tx_burst_size | u8 |
|
UDMAP transmit channel burst size configuration. The register is programmed if the corresponding valid bit is set. This field is not supported on some SoCs. On SoCs that do not support this field the input is quietly ignored even if the valid bit is set. |
| tx_tdtype | u8 |
|
UDMAP transmit channel teardown type configuration programmed into the tx_tdtype field of the TCHAN_TCFG register. Can be set to 0 for immediate teardown or 1 to wait for remote peer to send completion message for teardown. Only valid if corresponding valid bit is set. This field is not supported on some SoCs. On SoCs that do not support this field the input is quietly ignored even if the valid bit is set. |
UDMAP Transmit Channel Configuration Valid Parameters¶
The following table describes the valid bit mappings for the UDMAP transmit channel configure message optional parameters:
| valid_params Bit | Corresponding tisci_msg_rm_udmap_tx_ch_cfg_req Optional Parameter |
|---|---|
| 0 | tx_pause_on_err |
| 1 | tx_atype |
| 2 | tx_chan_type |
| 3 | tx_fetch_size |
| 4 | txcq_qnum |
| 5 | tx_priority |
| 6 | tx_qos |
| 7 | tx_orderid |
| 8 | tx_sched_priority |
| 9 | tx_filt_einfo |
| 10 | tx_filt_pswords |
| 11 | tx_supr_tdpkt |
| 12 | tx_credit_count |
| 13 | fdepth |
| 14 | tx_burst_size |
UDMAP Transmit Channel Configure Response¶
The udmap tx channel cfg response message returns the result status of the processed udmap tx channel cfg message.
UDMAP Transmit Channel Configure Response Message Parameters¶
| Parameter | Type | Valid Values | Description |
|---|---|---|---|
| hdr | Generic TISCI message header (8 bytes) | Valid Host IDs | Generic TISCI message header. Contains the message ID, host ID, sequence number, and any return flags |
TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG - UDMAP Transmit Channel Get Configuration¶
UDMAP Transmit Channel Get Configuration Request¶
The udmap_tx_ch get cfg TISCI message API is used to retrieve the non-real-time registers field settings, or the hardware reset register settings, for a UDMAP transmit channel. The host, or a supervisor of the host, who owns the transmit channel must be the requesting host. The register field values are returned in the udmap_tx_ch get cfg response message.
The udmap_tx_ch_get cfg API can be used to retrieve UDMAP transmit channel configurations within any Navigator Subsystem on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG (0x1206U)
RM TISCI message to get the register cfg for a Navigator Subsystem UDMAP transmit channel
UDMAP Transmit Channel Get Configuration Message Parameters¶
struct tisci_msg_rm_udmap_tx_ch_get_cfg_req
Get Navigator Subsystem UDMAP transmit channel’s non-real-time register configuration
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| nav_id | u16 | SoC device ID of Navigator Subsystem in which the UDMAP transmit channel is located |
| index | u16 | UDMAP transmit channel index. |
| get_reset_cfg | u8 | Switch defining which UDMAP tx ch configuration is returned: @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_REG - Return non-real-time register configuration @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_RESET - Return non-real-time register hardware reset value configuration |
Gets the configuration of the non-real-time register fields of a UDMAP transmit channel. The host, or a supervisor of the host, who owns the channel must be the requesting host. The values of the non-real-time registers are returned in @ref tisci_msg_rm_udmap_tx_ch_get_cfg_resp. The reset_cfg parameter is used to request either the existing non-real-time register values or the hardware reset values for the UDMAP transmit channel’s register fields.
UDMAP Transmit Channel Get Configuration Response¶
The udmap_tx_ch get cfg response TISCI message contains the UDMAP transmit channel’s non-real-time register field values.
UDMAP Transmit Channel Get Configuration Response Message Parameters¶
struct tisci_msg_rm_udmap_tx_ch_get_cfg_resp
UDMAP transmit channel get configuration response message
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| tx_pause_on_err | u8 | UDMAP transmit channel pause on error configuration |
| tx_filt_einfo | u8 | UDMAP transmit channel extended packet information passing configuration |
| tx_filt_pswords | u8 | UDMAP transmit channel protocol specific word passing configuration |
| tx_atype | u8 | UDMAP transmit channel non Ring Accelerator access pointer interpretation |
| tx_chan_type | u8 | UDMAP transmit channel functional channel type and work passing mechanism |
| tx_supr_tdpkt | u8 | UDMAP transmit channel teardown packet generation suppression |
| tx_fetch_size | u16 | UDMAP transmit channel number of 32-bit descriptor words to fetch |
| tx_credit_count | u8 | UDMAP transmit channel transfer request credit count |
| txcq_qnum | u16 | UDMAP transmit channel completion queue |
| tx_priority | u8 | UDMAP transmit channel transmit priority |
| tx_qos | u8 | UDMAP transmit channel transmit qos value |
| tx_orderid | u8 | UDMAP transmit channel bus order id |
| fdepth | u16 | UDMAP transmit channel FIFO depth |
| tx_sched_priority | u8 | UDMAP transmit channel tx scheduling priority |
| tx_burst_size | u8 | UDMAP transmit channel burst size. This field is not supported on some SoCs. Zeroes are returned on SoCs that do not support this field. |
| tx_tdtype | u8 | UDMAP transmit channel teardown type configuration to be programmed into the tdtype field of the TCHAN_TCFG register. |
Response received by host processor after RM has handled @ref tisci_msg_rm_udmap_tx_ch_get_cfg_req. The response contains the transmit channel’s non-real-time register values.
TISCI_MSG_RM_UDMAP_RX_CH_CFG - UDMAP Receive Channel Configure¶
UDMAP Receive Channel Configure¶
The UDMAP rx channel cfg TISCI message API is used to configure SoC Navigator Subsystem UDMAP receive channels. The API only allows configuration of a receive channel by passing the rx channel index and the Navigator SoC device ID in which the channel is located. Only the non-real-time receive channel registers are programmed as part of the channel configuration. The host is granted access to the receive channel real-time registers via the SoC channelized firewalls based on the RM board configuration. The OS can access the channel real-time registers directly after receive channel configuration is complete.
The UDMAP global invalid receive flow event and per receive channel output event (OES) and error output event (EOES) registers are not programmed as part of the UDMAP rx channel cfg API. They’re programmed internally via the RM IRQ Set message.
The UDMAP rx channel cfg API can be used to configure receive channels within any Navigator Subsystem UDMAP on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_RX_CH_CFG (0x1215U)
RM TISCI message to configure a Navigator Subsystem UDMAP receive channel
UDMAP Receive Channel Configure Message Parameters¶
| Parameter | Type | Valid Values | Description |
|---|---|---|---|
| hdr | Generic TISCI message header (8 bytes) | Valid Host IDs | Generic TISCI message header. Contains the message ID, host ID, sequence number, and any flags |
| valid_params | u32 | UDMAP Receive Channel Configuration Valid Parameters | Bitfield defining validity of UDMAP receive channel configuration parameters. The channel configuration fields are not valid, and will not be used, if their corresponding valid bit is zero. |
| nav_id | u16 | Valid Navigator Subsystem UDMAP Device IDs | The SoC-specific Device ID of the Navigator subsystem UDMAP in which the receive channel is located. |
| index | u16 | Valid Navigator Subsystem Receive Channel Indices | Specifies the requested receive channel index for configuration |
| rx_fetch_size | u16 | Cannot be greater than 127 | Receive channel number of 32-bit descriptor words to fetch. The user must make sure to set the maximum word count that can pass through the channel for any allowed descriptor type. The register field is programmed if rx_fetch_size’s valid bit is set. |
| rxcq_qnum | u16 | Valid, assigned ring | Receive channel completion queue. The specified completion queue must be assigned to the host, or a subordinate of the host, requesting configuration of the receive channel. The register field is programmed if rxcq_qnum’s valid bit is set. |
| rx_priority | u8 | Receive channel receive priority | The register field is programmed if rx_priority’s valid bit is set. |
| rx_qos | u8 | Receive channel QoS value | Receive channel receive qos value. The register field is programmed if rx_qos’s valid bit is set. |
| rx_orderid | u8 | Receive channel bus order ID | Receive channel bus order id. The register field is programmed if rx_orderid’s valid bit is set. |
| rx_sched_priority | u8 |
|
Rx scheduling priority configuration. The register field is programmed if rx_sched_priority’s valid bit is set. |
| flowid_start | u16 | Common Navigator Subsystem Receive Flow Indices | Specifies the starting index for flow IDs the receive channel is to make use of beyond the default, statically mapped flow. The additional flows must be assigned to the host, or a subordinate of the host, requesting configuration of the receive channel. The register field is programmed if flowid_start and flowid_cnt valid bits are set. |
| flowid_cnt | u16 | flowid_cnt such that flowid_start + flowid_cnt cannot exceed number of receive flows in receive channel’s Navigator Subsystem | Receive channel rx flow ID count starting at flowid_start index. This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for the channel. The additional flows must be assigned to the host, or a subordinate of the host, requesting configuration of the receive channel. The register field is programmed if flowid_start and flowid_cnt valid bits are set. |
| rx_pause_on_err | u8 |
|
Receive channel pause on error configuration. The register field is programmed if rx_pause_on_err’s valid bit is set. |
| rx_atype | u8 |
|
Receive channel non Ring Accelerator access pointer interpretation configuration. The register field is programmed if rx_atype’s valid bit is set. |
| rx_chan_type | u8 | (2) - Packet transfers using pass by reference rings, (3) - Packet transfers using pass by reference rings with single buffer packet mode enabled, (10) - 3rd party DMA transfers using pass by reference rings, (11) - 3rd party DMA transfers using pass by value rings, (12) - 3rd party block copy DMA transfers using pass by reference rings, (13) - 3rd party block copy DMA transfers using pass by value rings. | Receive channel functional channel type and work passing mechanism. The register field is programmed if rx_chan_type’s valid bit is set. |
| rx_ignore_short | u8 |
|
Receive channel short packet treatment. The register field is programmed if rx_ignore_short’s valid bit is set. |
| rx_ignore_long | u8 |
|
Receive channel long packet treatment. The register field is programmed if rx_ignore_long’s valid bit is set. |
| rx_burst_size | u8 |
|
UDMAP receive channel burst size configuration. The register is programmed if the corresponding valid bit is set. This field is not supported on some SoCs. On SoCs that do not support this field the input is quietly ignored even if the valid bit is set. |
UDMAP Receive Channel Configuration Valid Parameters¶
The following table describes the valid bit mappings for the UDMAP receive channel configure message optional parameters:
| valid_params Bit | Corresponding tisci_msg_rm_udmap_rx_ch_cfg_req Optional Parameter |
|---|---|
| 0 | rx_pause_on_err |
| 1 | rx_atype |
| 2 | rx_chan_type |
| 3 | rx_fetch_size |
| 4 | rxcq_qnum |
| 5 | rx_priority |
| 6 | rx_qos |
| 7 | rx_orderid |
| 8 | rx_sched_priority |
| 9 | flowid_start |
| 10 | flowid_cnt |
| 11 | rx_ignore_short |
| 12 | rx_ignore_long |
| 14 | rx_burst_size |
UDMAP Receive Channel Configure Response¶
The udmap rx channel cfg response message returns the result status of the processed udmap rx channel cfg message.
UDMAP Receive Channel Configure Response Message Parameters¶
| Parameter | Type | Valid Values | Description |
|---|---|---|---|
| hdr | Generic TISCI message header (8 bytes) | Valid Host IDs | Generic TISCI message header. Contains the message ID, host ID, sequence number, and any return flags |
TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG - UDMAP Receive Channel Get Configuration¶
UDMAP Receive Channel Get Configuration Request¶
The udmap_rx_ch get cfg TISCI message API is used to retrieve the non-real-time registers field settings, or the hardware reset register settings, for a UDMAP receive channel. The host, or a supervisor of the host, who owns the receive channel must be the requesting host. The register field values are returned in the udmap_rx_ch get cfg response message.
The udmap_rx_ch_get cfg API can be used to retrieve UDMAP receive channel configurations within any Navigator Subsystem on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG (0x1216U)
RM TISCI message to get the register cfg for a Navigator Subsystem UDMAP receive channel
UDMAP Receive Channel Get Configuration Message Parameters¶
struct tisci_msg_rm_udmap_rx_ch_get_cfg_req
Get Navigator Subsystem UDMAP receive channel’s non-real-time register configuration
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| nav_id | u16 | SoC device ID of Navigator Subsystem in which the UDMAP receive channel is located |
| index | u16 | UDMAP receive channel index. |
| get_reset_cfg | u8 | Switch defining which UDMAP rx ch configuration is returned: @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_REG - Return non-real-time register configuration @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_RESET - Return non-real-time register hardware reset value configuration |
Gets the configuration of the non-real-time register fields of a UDMAP receive channel. The host, or a supervisor of the host, who owns the channel must be the requesting host. The values of the non-real-time registers are returned in @ref tisci_msg_rm_udmap_rx_ch_get_cfg_resp. The reset_cfg parameter is used to request either the existing non-real-time register values or the hardware reset values for the UDMAP receive channel’s register fields.
UDMAP Receive Channel Get Configuration Response¶
The udmap_rx_ch get cfg response TISCI message contains the UDMAP receive channel’s non-real-time register field values.
UDMAP Receive Channel Get Configuration Response Message Parameters¶
struct tisci_msg_rm_udmap_rx_ch_get_cfg_resp
UDMAP receive channel get configuration response message
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| rx_fetch_size | u16 | UDMAP receive channel number of 32-bit descriptor words to fetch |
| rxcq_qnum | u16 | UDMAP receive channel completion queue |
| rx_priority | u8 | UDMAP receive channel receive priority |
| rx_qos | u8 | UDMAP receive channel receive qos value |
| rx_orderid | u8 | UDMAP receive channel bus order id |
| rx_sched_priority | u8 | UDMAP receive channel rx scheduling priority |
| flowid_start | u16 | UDMAP receive channel additional flows starting index |
| flowid_cnt | u16 | UDMAP receive channel additional flows count |
| rx_pause_on_err | u8 | UDMAP receive channel pause on error |
| rx_atype | u8 | UDMAP receive channel non Ring Accelerator access pointer interpretation |
| rx_chan_type | u8 | UDMAP receive channel functional channel type and work passing mechanism |
| rx_ignore_short | u8 | UDMAP receive channel short packet treatment |
| rx_ignore_long | u8 | UDMAP receive channel long packet treatment |
| rx_burst_size | u8 | UDMAP receive channel burst size. This field is not supported on some SoCs. Zeroes are returned on SoCs that do not support this field. |
Response received by host processor after RM has handled @ref tisci_msg_rm_udmap_rx_ch_get_cfg_req. The response contains the receive channel’s non-real-time register values.
UDMAP Receive Flow Configuration¶
UDMAP Receive Flow Configuration Request¶
Warning
This API is deprecated and will be removed in 2018.09.
The UDMAP rx flow cfg TISCI message API is used to configure an allocated SoC Navigator Subsystem UDMAP receive flow’s non-optional registers. The receive flow must be used by the specified receive channel and the host requesting the receive flow configuration must be the host, or the supervisor of the host, that owns the receive channel in order for the flow to be configured. It’s the user’s responsbility to make sure the receive channel is disabled when changing the receive flow configuration. Otherwise, unknown operation may occur.
The UDMAP global invalid receive flow event register is not programmed as part of the UDMAP rx flow cfg API. It is programmed internally via the RM IRQ Set message.
The UDMAP rx flow cfg API can be used to configure receive flows within any Navigator Subsystem UDMAP on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
UDMAP Receive Flow Configuration Message Parameters¶
| Parameter | Type | Valid Values | Description |
|---|---|---|---|
| hdr | Generic TISCI message header (8 bytes) | Valid Host IDs | Generic TISCI message header. Contains the message ID, host ID, sequence number, and any flags |
| nav_id | u32 | Valid Navigator Subsystem UDMAP Device IDs | The SoC-specific Device ID of the Navigator subsystem UDMAP in which the receie flow is located. |
| flow_index | u32 | Valid Navigator Subsystem Receive Flow Indices | Specifies the receive flow index for non-optional configuration. |
| rx_ch_index | u32 | Valid Navigator Subsystem Receive Channel Indices | Specifies the receive channel index using the receive flow to be configured. The receive channel must be using the receive flow either through the static mapping of receive channels to receive flows or through the receive channel’s flow range specification. |
| rx_einfo_present | u8 |
|
Receive flow extended packet info present |
| rx_psinfo_present | u8 |
|
Receive flow PS words present |
| rx_error_handling | u8 |
|
Receive flow error handling |
| rx_desc_type | u8 |
|
Receive flow descriptor type |
| rx_sop_offset | u16 | 0 - 255 bytes | Receive flow start of packet offset. See the UDMAP section of the TRM for more information on this setting. |
| rx_dest_qnum | u16 | Receive flow destination queue configuration | The specified destination queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
| rx_ps_location | u8 |
|
Receive flow PS words location |
| rx_src_tag_hi | u8 | See the UDMAP section of the TRM for more information on this setting | Receive flow source tag high byte constant |
| rx_src_tag_lo | u8 | See the UDMAP section of the TRM for more information on this setting | Receive flow source tag low byte constant |
| rx_dest_tag_hi | u8 | See the UDMAP section of the TRM for more information on this setting | Receive flow destination tag high byte constant |
| rx_dest_tag_lo | u8 | See the UDMAP section of the TRM for more information on this setting | Receive flow destination tag low byte constant |
| rx_src_tag_hi_sel | u8 |
|
Receive flow source tag high byte selector |
| rx_src_tag_lo_sel | u8 |
|
Receive flow source tag low byte selector |
| rx_dest_tag_hi_sel | u8 |
|
Receive flow destination tag high byte selector |
| rx_dest_tag_lo_sel | u8 |
|
Receive flow destination tag low byte selector |
| rx_size_thresh_en | u8 | Receive flow packet size based free buffer queue enable, cannot be greater than 7 | See the UDMAP section of the TRM for more information on this setting. Configuration of the optional size thresholds when this configuration is enabled is done by sending the Receive Flow Optional Config Message to System Firmware for the receive flow allocated by this request. |
| rx_fdq0_sz0_qnum | u16 | Receive flow free descriptor queue 0 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
| rx_fdq1_qnum | u16 | Receive flow free descriptor queue 1 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
| rx_fdq2_qnum | u16 | Receive flow free descriptor queue 2 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
| rx_fdq3_qnum | u16 | Receive flow free descriptor queue 3 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
UDMAP Receive Flow Optional Config¶
UDMAP Receive Flow Optional Config Request¶
Warning
This API is deprecated and will be removed in 2018.09.
The UDMAP rx flow optional cfg TISCI message API is used to configure the optional registers for an allocated flow. The API allows programming of an allocated receive flow’s optional size threshold register fields if the flow’s rx_size_thresh_en field was set when the receive flow non-optional registers were configured using the UDMAP rx flow cfg TISCI message. The receive flow must be used by the specified receive channel and the host requesting the receive flow configuration must be the host, or the supervisor of the host, that owns the receive channel in order for the flows optional registers to be configured. It’s the user’s responsbility to make sure the receive channel is disabled when changing the receive flow optionawl configuration. Otherwise, unknown operation may occur.
The UDMAP rx flow optional cfg API can be used to configure optional fields of receive flow within any Navigator Subsystem UDMAP on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
UDMAP Receive Flow Optional Config Message Parameters¶
| Parameter | Type | Valid Values | Description |
|---|---|---|---|
| hdr | Generic TISCI message header (8 bytes) | Valid Host IDs | Generic TISCI message header. Contains the message ID, host ID, sequence number, and any flags |
| nav_id | u32 | Valid Navigator Subsystem UDMAP Device IDs | The SoC-specific Device ID of the Navigator subsystem UDMAP in which the receie flow is located. |
| flow_index | u32 | Valid Navigator Subsystem Receive Flow Indices | Specifies the receive flow index for optional configuration. |
| rx_ch_index | u32 | Valid Navigator Subsystem Receive Channel Indices | Specifies the receive channel index using the receive flow to be configured. The receive channel must be using the receive flow either through the static mapping of receive channels to receive flows or through the receive channel’s flow range specification. |
| rx_size_thresh0 | u16 | Receive flow packet size threshold 0 | See the UDMAP section of the TRM for more information on this setting |
| rx_size_thresh1 | u16 | Receive flow packet size threshold 1 | See the UDMAP section of the TRM for more information on this setting. |
| rx_size_thresh2 | u16 | Receive flow packet size threshold 2 | See the UDMAP section of the TRM for more information on this setting. |
| rx_fdq0_sz1_qnum | u16 | Receive flow free descriptor queue for size threshold 1 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, who owns the receive flow index and who is making the optional configuration request. |
| rx_fdq0_sz2_qnum | u16 | Receive flow free descriptor queue for size threshold 2 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, who owns the receive flow index and who is making the optional configuration request. |
| rx_fdq0_sz3_qnum | u16 | Receive flow free descriptor queue for size threshold 3 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, who owns the receive flow index and who is making the optional configuration request. |
TISCI_MSG_RM_UDMAP_FLOW_CFG - UDMAP Receive Flow Configure¶
UDMAP Receive Flow Configure Request¶
The UDMAP flow cfg TISCI message API is used to configure a SoC Navigator Subsystem UDMAP receive flow’s standard, non-size threshold registers. The flow index must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment range list.
It’s the user’s responsibility to make sure any receive channels using the flow are disabled when changing the receive flow configuration. Otherwise, unknown operation may occur.
The UDMAP global invalid receive flow event register is not programmed as part of the UDMAP flow cfg API. It is programmed internally via the RM IRQ Set message.
The UDMAP flow cfg API can be used to configure receive flows within any Navigator Subsystem UDMAP on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_FLOW_CFG (0x1230U)
RM TISCI message to configure a Navigator Subsystem UDMAP receive flow
UDMAP Receive Flow Configure Message Parameters¶
| Parameter | Type | Valid Values | Description |
|---|---|---|---|
| hdr | Generic TISCI message header | Valid Host IDs | Generic TISCI message header. Contains the message ID, host ID, sequence number, and any flags |
| valid_params | u32 | UDMAP Receive Flow Configure Valid Parameters | Bitfield defining validity of UDMAP receive channel configuration parameters. The channel configuration fields are not valid, and will not used, if their corresponding valid bit is zero. |
| nav_id | u16 | Valid Navigator Subsystem UDMAP Device IDs | The SoC-specific Device ID of the Navigator subsystem UDMAP in which the receive flow is located. |
| flow_index | u16 | Valid Receive Flow Indices | Specifies the receive flow index |
| rx_einfo_present | u8 |
|
Receive flow extended packet info present. The register field is programmed if rx_einfo_present’s valid bit is set. |
| rx_psinfo_present | u8 |
|
Receive flow PS words present. The register field is programmed if rx_psinfo_present’s valid bit is set. |
| rx_error_handling | u8 |
|
Receive flow error handling. The register field is programmed if rx_error_handling’s valid bit is set. |
| rx_desc_type | u8 |
|
Receive flow descriptor type. The register field is programmed if rx_desc_types’s valid bit is set. |
| rx_sop_offset | u16 | 0 - 255 bytes | Receive flow start of packet offset. See the UDMAP section of the TRM for more information on this setting. The register field is programmed rx_sop_offset’s valid bit is set. |
| rx_dest_qnum | u16 | Receive flow destination queue configuration | The specified destination queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. The register field is programmed rx_dest_qnum’s valid bit is set. |
| rx_src_tag_hi | u8 | See the UDMAP section of the TRM for more information on this setting | Receive flow source tag high byte constant. The register field is programmed rx_src_tag_hi’s valid bit is set. |
| rx_src_tag_lo | u8 | See the UDMAP section of the TRM for more information on this setting | Receive flow source tag low byte constant. The register field is programmed rx_src_tag_lo’s valid bit is set. |
| rx_dest_tag_hi | u8 | See the UDMAP section of the TRM for more information on this setting | Receive flow destination tag high byte constant. The register field is programmed rx_dest_tag_hi’s valid bit is set. |
| rx_dest_tag_lo | u8 | See the UDMAP section of the TRM for more information on this setting | Receive flow destination tag low byte constant. The register field is programmed rx_dest_tag_lo’s valid bit is set. |
| rx_src_tag_hi_sel | u8 | (0) - Do not overwrite, (1) - Overwrite with value in rx_src_tag_hi, (2) - Overwrite with flow_id[7:0], (4) - Overwrite with src_tag[7:0], (5) - Overwrite with src_tag[15:8] | Receive flow source tag high byte selector. The register field is programmed if rx_src_tag_hi_sel’s valid bit is set. |
| rx_src_tag_lo_sel | u8 | (0) - Do not overwrite, (1) - Overwrite with value in rx_src_tag_lo, (2) - Overwrite with flow_id[7:0], (4) - Overwrite with src_tag[7:0], (5) - Overwrite with src_tag[15:8] | Receive flow source tag low byte selector. The register field is programmed if rx_src_tag_lo_sel’s valid bit is set. |
| rx_dest_tag_hi_sel | u8 | (0) - Do not overwrite, (1) - Overwrite with value in rx_dest_tag_hi, (2) - Overwrite with flow_id[7:0], (4) - Overwrite with src_tag[7:0], (5) - Overwrite with src_tag[15:8] | Receive flow destination tag high byte selector. The register field is programmed if rx_dest_tag_hi_sel’s valid bit is set. |
| rx_dest_tag_lo_sel | u8 | (0) - Do not overwrite, (1) - Overwrite with value in rx_dest_tag_lo, (2) - Overwrite with flow_id[7:0], (4) - Overwrite with src_tag[7:0], (5) - Overwrite with src_tag[15:8] | Receive flow destination tag low byte selector. The register field is programmed if rx_dest_tag_lo_sel’s valid bit is set. |
| rx_fdq0_sz0_qnum | u16 | Receive flow free descriptor queue 0 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
| rx_fdq1_qnum | u16 | Receive flow free descriptor queue 1 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
| rx_fdq2_qnum | u16 | Receive flow free descriptor queue 2 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
| rx_fdq3_qnum | u16 | Receive flow free descriptor queue 3 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
| rx_ps_location | u8 |
|
Receive flow PS words location. The register field is programmed if rx_ps_location’s valid bit is set. |
UDMAP Receive Flow Configure Valid Parameters¶
The following table describes the valid bit mappings for the UDMAP receive flow configure message parameters:
| valid_params Bit | Corresponding tisci_msg_rm_udmap_flow_cfg_req Parameter |
|---|---|
| 0 | rx_einfo_present |
| 1 | rx_psinfo_present |
| 2 | rx_error_handling |
| 3 | rx_desc_type |
| 4 | rx_sop_offset |
| 5 | rx_dest_qnum |
| 6 | rx_src_tag_hi |
| 7 | rx_src_tag_lo |
| 8 | rx_dest_tag_hi |
| 9 | rx_dest_tag_lo |
| 10 | rx_src_tag_hi_sel |
| 11 | rx_src_tag_lo_sel |
| 12 | rx_dest_tag_hi_sel |
| 13 | rx_dest_tag_lo_sel |
| 14 | rx_fdq0_sz0_qnum |
| 15 | rx_fdq1_sz0_qnum |
| 16 | rx_fdq2_sz0_qnum |
| 17 | rx_fdq3_sz0_qnum |
| 18 | rx_ps_location |
UDMAP Receive Flow Configure Response¶
The udmap flow cfg response message returns the result status of the processed udmap flow cfg message.
UDMAP Receive Flow Configure Response Message Parameters¶
| Parameter | Type | Valid Values | Description |
|---|---|---|---|
| hdr | Generic TISCI message header (8 bytes) | Valid Host IDs | Generic TISCI message header. Contains the message ID, host ID, sequence number, and any return flags |
TISCI_MSG_RM_UDMAP_FLOW_GET_CFG - UDMAP Receive Flow Get Configuration¶
UDMAP Receive Flow Get Configuration Request¶
The udmap_flow_get_cfg TISCI message API is used to retrieve the non-real-time registers field settings, or the hardware reset register settings, for a UDMAP receive flow. The host, or a supervisor of the host, who owns the receive flow must be the requesting host. The register field values are returned in the udmap_flow_get_cfg_response message.
The udmap_flow_get_cfg API can be used to retrieve UDMAP receive flow configurations within any Navigator Subsystem on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_FLOW_GET_CFG (0x1232U)
RM TISCI message to get the register cfg for a Navigator Subsystem UDMAP receive flow’s standard registers
UDMAP Receive Flow Get Configuration Message Parameters¶
struct tisci_msg_rm_udmap_flow_get_cfg_req
Get Navigator Subsystem UDMAP receive flow’s non-real-time register configuration
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| nav_id | u16 | SoC device ID of Navigator Subsystem in which the UDMAP receive flow is located |
| index | u16 | UDMAP receive flow index. |
| get_reset_cfg | u8 | Switch defining which UDMAP flow configuration is returned: @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_REG - Return non-real-time register configuration @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_RESET - Return non-real-time register hardware reset value configuration |
Gets the configuration of the non-real-time register fields of a UDMAP receive flow. The host, or a supervisor of the host, who owns the flow must be the requesting host. The values of the non-real-time registers are returned in @ref tisci_msg_rm_udmap_flow_get_cfg_resp. The reset_cfg parameter is used to request either the existing non-real-time register values or the hardware reset values for the UDMAP flow’s register fields.
UDMAP Receive Flow Get Configuration Response¶
The udmap_flow_get_cfg response TISCI message contains the UDMAP receive flow’s non-real-time register field values.
UDMAP Receive Flow Get Configuration Response Message Parameters¶
struct tisci_msg_rm_udmap_flow_get_cfg_resp
UDMAP receive flow get configuration response message
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| rx_einfo_present | u8 | UDMAP receive flow extended packet info present configuration |
| rx_psinfo_present | u8 | UDMAP receive flow PS words present configuration |
| rx_error_handling | u8 | UDMAP receive flow error handling configuration |
| rx_desc_type | u8 | UDMAP receive flow descriptor type |
| rx_sop_offset | u16 | UDMAP receive flow start of packet offset |
| rx_dest_qnum | u16 | UDMAP receive flow destination queue |
| rx_src_tag_hi | u8 | UDMAP receive flow source tag high byte constant |
| rx_src_tag_lo | u8 | UDMAP receive flow source tag low byte constant |
| rx_dest_tag_hi | u8 | UDMAP receive flow destination tag high byte constant |
| rx_dest_tag_lo | u8 | UDMAP receive flow destination tag low byte constant |
| rx_src_tag_hi_sel | u8 | UDMAP receive flow source tag high byte selector |
| rx_src_tag_lo_sel | u8 | UDMAP receive flow source tag low byte selector |
| rx_dest_tag_hi_sel | u8 | UDMAP receive flow destination tag high byte selector |
| rx_dest_tag_lo_sel | u8 | UDMAP receive flow destination tag low byte selector |
| rx_fdq0_sz0_qnum | u16 | UDMAP receive flow free descriptor queue 0 |
| rx_fdq1_qnum | u16 | UDMAP receive flow free descriptor queue 1 |
| rx_fdq2_qnum | u16 | UDMAP receive flow free descriptor queue 2 |
| rx_fdq3_qnum | u16 | UDMAP receive flow free descriptor queue 3 |
| rx_ps_location | u8 | UDMAP receive flow PS words location |
Response received by host processor after RM has handled @ref tisci_msg_rm_udmap_flow_get_cfg_req. The response contains the receive flow’s register values.
TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG - UDMAP Receive Flow Size Threshold Configure¶
UDMAP Receive Flow Size Threshold Configure Request¶
The UDMAP flow size threshold cfg TISCI message API is used to configure the size-based free descriptor queue routing registers for flow. The flow index must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment range list.
It’s the user’s responsibility to make sure any receive channels using the flow are disabled when changing the receive flow configuration. Otherwise, unknown operation may occur.
The UDMAP flow size threshold cfg API can be used to configure receive flows within any Navigator Subsystem UDMAP on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG (0x1231U)
RM TISCI message to configure a Navigator Subsystem UDMAP receive flow’s optional, size based free descriptor queue registers
UDMAP Receive Flow Size Threshold Configure Message Parameters¶
| Parameter | Type | Valid Values | Description | |
|---|---|---|---|---|
| hdr | Generic TISCI message header | Valid Host IDs | Generic TISCI message header. Contains the message ID, host ID, sequence number, and any flags | |
| valid_params | u32 |
|
||
| nav_id | u16 |
|
||
| flow_index | u16 | Valid Receive Flow Indices | Specifies the receive flow index. | |
| rx_size_thresh0 | u16 | Receive flow packet size threshold 0 | See the UDMAP section of the TRM for more information on this setting. The value must be provided in 32-byte units due to a 5-bit left shift performed by the HW prior to comparison to packet size. The register field is programmed if rx_size_thresh0’s valid bit is set. | |
| rx_size_thresh1 | u16 | Receive flow packet size threshold 1 | See the UDMAP section of the TRM for more information on this setting. The value must be provided in 32-byte units due to a 5-bit left shift performed by the HW prior to comparison to packet size. The register field is programmed if rx_size_thresh1’s valid bit is set. | |
| rx_size_thresh2 | u16 | Receive flow packet size threshold 2 | See the UDMAP section of the TRM for more information on this setting. The value must be provided in 32-byte unites due to a left performed by the HW prior to comparison to packet size. The register field is programmed if rx_size_thresh2’s valid bit is set. | |
| rx_fdq0_sz1_qnum | u16 | Receive flow free descriptor queue for size threshold 1 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, who owns the receive flow index and who is making the optional configuration request. The register field is programmed if rx_fdq0_sz1_qnum’s valid bit is set. | |
| rx_fdq0_sz2_qnum | u16 | Receive flow free descriptor queue for size threshold 2 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, who owns the receive flow index and who is making the optional configuration request. The register field is programmed if rx_fdq0_sz2_qnum’s valid bit is set. | |
| rx_fdq0_sz3_qnum | u16 | Receive flow free descriptor queue for size threshold 3 | See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, who owns the receive flow index and who is making the optional configuration request. The register field is programmed if rx_fdq0_sz3_qnum’s valid bit is set. | |
| rx_size_thresh_en | u8 | Flow packet size based free queue routing enable, cannot be greater than 7 | See the UDMAP section of the TRM for more information on this setting. The register field is programmed if rx_size_thresh’s valid bit is set. | |
UDMAP Receive Flow Size Threshold Configure Valid Parameters¶
The following table describes the valid bit mappings for the UDMAP receive flow size threshold configure message parameters:
| valid_params Bit | Corresponding tisci_msg_rm_udmap_flow_size_thresh_cfg_req Parameter |
|---|---|
| 0 | rx_size_thresh0 |
| 1 | rx_size_thresh1 |
| 2 | rx_size_thresh2 |
| 3 | rx_fdq0_sz1_qnum |
| 4 | rx_fdq0_sz2_qnum |
| 5 | rx_fdq0_sz3_qnum |
| 6 | rx_size_thresh_en |
UDMAP Receive Flow Size Threshold Configure Response¶
The udmap flow size threshold cfg response message returns the result status of the processed udmap flow size threshold cfg message.
UDMAP Receive Flow Size Threshold Configure Response Message Parameters¶
| Parameter | Type | Valid Values | Description |
|---|---|---|---|
| hdr | Generic TISCI message header (8 bytes) | Valid Host IDs | Generic TISCI message header. Contains the message ID, host ID, sequence number, and any return flags |
TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG - UDMAP Receive Flow Size Threshold Get Configuration¶
UDMAP Receive Flow Size Threshold Routing Get Configuration Request¶
The udmap_flow_size_thresh_get_cfg TISCI message API is used to retrieve the non-real-time registers field settings for a UDMAP receive flow’s size threshold routing registers, or the hardware reset settings. The host, or a supervisor of the host, who owns the receive flow must be the requesting host. The register field values are returned in the udmap_flow_size_thresh_get_cfg_response message.
The udmap_flow_size_thresh_get_cfg API can be used to retrieve UDMAP receive flow configurations within any Navigator Subsystem on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG (0x1233U)
RM TISCI message to get the register cfg for a Navigator Subsystem UDMAP receive flow’s size based free descriptor queue registers
UDMAP Receive Flow Size Threshold Routing Get Configuration Message Parameters¶
struct tisci_msg_rm_udmap_flow_size_thresh_get_cfg_req
Get Navigator Subsystem UDMAP receive flow’s non-real-time size threshold based queue routing register configuration
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| nav_id | u16 | SoC device ID of Navigator Subsystem in which the UDMAP receive flow is located |
| index | u16 | UDMAP receive flow index. |
| get_reset_cfg | u8 | Switch defining which UDMAP flow configuration is returned: @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_REG - Return non-real-time register configuration @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_RESET - Return non-real-time register hardware reset value configuration |
Gets the configuration of the non-real-time register fields of a UDMAP receive flow’s size threshold routing registers. The host, or a supervisor of the host, who owns the flow must be the requesting host. The values of the non-real-time registers are returned in @ref tisci_msg_rm_udmap_flow_size_thresh_get_cfg_resp. The reset_cfg parameter is used to request either the existing non-real-time register values or the hardware reset values for the UDMAP flow’s register fields.
UDMAP Receive Flow Size Threshold Routing Get Configuration Response¶
The udmap_flow_size_thresh_get_cfg response TISCI message contains the UDMAP receive flow’s non-real-time size threshold routing register field values.
UDMAP Receive Flow Size Threshold Routing Get Configuration Response Message Parameters¶
struct tisci_msg_rm_udmap_flow_size_thresh_get_cfg_resp
UDMAP receive flow get size threshold configuration response message
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| rx_size_thresh0 | u16 | UDMAP receive flow packet size threshold 0 |
| rx_size_thresh1 | u16 | UDMAP receive flow packet size threshold 1 |
| rx_size_thresh2 | u16 | UDMAP receive flow packet size threshold 2 |
| rx_fdq0_sz1_qnum | u16 | UDMAP receive flow free descriptor queue for size threshold 1 |
| rx_fdq0_sz2_qnum | u16 | UDMAP receive flow free descriptor queue for size threshold 2 |
| rx_fdq0_sz3_qnum | u16 | UDMAP receive flow free descriptor queue for size threshold 3 |
| rx_size_thresh_en | u8 | UDMAP receive flow packet size based free buffer queue enable |
Response received by host processor after RM has handled @ref tisci_msg_rm_udmap_flow_size_thresh_get_cfg_req. The response contains the receive flow’s non-real-time size threshold routing register values.
TISCI_MSG_RM_UDMAP_GCFG_CFG - UDMAP Global Configuration Configure¶
UDMAP Global Configuration Configure Request¶
The udmap_gcfg_cfg TISCI message API is used to configure non-real-time registers in the UDMAP subsystem’s global configuration region. The host, or a supervisor of the host, who owns the global configuration region must be the requesting host. The API allows configuration of the global configuration region by passing the Navigator SoC device ID of the UDMAP subsystem in which the region is located.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_GCFG_CFG (0x1240U)
RM TISCI message to configure a Navigator Subsystem UDMAP global configuration
UDMAP Global Configuration Configure Message Parameters¶
struct tisci_msg_rm_udmap_gcfg_cfg_req
Configures a Navigator Subsystem UDMAP global configuration region. Configures the non-real-time registers of a Navigator Subsystem UDMAP global configuration region. The GCFG region being programmed must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment array. Individual fields for registers specified as valid are not checked for correctness. It is the application’s responsibility to verify if the register fields are being set according to the device specification.
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| valid_params | u32 | Bitfield defining validity of global configuration parameters. The configuration fields are not valid, and will not be used for global configuration, if their corresponding valid bit is zero. Valid bit usage: 0 - Valid bit for @ref tisci_msg_rm_udmap_gcfg_cfg_req::perf_ctrl 1 - Valid bit for @ref tisci_msg_rm_udmap_gcfg_cfg_req::emu_ctrl 2 - Valid bit for @ref tisci_msg_rm_udmap_gcfg_cfg_req::psil_to 3 - Valid bit for @ref tisci_msg_rm_udmap_gcfg_cfg_req::rflowfwstat |
| nav_id | u16 | SoC device ID of Navigator Subsystem where global configuration is located |
| perf_ctrl | u32 | Configures the performance control register. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_GCFG_PERF_CTRL_VALID is set in @ref tisci_msg_rm_udmap_gcfg_cfg_req::valid_params. |
| emu_ctrl | u32 | Configures the emulation control register. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_GCFG_EMU_CTRL_VALID is set in @ref tisci_msg_rm_udmap_gcfg_cfg_req::valid_params. |
| psil_to | u32 | Configures the PSI-L proxy timeout register. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_GCFG_PSIL_TO_VALID is set in @ref tisci_msg_rm_udmap_gcfg_cfg_req::valid_params. |
| rflowfwstat | u32 | Writes the rx flow ID firewall status register. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_GCFG_RFLOWFWSTAT_VALID is set in @ref tisci_msg_rm_udmap_gcfg_cfg_req::valid_params. |
UDMAP Global Configuration Configure Valid Parameters¶
The following table describes the valid bit mappings for the UDMAP global configuration configure parameters:
| valid_params Bit | Corresponding tisci_msg_rm_udmap_gcfg_cfg_req Parameter |
|---|---|
| 0 | perf_ctrl_timeout_cnt |
| 1 | emu_ctrl_soft |
| 2 | emu_ctrl_free |
| 3 | psil_to_tout |
| 4 | psil_to_tout_cnt |
| 5 | utc_chan_start |
| 6 | rflowfwstat_pend |
UDMAP Global Configuration Configure Response¶
The udmap_gcfg_cfg_response message returns the result status of the processed udmap_gcfg_cfg message.
UDMAP Global Configuration Configure Response Message Parameters¶
struct tisci_msg_rm_udmap_gcfg_cfg_resp
Response to configuring UDMAP global configuration.
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
TISCI_MSG_RM_UDMAP_GCFG_GET_CFG - UDMAP Global Configuration Get Configuration¶
UDMAP Global Configuration Get Configuration Request¶
The udmap_gcfg_get_cfg TISCI message API is used to retrieve the non-real-time registers field settings for a UDMAP global configuration region registers, or the hardware reset settings. The host, or a supervisor of the host, who owns the global configuration region must be the requesting host. The register field values are returned in the udmap_gcfg_get_cfg_response message.
The udmap_gcfg_get_cfg API can be used to retrieve UDMAP global configuration within any Navigator Subsystem on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_GCFG_GET_CFG (0x1241U)
RM TISCI message to get the register cfg for a Navigator Subsystem UDMAP global configuration
UDMAP Global Configuration Get Configuration Message Parameters¶
struct tisci_msg_rm_udmap_gcfg_get_cfg_req
Get Navigator Subsystem UDMAP global configuration’s non-real-time register configuration. Gets the configuration of the non-real-time register fields of a UDMAP global configuration. The host, or a supervisor of the host, who owns the gcfg region must be the requesting host. The values of the non-real-time registers are returned in @ref tisci_msg_rm_udmap_gcfg_get_cfg_resp. The reset_cfg parameter is used to request either the existing non-real-time register values or the hardware reset values for the UDMAP global configuration register fields.
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| nav_id | u16 | SoC device ID of Navigator Subsystem in which the UDMAP global configuration is located |
| get_reset_cfg | u8 | Switch defining which UDMAP global configuration is returned: @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_REG - Return non-real-time register configuration @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_RESET - Return non-real-time register hardware reset value configuration |
UDMAP Global Configuration Get Configuration Response¶
The udmap_gcfg_get_cfg response TISCI message contains the UDMAP global configuration’s non-real-time register field values.
UDMAP Global Configuration Get Configuration Response Message Parameters¶
struct tisci_msg_rm_udmap_gcfg_get_cfg_resp
UDMAP global configuration get configuration response message. Response received by host processor after RM has handled @ref tisci_msg_rm_udmap_gcfg_get_cfg_req. The response contains the global configuration’s non-real-time register values.
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| revision | u32 | UDMAP module revision register. This field is read-only. Use @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_REG to retrieve this field’s value. |
| perf_ctrl | u32 | UDMAP performance control register |
| emu_ctrl | u32 | UDMAP emulation control |
| psil_to | u32 | UDMAP PSI-L proxy timeout register |
| utc_ctrl | u32 | UDMAP external UTC control register |
| cap0 | u32 | UDMAP capabilities 0 register. This field is read-only. Use @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_REG to retrieve this field’s value. |
| cap1 | u32 | UDMAP capabilities 1 register. This field is read-only. Use @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_REG to retrieve this field’s value. |
| cap2 | u32 | UDMAP capabilities 2 register. This field is read-only. Use @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_REG to retrieve this field’s value. |
| cap3 | u32 | UDMAP capabilities 3 register. This field is read-only. Use @ref TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_REG to retrieve this field’s value. |
| rflowfwstat | u32 | UDMAP rx flow ID firewall status register |