RTXCgen - Generation Utility

Binding Manual

Supported Environment
Processor Family | ARM
Tool Set | IAR Embedded Workbench IDE
Development Environment | Win 9x/2000/NT/XP

Binding Configuration Options

Building the RTXC library or any of the demonstration applications requires the compilation and/or assembly of the source code. RTXC switch options are used during the build process to modify the configuration of your RTXC application. There are two basic types of RTXC switch options; application or structural specifications and Kernel or object/services specification. These switch options are found in the RTXC options files, AOPTIONS.H, AOPTIONS.INC, KOPTIONS.H and KOPTIONS.INC. The switches are set in the generation utility program, RTXCgen, which will generate all four of these files.

1.1 USE SWI-BASED KERNEL CALLS

RTXC typically supports either call- or vector-based kernel service requests. If the VECTOR_BASED option is selected, then the SWI vector is used. Otherwise, then the kernel call processing function is called as any C-function.

NOTE: In some debug environments, there is conflict for the SWI. In these environments, it is probably best to use call-based, ie. #undef VECTOR_BASED. Otherwise, you may need to alter the debug environment in some way. See the example below:

USING VECTOR_BASED ON THE ARM940T - The ARM940T Header Card w/ Multi-ICE on the Pid7t Board is one such example. A workaround for this is to disable semihosting on the debugger. In AXD, this can be done using the Command Line Interface and entering "spp semihosting_enabled 0". However, this should not be done until AFTER the startup code has been executed and Rtxcmain has been entered.

1.2 DIRECT MANIPULATION OF CPSR

This option determines whether or not the CPSR is manipulated using immediate values of the form:

- MSR #value

or indirectly using a register having the form:

- LDR Rn, #value
- MSR Rn

The ARM documentation prohibits the immediate form. However, we have found that the immediate form executes properly on all platforms that we have tested. Also, it is slightly faster. Consult your processor's documentation to determine if the immediate form is acceptable.

1.3 GLOBAL PRESERVATION OF FIQ BIT

This option selects whether the kernel masks the FIQ bit in the CPSR to retain a global setting of the bit across modes and tasks or does not mask the bit. If this option is selected, DIRECT_CPSR_C above cannot be selected.

1.4 ARM MODE ONLY

This mode allows for slightly smaller and faster code when it is known that there is no Thumb code and hence no interworking needed. Should also be turned on if a non-Thumb processor core is being used.

RTXCgen Exception Definitions

RTXCgen for ARM will usually have ONLY ONE exception definition for the IRQ Handler. Some ARM processors include an advanced IRQ controller (sometimes known as an AIC or a VIC, for example). On these processors, RTXCgen will have one exception definition for each IRQ vector to be claimed.

Do NOT define an FIQ handler in RTXCgen. If you are to have an FIQ it must be private (ie. external to RTXC). The reason for this is that the assembly prologue and epilogue code(found in rtxcmac.inc) that RTXCgen binds to your C-handler is specific to an IRQ exception.