TI Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.msp432:MSP432E401Y

Tool Chain Version: 20.2.0

BIOS Version: bios_6_81_00_03_eng

XDCTools Version: xdctools_3_61_00_16_core

Benchmark	Cycles
Interrupt Latency	174
Hwi_restore()	13
Hwi_disable()	9
Hwi dispatcher prolog	125
Hwi dispatcher epilog	231
Hwi dispatcher	340
Hardware Interrupt to Blocked Task	542
Hardware Interrupt to Software Interrupt	351
Swi_enable()	70
Swi_disable()	18
Post Software Interrupt Again	34
Post Software Interrupt without Context Switch	90
Post Software Interrupt with Context Switch	174
Create a New Task without Context Switch	2434
Set a Task Priority without a Context Switch	154
Task_yield()	217
Post Semaphore No Waiting Task	88
Post Semaphore No Task Switch	175
Post Semaphore with Task Switch	266
Pend on Semaphore No Context Switch	78
Pend on Semaphore with Task Switch	287
Clock_getTicks()	14
POSIX Create a New Task without Context Switch	4425
POSIX Set a Task Priority without a Context Switch	204
POSIX Post Semaphore No Waiting Task	100
POSIX Post Semaphore No Task Switch	192
POSIX Post Semaphore with Task Switch	279
POSIX Pend on Semaphore No Context Switch	92
POSIX Pend on Semaphore with Task Switch	303

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –abi=eabi –float_support=fpv4spd16 -ms –opt_for_speed=2 –program_level_compile -o3”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.