75 #ifndef ti_drivers_uart_UARTMSP432E4__include 76 #define ti_drivers_uart_UARTMSP432E4__include 86 #include <ti/devices/msp432e4/inc/msp432.h> 88 #include <ti/devices/msp432e4/driverlib/gpio.h> 89 #include <ti/devices/msp432e4/driverlib/pin_map.h> 91 #include <ti/drivers/dpl/ClockP.h> 92 #include <ti/drivers/dpl/HwiP.h> 93 #include <ti/drivers/dpl/SemaphoreP.h> 105 #define UARTMSP432E4_PIN_UNASSIGNED 0xFFFFFFFF 110 #define UARTMSP432E4_FLOWCTRL_NONE 0 115 #define UARTMSP432E4_FLOWCTRL_HARDWARE 1 120 #define UARTMSP432E4_PA0_U0RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 0, GPIO_PA0_U0RX) 125 #define UARTMSP432E4_PA1_U0TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 1, GPIO_PA1_U0TX) 130 #define UARTMSP432E4_PH1_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 1, GPIO_PH1_U0CTS) 135 #define UARTMSP432E4_PM4_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTM, 4, GPIO_PM4_U0CTS) 140 #define UARTMSP432E4_PB4_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 4, GPIO_PB4_U0CTS) 145 #define UARTMSP432E4_PE6_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 6, GPIO_PE6_U0CTS) 150 #define UARTMSP432E4_PG4_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 4, GPIO_PG4_U0CTS) 155 #define UARTMSP432E4_PH0_U0RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 0, GPIO_PH0_U0RTS) 160 #define UARTMSP432E4_PB5_U0RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 5, GPIO_PB5_U0RTS) 165 #define UARTMSP432E4_PE7_U0RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 7, GPIO_PE7_U0RTS) 170 #define UARTMSP432E4_PG5_U0RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 5, GPIO_PG5_U0RTS) 176 #define UARTMSP432E4_PB0_U1RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 0, GPIO_PB0_U1RX) 181 #define UARTMSP432E4_PQ4_U1RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 4, GPIO_PQ4_U1RX) 186 #define UARTMSP432E4_PR5_U1RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 5, GPIO_PR5_U1RX) 191 #define UARTMSP432E4_PB1_U1TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 1, GPIO_PB1_U1TX) 196 #define UARTMSP432E4_PQ5_U1TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 5, GPIO_PQ5_U1TX) 201 #define UARTMSP432E4_PR6_U1TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 6, GPIO_PR6_U1TX) 206 #define UARTMSP432E4_PP3_U1CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 3, GPIO_PP3_U1CTS) 211 #define UARTMSP432E4_PN1_U1CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 1, GPIO_PN1_U1CTS) 216 #define UARTMSP432E4_PE0_U1RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 0, GPIO_PE0_U1RTS) 221 #define UARTMSP432E4_PN0_U1RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 0, GPIO_PN0_U1RTS) 226 #define UARTMSP432E4_PN7_U1RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 7, GPIO_PN7_U1RTS) 232 #define UARTMSP432E4_PA6_U2RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 6, GPIO_PA6_U2RX) 237 #define UARTMSP432E4_PD4_U2RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 4, GPIO_PD4_U2RX) 242 #define UARTMSP432E4_PA7_U2TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 7, GPIO_PA7_U2TX) 247 #define UARTMSP432E4_PD5_U2TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 5, GPIO_PD5_U2TX) 252 #define UARTMSP432E4_PN3_U2CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 3, GPIO_PN3_U2CTS) 257 #define UARTMSP432E4_PD7_U2CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 7, GPIO_PD7_U2CTS) 262 #define UARTMSP432E4_PJ3_U2CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 3, GPIO_PJ3_U2CTS) 267 #define UARTMSP432E4_PN2_U2RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 2, GPIO_PN2_U2RTS) 272 #define UARTMSP432E4_PD6_U2RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 6, GPIO_PD6_U2RTS) 277 #define UARTMSP432E4_PJ2_U2RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 2, GPIO_PJ2_U2RTS) 283 #define UARTMSP432E4_PA4_U3RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 4, GPIO_PA4_U3RX) 288 #define UARTMSP432E4_PJ0_U3RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 0, GPIO_PJ0_U3RX) 293 #define UARTMSP432E4_PA5_U3TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 5, GPIO_PA5_U3TX) 298 #define UARTMSP432E4_PJ1_U3TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 1, GPIO_PJ1_U3TX) 303 #define UARTMSP432E4_PP5_U3CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 5, GPIO_PP5_U3CTS) 308 #define UARTMSP432E4_PN5_U3CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 5, GPIO_PN5_U3CTS) 313 #define UARTMSP432E4_PJ5_U3CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 5, GPIO_PJ5_U3CTS) 318 #define UARTMSP432E4_PP4_U3RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 4, GPIO_PP4_U3RTS) 323 #define UARTMSP432E4_PN4_U3RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 4, GPIO_PN4_U3RTS) 328 #define UARTMSP432E4_PJ4_U3RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 4, GPIO_PJ4_U3RTS) 334 #define UARTMSP432E4_PA2_U4RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 2, GPIO_PA2_U4RX) 339 #define UARTMSP432E4_PK0_U4RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 0, GPIO_PK0_U4RX) 344 #define UARTMSP432E4_PR1_U4RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 1, GPIO_PR1_U4RX) 349 #define UARTMSP432E4_PA3_U4TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 3, GPIO_PA3_U4TX) 354 #define UARTMSP432E4_PK1_U4TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 1, GPIO_PK1_U4TX) 359 #define UARTMSP432E4_PR0_U4TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 0, GPIO_PR0_U4TX) 364 #define UARTMSP432E4_PK3_U4CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 3, GPIO_PK3_U4CTS) 369 #define UARTMSP432E4_PJ7_U4CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 7, GPIO_PJ7_U4CTS) 374 #define UARTMSP432E4_PN7_U4CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 7, GPIO_PN7_U4CTS) 379 #define UARTMSP432E4_PK2_U4RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 2, GPIO_PK2_U4RTS) 384 #define UARTMSP432E4_PJ6_U4RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 6, GPIO_PJ6_U4RTS) 389 #define UARTMSP432E4_PN6_U4RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 6, GPIO_PN6_U4RTS) 395 #define UARTMSP432E4_PC6_U5RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTC, 6, GPIO_PC6_U5RX) 400 #define UARTMSP432E4_PH6_U5RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 6, GPIO_PH6_U5RX) 405 #define UARTMSP432E4_PC7_U5TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTC, 7, GPIO_PC7_U5TX) 410 #define UARTMSP432E4_PH7_U5TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 7, GPIO_PH7_U5TX) 416 #define UARTMSP432E4_PP0_U6RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 0, GPIO_PP0_U6RX) 421 #define UARTMSP432E4_PP1_U6TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 1, GPIO_PP1_U6TX) 427 #define UARTMSP432E4_PC4_U7RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTC, 4, GPIO_PC4_U7RX) 432 #define UARTMSP432E4_PH6_U7RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 6, GPIO_PH6_U7RX) 437 #define UARTMSP432E4_PC5_U7TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTC, 5, GPIO_PC5_U7TX) 442 #define UARTMSP432E4_PH7_U7TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 7, GPIO_PH7_U7TX) UART_Callback readCallback
Definition: UARTMSP432E4.h:617
struct UARTMSP432E4_Object UARTMSP432E4_Object
UARTMSP432E4 Object.
void(* UARTMSP432E4_ErrorCallback)(UART_Handle handle, uint32_t error)
The definition of an optional callback function used by the UART driver to notify the application whe...
Definition: UARTMSP432E4.h:459
enum UART_Echo_ UART_Echo
UART echo settings.
uint32_t txPin
Definition: UARTMSP432E4.h:559
int(* readTaskFxn)(UART_Handle handle)
Definition: UARTMSP432E4.h:485
size_t readSize
Definition: UARTMSP432E4.h:613
RingBuf_Object ringBuffer
Definition: UARTMSP432E4.h:609
uint32_t intNum
Definition: UARTMSP432E4.h:547
UARTMSP432E4 Hardware attributes.
Definition: UARTMSP432E4.h:543
uint32_t rtsPin
Definition: UARTMSP432E4.h:563
uint32_t flowControl
Definition: UARTMSP432E4.h:551
enum UART_PAR_ UART_PAR
UART parity type settings.
HwiP_Handle hwi
Definition: UARTMSP432E4.h:627
UARTMSP432E4 Object.
Definition: UARTMSP432E4.h:573
enum UART_LEN_ UART_LEN
UART data length settings.
enum UART_Mode_ UART_Mode
UART mode settings.
uint32_t ctsPin
Definition: UARTMSP432E4.h:561
unsigned int readTimeout
Definition: UARTMSP432E4.h:616
UART Global configuration.
Definition: UART.h:695
UART_LEN dataLength
Definition: UARTMSP432E4.h:604
size_t writeCount
Definition: UARTMSP432E4.h:622
unsigned char * ringBufPtr
Definition: UARTMSP432E4.h:553
const unsigned char * writeBuf
Definition: UARTMSP432E4.h:620
UART_STOP stopBits
Definition: UARTMSP432E4.h:605
UARTMSP432E4_FxnSet readFxns
Definition: UARTMSP432E4.h:611
UART_Callback writeCallback
Definition: UARTMSP432E4.h:625
The definition of a UART function table that contains the required set of functions to control a spec...
Definition: UART.h:652
size_t writeSize
Definition: UARTMSP432E4.h:621
struct UARTMSP432E4_HWAttrs UARTMSP432E4_HWAttrs
UARTMSP432E4 Hardware attributes.
SemaphoreP_Handle writeSem
Definition: UARTMSP432E4.h:623
size_t readCount
Definition: UARTMSP432E4.h:614
UARTMSP432E4_ErrorCallback errorFxn
Definition: UARTMSP432E4.h:565
bool(* readIsrFxn)(UART_Handle handle)
Definition: UARTMSP432E4.h:484
UART_PAR parityType
Definition: UARTMSP432E4.h:606
uint32_t baseAddr
Definition: UARTMSP432E4.h:545
enum UART_STOP_ UART_STOP
UART stop bit settings.
ClockP_Handle timeoutClk
Definition: UARTMSP432E4.h:602
enum UART_ReturnMode_ UART_ReturnMode
UART return mode settings.
const UART_FxnTable UARTMSP432E4_fxnTable
SemaphoreP_Handle readSem
Definition: UARTMSP432E4.h:615
uint32_t baudRate
Definition: UARTMSP432E4.h:603
uint32_t rxPin
Definition: UARTMSP432E4.h:557
struct UARTMSP432E4_FxnSet UARTMSP432E4_FxnSet
Complement set of read functions to be used by the UART ISR and UARTMSP432E4_read(). Internal use only.
size_t ringBufSize
Definition: UARTMSP432E4.h:555
unsigned char * readBuf
Definition: UARTMSP432E4.h:612
uint32_t intPriority
Definition: UARTMSP432E4.h:549
unsigned int writeTimeout
Definition: UARTMSP432E4.h:624
Complement set of read functions to be used by the UART ISR and UARTMSP432E4_read(). Internal use only.
Definition: UARTMSP432E4.h:483
void(* UART_Callback)(UART_Handle handle, void *buf, size_t count)
The definition of a callback function used by the UART driver when used in UART_MODE_CALLBACK The cal...
Definition: UART.h:438
enum UART_DataMode_ UART_DataMode
UART data mode settings.
struct UARTMSP432E4_Object * UARTMSP432E4_Handle