IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 8.32.2.178

BIOS Version: bios_6_76_00_06_eng_k3

XDCTools Version: xdctools_3_55_00_09_core_eng

Benchmark	Cycles
Interrupt Latency	144
Hwi_restore()	14
Hwi_disable()	16
Hwi dispatcher prolog	118
Hwi dispatcher epilog	251
Hwi dispatcher	358
Hardware Interrupt to Blocked Task	579
Hardware Interrupt to Software Interrupt	393
Swi_enable()	79
Swi_disable()	17
Post Software Interrupt Again	24
Post Software Interrupt without Context Switch	106
Post Software Interrupt with Context Switch	211
Create a New Task without Context Switch	2670
Set a Task Priority without a Context Switch	195
Task_yield()	240
Post Semaphore No Waiting Task	82
Post Semaphore No Task Switch	204
Post Semaphore with Task Switch	276
Pend on Semaphore No Context Switch	78
Pend on Semaphore with Task Switch	314
Clock_getTicks()	15
POSIX Create a New Task without Context Switch	4738
POSIX Set a Task Priority without a Context Switch	250
POSIX Post Semaphore No Waiting Task	105
POSIX Post Semaphore No Task Switch	225
POSIX Post Semaphore with Task Switch	291
POSIX Pend on Semaphore No Context Switch	62
POSIX Pend on Semaphore with Task Switch	314

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.