IAR Cortex-M4 with hard FP Timing Benchmarks
Target Platform: ti.platforms.simplelink:CC2642:1
Tool Chain Version: 8.11.1.47
BIOS Version: bios_6_52_00_11_eng
XDCTools Version: xdctools_3_50_03_33_core
Benchmark | Cycles |
---|---|
Interrupt Latency | 160 |
Hwi_restore() | 15 |
Hwi_disable() | 15 |
Hwi dispatcher prolog | 153 |
Hwi dispatcher epilog | 241 |
Hwi dispatcher | 383 |
Hardware Interrupt to Blocked Task | 651 |
Hardware Interrupt to Software Interrupt | 456 |
Swi_enable() | 83 |
Swi_disable() | 19 |
Post Software Interrupt Again | 35 |
Post Software Interrupt without Context Switch | 112 |
Post Software Interrupt with Context Switch | 240 |
Create a New Task without Context Switch | 4650 |
Set a Task Priority without a Context Switch | 215 |
Task_yield() | 286 |
Post Semaphore No Waiting Task | 59 |
Post Semaphore No Task Switch | 223 |
Post Semaphore with Task Switch | 334 |
Pend on Semaphore No Context Switch | 74 |
Pend on Semaphore with Task Switch | 372 |
Clock_getTicks() | 296 |
POSIX Create a New Task without Context Switch | 7199 |
POSIX Set a Task Priority without a Context Switch | 303 |
POSIX Post Semaphore No Waiting Task | 72 |
POSIX Post Semaphore No Task Switch | 236 |
POSIX Post Semaphore with Task Switch | 345 |
POSIX Pend on Semaphore No Context Switch | 88 |
POSIX Pend on Semaphore with Task Switch | 385 |
The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.
See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.