TI Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 18.1.1

BIOS Version: bios_6_55_00_05_eng

XDCTools Version: xdctools_3_50_05_11_core_eng

Benchmark	Cycles
Interrupt Latency	127
Hwi_restore()	10
Hwi_disable()	14
Hwi dispatcher prolog	105
Hwi dispatcher epilog	236
Hwi dispatcher	335
Hardware Interrupt to Blocked Task	631
Hardware Interrupt to Software Interrupt	373
Swi_enable()	84
Swi_disable()	13
Post Software Interrupt Again	39
Post Software Interrupt without Context Switch	99
Post Software Interrupt with Context Switch	201
Create a New Task without Context Switch	2765
Set a Task Priority without a Context Switch	189
Task_yield()	268
Post Semaphore No Waiting Task	92
Post Semaphore No Task Switch	246
Post Semaphore with Task Switch	353
Pend on Semaphore No Context Switch	83
Pend on Semaphore with Task Switch	342
Clock_getTicks()	8
POSIX Create a New Task without Context Switch	5015
POSIX Set a Task Priority without a Context Switch	254
POSIX Post Semaphore No Waiting Task	105
POSIX Post Semaphore No Task Switch	262
POSIX Post Semaphore with Task Switch	369
POSIX Pend on Semaphore No Context Switch	96
POSIX Pend on Semaphore with Task Switch	362

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.