TI Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 18.1.1

BIOS Version: bios_6_55_00_05_eng

XDCTools Version: xdctools_3_50_05_11_core_eng

Benchmark	Cycles
Interrupt Latency	135
Hwi_restore()	6
Hwi_disable()	8
Hwi dispatcher prolog	114
Hwi dispatcher epilog	210
Hwi dispatcher	314
Hardware Interrupt to Blocked Task	562
Hardware Interrupt to Software Interrupt	327
Swi_enable()	60
Swi_disable()	8
Post Software Interrupt Again	30
Post Software Interrupt without Context Switch	82
Post Software Interrupt with Context Switch	158
Create a New Task without Context Switch	2142
Set a Task Priority without a Context Switch	143
Task_yield()	239
Post Semaphore No Waiting Task	72
Post Semaphore No Task Switch	191
Post Semaphore with Task Switch	310
Pend on Semaphore No Context Switch	62
Pend on Semaphore with Task Switch	296
Clock_getTicks()	7
POSIX Create a New Task without Context Switch	3771
POSIX Set a Task Priority without a Context Switch	188
POSIX Post Semaphore No Waiting Task	81
POSIX Post Semaphore No Task Switch	203
POSIX Post Semaphore with Task Switch	323
POSIX Pend on Semaphore No Context Switch	74
POSIX Pend on Semaphore with Task Switch	309

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –abi=eabi –float_support=fpv4spd16 -ms –opt_for_speed=2 –program_level_compile -o3”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.