TI Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC2642:1

Tool Chain Version: 18.1.1

BIOS Version: bios_6_55_00_05_eng

XDCTools Version: xdctools_3_50_05_11_core_eng

Benchmark	Cycles
Interrupt Latency	144
Hwi_restore()	14
Hwi_disable()	13
Hwi dispatcher prolog	145
Hwi dispatcher epilog	240
Hwi dispatcher	375
Hardware Interrupt to Blocked Task	642
Hardware Interrupt to Software Interrupt	447
Swi_enable()	82
Swi_disable()	17
Post Software Interrupt Again	36
Post Software Interrupt without Context Switch	116
Post Software Interrupt with Context Switch	238
Create a New Task without Context Switch	4653
Set a Task Priority without a Context Switch	178
Task_yield()	285
Post Semaphore No Waiting Task	60
Post Semaphore No Task Switch	222
Post Semaphore with Task Switch	332
Pend on Semaphore No Context Switch	75
Pend on Semaphore with Task Switch	372
Clock_getTicks()	354
POSIX Create a New Task without Context Switch	7302
POSIX Set a Task Priority without a Context Switch	232
POSIX Post Semaphore No Waiting Task	71
POSIX Post Semaphore No Task Switch	235
POSIX Post Semaphore with Task Switch	346
POSIX Pend on Semaphore No Context Switch	90
POSIX Pend on Semaphore with Task Switch	388

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –abi=eabi –float_support=fpv4spd16 -ms –opt_for_speed=2 –program_level_compile -o3”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.