TI Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.msp432:MSP432P401R:1

Tool Chain Version: 18.1.0

BIOS Version: bios_6_55_00_04_eng

XDCTools Version: xdctools_3_50_05_11_core_eng

Benchmark	Cycles
Interrupt Latency	133
Hwi_restore()	6
Hwi_disable()	7
Hwi dispatcher prolog	122
Hwi dispatcher epilog	222
Hwi dispatcher	333
Hardware Interrupt to Blocked Task	600
Hardware Interrupt to Software Interrupt	353
Swi_enable()	64
Swi_disable()	9
Post Software Interrupt Again	30
Post Software Interrupt without Context Switch	88
Post Software Interrupt with Context Switch	173
Create a New Task without Context Switch	2250
Set a Task Priority without a Context Switch	151
Task_yield()	251
Post Semaphore No Waiting Task	76
Post Semaphore No Task Switch	205
Post Semaphore with Task Switch	330
Pend on Semaphore No Context Switch	65
Pend on Semaphore with Task Switch	314
Clock_getTicks()	8
POSIX Create a New Task without Context Switch	3978
POSIX Set a Task Priority without a Context Switch	196
POSIX Post Semaphore No Waiting Task	85
POSIX Post Semaphore No Task Switch	216
POSIX Post Semaphore with Task Switch	342
POSIX Pend on Semaphore No Context Switch	78
POSIX Pend on Semaphore with Task Switch	328

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –abi=eabi –float_support=fpv4spd16 -ms –opt_for_speed=2 –program_level_compile -o3”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.