TI Cortex-M3 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC1350:1

Tool Chain Version: 18.1.1

BIOS Version: bios_6_55_00_05_eng

XDCTools Version: xdctools_3_50_05_11_core_eng

Benchmark Cycles
Interrupt Latency 126
Hwi_restore() 13
Hwi_disable() 13
Hwi dispatcher prolog 112
Hwi dispatcher epilog 204
Hwi dispatcher 306
Hardware Interrupt to Blocked Task 531
Hardware Interrupt to Software Interrupt 379
Swi_enable() 74
Swi_disable() 15
Post Software Interrupt Again 37
Post Software Interrupt without Context Switch 105
Post Software Interrupt with Context Switch 210
Create a New Task without Context Switch 4640
Set a Task Priority without a Context Switch 158
Task_yield() 211
Post Semaphore No Waiting Task 61
Post Semaphore No Task Switch 201
Post Semaphore with Task Switch 264
Pend on Semaphore No Context Switch 72
Pend on Semaphore with Task Switch 300
Clock_getTicks() 366
POSIX Create a New Task without Context Switch 7439
POSIX Set a Task Priority without a Context Switch 212
POSIX Post Semaphore No Waiting Task 72
POSIX Post Semaphore No Task Switch 214
POSIX Post Semaphore with Task Switch 278
POSIX Pend on Semaphore No Context Switch 87
POSIX Pend on Semaphore with Task Switch 316

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M3 –abi=eabi -ms –opt_for_speed=2 –program_level_compile -o3”.

The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.