IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 8.20.2.58

BIOS Version: bios_6_55_00_05_eng

XDCTools Version: xdctools_3_50_05_11_core_eng

Benchmark Cycles
Interrupt Latency 116
Hwi_restore() 7
Hwi_disable() 9
Hwi dispatcher prolog 95
Hwi dispatcher epilog 197
Hwi dispatcher 282
Hardware Interrupt to Blocked Task 508
Hardware Interrupt to Software Interrupt 309
Swi_enable() 56
Swi_disable() 12
Post Software Interrupt Again 20
Post Software Interrupt without Context Switch 81
Post Software Interrupt with Context Switch 165
Create a New Task without Context Switch 1917
Set a Task Priority without a Context Switch 156
Task_yield() 214
Post Semaphore No Waiting Task 63
Post Semaphore No Task Switch 191
Post Semaphore with Task Switch 268
Pend on Semaphore No Context Switch 57
Pend on Semaphore with Task Switch 271
Clock_getTicks() 9
POSIX Create a New Task without Context Switch 3372
POSIX Set a Task Priority without a Context Switch 197
POSIX Post Semaphore No Waiting Task 76
POSIX Post Semaphore No Task Switch 203
POSIX Post Semaphore with Task Switch 273
POSIX Pend on Semaphore No Context Switch 48
POSIX Pend on Semaphore with Task Switch 278

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.