GCC Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC2642:1

Tool Chain Version: 7.2.1

BIOS Version: bios_6_55_00_05_eng

XDCTools Version: xdctools_3_50_05_12_core

Benchmark Cycles
Interrupt Latency 176
Hwi_restore() 17
Hwi_disable() 16
Hwi dispatcher prolog 151
Hwi dispatcher epilog 240
Hwi dispatcher 382
Hardware Interrupt to Blocked Task 650
Hardware Interrupt to Software Interrupt 454
Swi_enable() 90
Swi_disable() 20
Post Software Interrupt Again 37
Post Software Interrupt without Context Switch 117
Post Software Interrupt with Context Switch 240
Create a New Task without Context Switch 4650
Set a Task Priority without a Context Switch 190
Task_yield() 287
Post Semaphore No Waiting Task 61
Post Semaphore No Task Switch 224
Post Semaphore with Task Switch 335
Pend on Semaphore No Context Switch 75
Pend on Semaphore with Task Switch 375
Clock_getTicks() 220
POSIX Create a New Task without Context Switch 7599
POSIX Set a Task Priority without a Context Switch 274
POSIX Post Semaphore No Waiting Task 73
POSIX Post Semaphore No Task Switch 238
POSIX Post Semaphore with Task Switch 349
POSIX Pend on Semaphore No Context Switch 90
POSIX Pend on Semaphore with Task Switch 388

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings:

“-mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -Dti_sysbios_Build_useHwiMacros -Dfar= -D__DYNAMIC_REENT__”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.