GCC Cortex-A9 with hard FP Timing Benchmarks

Target Platform: ti.platforms.sdp4430

Tool Chain Version: 7.2.1

BIOS Version: bios_6_55_00_05_eng

XDCTools Version: xdctools_3_50_05_11_core_eng

Benchmark	Cycles
Interrupt Latency	352
Hwi_restore()	8
Hwi_disable()	4
Hwi dispatcher prolog	196
Hwi dispatcher epilog	166
Hwi dispatcher	367
Hardware Interrupt to Blocked Task	617
Hardware Interrupt to Software Interrupt	368
Swi_enable()	78
Swi_disable()	18
Post Software Interrupt Again	24
Post Software Interrupt without Context Switch	81
Post Software Interrupt with Context Switch	151
Create a New Task without Context Switch	1806
Set a Task Priority without a Context Switch	99
Task_yield()	260
Post Semaphore No Waiting Task	81
Post Semaphore No Task Switch	192
Post Semaphore with Task Switch	314
Pend on Semaphore No Context Switch	35
Pend on Semaphore with Task Switch	302
Clock_getTicks()	5
POSIX Create a New Task without Context Switch	3590
POSIX Set a Task Priority without a Context Switch	88
POSIX Post Semaphore No Waiting Task	84
POSIX Post Semaphore No Task Switch	218
POSIX Post Semaphore with Task Switch	343
POSIX Pend on Semaphore No Context Switch	37
POSIX Pend on Semaphore with Task Switch	314

As the timer used to run these benchmarks is run at 1/2 the CPU frequency, an deviation of +-2 cycles is to be expected.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.