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32
33 34 35 36
37 package ti.sysbios.family.arm.m3;
38
39 import xdc.rov.ViewInfo;
40 import xdc.runtime.Diags;
41 import xdc.runtime.Log;
42 import xdc.runtime.Assert;
43 import xdc.runtime.Error;
44 import xdc.runtime.Types;
45
46 import ti.sysbios.BIOS;
47 import ti.sysbios.interfaces.IHwi;
48
49 /*!
50 * ======== Hwi ========
51 * Cortex M3/M4 Hardware Interrupt Manager
52 *
53 * The Cortex-M devices' Nested Vectored Interrupt Controller (NVIC)
54 * supports up to 256 interrupts/exceptions. In practice, most
55 * devices support much fewer (ie the SimpleLink CC13XX/CC26XX
56 * family of devices have only 50 total interrupts defined).
57 *
58 * SYS/BIOS Interrupt IDs or interrupt numbers correspond
59 * to an interrupt's position in the interrupt vector table.
60 *
61 * ID 0 corresponds to vector 0 which is used by the NVIC
62 * to hold the initial (reset) stack pointer value.
63 *
64 * ID 1 corresponds to vector 1 which is the reset vector which is
65 * usually initialized to point to an application's entry point
66 * (ie for the TI compiler tool chain, the entry point is "_c_int00")
67 *
68 * IDs 2-13 are, by default, hard wired to the internal exception handler
69 * which will save important context information that can be viewed
70 * using the ROV tool within either the Code Composer Studio debugger
71 * or the IAR Workbench debugger.
72 *
73 * ID 14 is the "pendSV" handler which is used exclusively by the shared
74 * interrupt dispatcher to orchestrate the execution of
75 * {@link ti.sysbios.knl.Swi Swis} posted
76 * from within interrupts, as well as to manage asynchronous
77 * task pre-emption upon returning from interrupts which have
78 * readied a task of higher priority than the task that
79 * was interrupted.
80 *
81 * ID 15 is the SysTick timer interrupt.
82 *
83 * ID's 16-255 are mapped to the NVIC's "User" interrupts 0-239
84 * which are tied to platform specific interrupt sources.
85 *
86 * @a(Zero Latency Interrupts)
87 * The M3/M4 Hwi module supports "zero latency" interrupts.
88 * Interrupts configured with priority greater (in actual
89 * hardware priority, but lower in number) than the configured
90 * {@link #disablePriority Hwi.disablePriority} are NOT
91 * disabled by {@link #disable Hwi_disable()}, and they are not managed by
92 * the internal interrupt dispatcher.
93 *
94 * Zero Latency interrupts fall into the commonly used category
95 * of "Unmanaged Interrupts". However they are somewhat distinct from
96 * that definition in that in addition to being unmanaged, they are
97 * also almost never disabled by SYS/BIOS code, thus gaining the
98 * "Zero Latency" title.
99 *
100 * Zero latency interrupts are distinguished from regular dispatched
101 * interrupts at create time solely by their interrupt priority being
102 * set greater than the configured Hwi.disablePriority.
103 *
104 * Note that since zero latency interrupts don't use the dispatcher,
105 * the {@link ti.sysbios.interfaces.IHwi#arg arg} parameter is not
106 * functional. Also note that due to the Cortex-M's native automatic
107 * stacking of saved-by-caller C context on the way to an ISR, zero
108 * latency interrupt handlers are implemented using regular C functions
109 * (ie no 'interrupt' keyword is required).
110 *
111 * @a(WARNING)
112 * Zero latency interrupts are NOT HANDLED by the SYS/BIOS
113 * interrupt dispatcher! Instead, they are vectored to directly.
114 * As such, and because they are NOT DISABLED BY Hwi_disable(),
115 * these interrupt handlers are SEVERELY RESTRICTED in terms of the
116 * SYS/BIOS APIs they can invoke and THREAD SAFETY MUST BE CAREFULLY
117 * CONSIDERED! See the descriptions of {@link #disable Hwi_disable()} and
118 * and {@link #disablePriority Hwi.disablePriority} for more details.
119 *
120 * @a(Interrupt Masking Options)
121 *
122 * The NVIC interrupt controller is designed for priority based
123 * interrupts.
124 *
125 * In this Hwi module, the {@link #maskSetting} instance configuration
126 * parameter is ignored.
127 * Effectively, only the {@link #MaskingOption_LOWER} is supported.
128 *
129 * @a(Interrupt Priorities)
130 *
131 * In general, the NVIC supports priority values of 0 thru 255.
132 *
133 * In practice, the number of priorities and their values are device
134 * dependent, and their nesting behaviors depend on the
135 * {@link #priGroup Hwi.priGroup} setting.
136 *
137 * For most TI MCU devices, 8 priorities are supported. A peculiarity
138 * of ARM's NVIC is that, although the priority field is an 8 bit value,
139 * the range of supported priority values are left-justified within this
140 * 8 bit field. Consequently, the 8 priority values are not 0 thru 7 as
141 * one might expect, but rather:
142 *
143 * @p(code)
144 * 0x00 // highest priority, non dispatched, Zero Latency priority
145 * 0x20 // highest dispatched interrupt priority
146 * 0x40
147 * 0x60
148 * 0x80
149 * 0xa0
150 * 0xc0
151 * 0xe0 // lowest dispatched interrupt priority, (default)
152 * @p
153 *
154 * Priority 0 is the highest priority and by default is
155 * reserved for zero latency interrupts
156 * (see {@link #disablePriority Hwi.disablePriority}).
157 *
158 * See the {@link http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/CIHIGCIF.html Cortex M4 Devices Generic User Guide}
159 * for details on the behavior of interrupt priorities and their relationship
160 * to the {@link #priGroup Hwi.priGroup} setting.
161 *
162 * @a(Interrupt Vector Tables)
163 * SimpleLink CC13XX/CC26XX devices:
164 *
165 * By default, two vector tables are created for SimpleLink devices:
166 *
167 * A 15 entry boot vector table is placed at address 0x00000000 in
168 * FLASH.
169 *
170 * A 50 entry vector table is placed at address 0x20000000 in RAM.
171 *
172 * The FLASH boot vector table contains the reset vector and exception
173 * handler vectors used until the RAM based vector table is initialized.
174 *
175 * The RAM vector table contains those same first 15 vectors as well as
176 * the SysTick vector and the remainder of the user interrupt vectors.
177 *
178 * During system startup, the NVIC Vector Table Offset Registor is
179 * intialized to point to the RAM vector table after it has been
180 * initialized.
181 *
182 * @a( )
183 * Dual M3/M4 Core ('Ducati'/'Benelli') devices:
184 *
185 * By default, Ducati/Benelli core 0 places its runtime vector table at
186 * address 0x00000400 and core 1 places its runtime vector table at
187 * address 0x00000800.
188 *
189 * Additionally, a boot vector table is placed at address
190 * 0x00000000 which is shared by both cores.
191 *
192 * The boot reset vector function determines which core it is being
193 * executed on and jumps to the reset vector contained in its corresponding
194 * runtime vector table.
195 *
196 * The generation and placement of these vector tables is made
197 * automatically when the
198 * {@link ti.sysbios.family.arm.ducati.Core} module is used.
199 *
200 * Although STRONGLY discouraged, this default behavior can be overridden
201 * by explicitly setting the
202 * {@link #resetVectorAddress Hwi.resetVectorAddress} and
203 * {@link #vectorTableAddress Hwi.vectorTableAddress} config parameters.
204 *
205 * @a(Restrictions)
206 * When used within a dual M3/M4 core (Ducati/Benelli) arrangement, care
207 * must be taken when initializing this shared resource.
208 * The "Shared Resources" note provided
209 * in the {@link ti.sysbios.family.arm.ducati ducati} package discusses
210 * the management of the various hardware and software resources
211 * shared by the two M3/M4 cores.
212 * @a
213 *
214 * @p(html)
215 * <h3> Calling Context </h3>
216 * <table border="1" cellpadding="3">
217 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
218 *
219 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
220 * <!-- -->
221 * <tr><td> {@link #clearInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
222 * <tr><td> {@link #create} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
223 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
224 * <tr><td> {@link #disableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
225 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> N </td><td> N </td></tr>
226 * <tr><td> {@link #enableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
227 * <tr><td> {@link #Params_init} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
228 * <tr><td> {@link #restore} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
229 * <tr><td> {@link #restoreInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
230 * <tr><td> {@link #construct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
231 * <tr><td> {@link #delete} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
232 * <tr><td> {@link #destruct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
233 * <tr><td> {@link #getHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
234 * <tr><td> {@link #setFunc} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
235 * <tr><td> {@link #setHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
236 * <tr><td colspan="6"> Definitions: <br />
237 * <ul>
238 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
239 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
240 * <li> <b>Task</b>: API is callable from a Task thread. </li>
241 * <li> <b>Main</b>: API is callable during any of these phases: </li>
242 * <ul>
243 * <li> In your module startup after this module is started (e.g. Hwi_Module_startupDone() returns TRUE). </li>
244 * <li> During xdc.runtime.Startup.lastFxns. </li>
245 * <li> During main().</li>
246 * <li> During BIOS.startupFxns.</li>
247 * </ul>
248 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
249 * <ul>
250 * <li> During xdc.runtime.Startup.firstFxns.</li>
251 * <li> In your module startup before this module is started (e.g. Hwi_Module_startupDone() returns FALSE).</li>
252 * </ul>
253 * </ul>
254 * </td></tr>
255 *
256 * </table>
257 * @p
258 */
259
260
261 @Template("./Hwi.xdt")
262 @ModuleStartup
263 @InstanceInitStatic
264
265 module Hwi inherits ti.sysbios.interfaces.IHwi
266 {
267
268
269 /*!
270 * The Cortex M3/M4 NVIC supports up to 256 interrupts/exceptions.
271 *
272 * The actual number supported is device specific and provided by
273 * the catalog device specification.
274 */
275 config Int NUM_INTERRUPTS;
276
277 /*!
278 * The Cortex M3/M4 NVIC supports up to 256 interrupt priorities.
279 *
280 * The actual number supported is device specific and provided by
281 * the catalog device specification. For all TI SimpleLink devices,
282 * 8 priorities are supported.
283 */
284 config Int NUM_PRIORITIES;
285
286
287
288 /*! Hwi vector function type definition. */
289 typedef Void (*VectorFuncPtr)(void);
290
291 /*! Exception hook function type definition. */
292 typedef Void (*ExceptionHookFuncPtr)(ExcContext *);
293
294 /*! NVIC Configuration Control Register (CCR). */
295 struct CCR {
296 Bits8 STKALIGN; /*! Auto stack alignment in exception */
297 Bits8 BFHFNMIGN; /*! All faults ignore BUS Faults */
298 Bits8 DIV_0_TRP; /*! Trap on divide by zero */
299 Bits8 UNALIGN_TRP; /*! Trap on all unaligned accesses */
300 Bits8 USERSETMPEND; /*! Allow user to trigger interrupts */
301 Bits8 NONEBASETHRDENA; /*! Allow entering thread mode anytime */
302 };
303
304 /*! @_nodoc
305 * Nested Vectored Interrupt Controller.
306 */
307 struct NVIC {
308 UInt32 RES_00; /*! 0xE000E000 reserved */
309 UInt32 ICTR; /*! 0xE000E004 Interrupt Control Type */
310 UInt32 RES_08; /*! 0xE000E008 reserved */
311 UInt32 RES_0C; /*! 0xE000E00C reserved */
312 UInt32 STCSR; /*! 0xE000E010 SysTick Control & Status Register */
313 UInt32 STRVR; /*! 0xE000E014 SysTick Reload Value Register */
314 UInt32 STCVR; /*! 0xE000E018 SysTick Current Value Register */
315 UInt32 STCALIB; /*! 0xE000E01C SysTick Calibration Value Register */
316 UInt32 RES_20 [56]; /*! 0xE000E020-0xE000E0FC reserved */
317 UInt32 ISER [8]; /*! 0xE000E100-0xE000E11C Interrupt Set Enable Registers */
318 UInt32 RES_120 [24]; /*! 0xE000E120-0xE000E17C reserved */
319 UInt32 ICER [8]; /*! 0xE000E180-0xE000E19C Interrupt Clear Enable Registers */
320 UInt32 RES_1A0 [24]; /*! 0xE000E1A0-0xE000E1FC reserved */
321 UInt32 ISPR [8]; /*! 0xE000E200-0xE000E21C Interrupt Set Pending Registers */
322 UInt32 RES_220 [24]; /*! 0xE000E220-0xE000E7C reserved */
323 UInt32 ICPR [8]; /*! 0xE000E280-0xE000E29C Interrupt Clear Pending Registers */
324 UInt32 RES_2A0 [24]; /*! 0xE000E2A0-0xE000E2FC reserved */
325 UInt32 IABR [8]; /*! 0xE000E300-0xE000E31C Interrupt Active Bit Registers */
326 UInt32 RES_320 [56]; /*! 0xE000E320-0xE000E3FC reserved */
327 UInt8 IPR [240]; /*! 0xE000E400-0xE000E4EF Interrupt Priority Registers */
328 UInt32 RES_4F0 [516];/*! 0xE000E4F0-0xE000ECFC reserved */
329 UInt32 CPUIDBR; /*! 0xE000ED00 CPUID Base Register */
330 UInt32 ICSR; /*! 0xE000ED04 Interrupt Control State Register */
331 UInt32 VTOR; /*! 0xE000ED08 Vector Table Offset Register */
332 UInt32 AIRCR; /*! 0xE000ED0C Application Interrupt/Reset Control Register */
333 UInt32 SCR; /*! 0xE000ED10 System Control Register */
334 UInt32 CCR; /*! 0xE000ED14 Configuration Control Register */
335 UInt8 SHPR[12]; /*! 0xE000ED18 System Handlers 4-15 Priority Registers */
336 UInt32 SHCSR; /*! 0xE000ED24 System Handler Control & State Register */
337 UInt8 MMFSR; /*! 0xE000ED28 Memory Manage Fault Status Register */
338 UInt8 BFSR; /*! 0xE000ED29 Bus Fault Status Register */
339 UInt16 UFSR; /*! 0xE000ED2A Usage Fault Status Register */
340 UInt32 HFSR; /*! 0xE000ED2C Hard Fault Status Register */
341 UInt32 DFSR; /*! 0xE000ED30 Debug Fault Status Register */
342 UInt32 MMAR; /*! 0xE000ED34 Memory Manager Address Register */
343 UInt32 BFAR; /*! 0xE000ED38 Bus Fault Address Register */
344 UInt32 AFSR; /*! 0xE000ED3C Auxiliary Fault Status Register */
345 UInt32 PFR0; /*! 0xE000ED40 Processor Feature Register */
346 UInt32 PFR1; /*! 0xE000ED44 Processor Feature Register */
347 UInt32 DFR0; /*! 0xE000ED48 Debug Feature Register */
348 UInt32 AFR0; /*! 0xE000ED4C Auxiliary Feature Register */
349 UInt32 MMFR0; /*! 0xE000ED50 Memory Model Fault Register0 */
350 UInt32 MMFR1; /*! 0xE000ED54 Memory Model Fault Register1 */
351 UInt32 MMFR2; /*! 0xE000ED58 Memory Model Fault Register2 */
352 UInt32 MMFR3; /*! 0xE000ED5C Memory Model Fault Register3 */
353 UInt32 ISAR0; /*! 0xE000ED60 ISA Feature Register0 */
354 UInt32 ISAR1; /*! 0xE000ED64 ISA Feature Register1 */
355 UInt32 ISAR2; /*! 0xE000ED68 ISA Feature Register2 */
356 UInt32 ISAR3; /*! 0xE000ED6C ISA Feature Register3 */
357 UInt32 ISAR4; /*! 0xE000ED70 ISA Feature Register4 */
358 UInt32 RES_D74[5]; /*! 0xE000ED74-0xE000ED84 reserved */
359 UInt32 CPACR; /*! 0xE000ED88 Coprocessor Access Control Register */
360 UInt32 RES_D8C[93]; /*! 0xE000ED8C-0xE000EEFC reserved */
361 UInt32 STI; /*! 0xE000EF00 Software Trigger Interrupt Register */
362 UInt32 RES_F04[12]; /*! 0xE000EF04-0xE000EF30 reserved */
363 UInt32 FPCCR; /*! 0xE000EF34 FP Context Control Register */
364 UInt32 FPCAR; /*! 0xE000EF38 FP Context Address Register */
365 UInt32 FPDSCR; /*! 0xE000EF3C FP Default Status Control Register */
366 UInt32 MVFR0; /*! 0xE000EF40 Media & FP Feature Register0 */
367 UInt32 MVFR1; /*! 0xE000EF44 Media & FP Feature Register1 */
368 UInt32 RES_F48[34]; /*! 0xE000EF48-0xE000EFCC reserved */
369 UInt32 PID4; /*! 0xE000EFD0 Peripheral ID Register4 */
370 UInt32 PID5; /*! 0xE000EFD4 Peripheral ID Register5 */
371 UInt32 PID6; /*! 0xE000EFD8 Peripheral ID Register6 */
372 UInt32 PID7; /*! 0xE000EFDC Peripheral ID Register7 */
373 UInt32 PID0; /*! 0xE000EFE0 Peripheral ID Register0 */
374 UInt32 PID1; /*! 0xE000EFE4 Peripheral ID Register1 */
375 UInt32 PID2; /*! 0xE000EFE8 Peripheral ID Register2 */
376 UInt32 PID3; /*! 0xE000EFEC Peripheral ID Register3 */
377 UInt32 CID0; /*! 0xE000EFF0 Component ID Register0 */
378 UInt32 CID1; /*! 0xE000EFF4 Component ID Register1 */
379 UInt32 CID2; /*! 0xE000EFF8 Component ID Register2 */
380 UInt32 CID3; /*! 0xE000EFFC Component ID Register3 */
381 }
382
383 /*!
384 * Physical Nested Vectored Interrupt Controller Device.
385 * Short name is "Hwi_nvic"
386 * Long name is "ti_sysbios_family_arm_m3_Hwi_nvic"
387 */
388 extern volatile NVIC nvic;
389
390 /*!
391 * Virtual Nested Vectored Interrupt Controller structure
392 * written to by both cores for SMP.
393 * Short name is "Hwi_vnvic"
394 * Long name is "ti_sysbios_family_arm_m3_Hwi_vnvic"
395 */
396 extern volatile NVIC vnvic;
397
398 /*!
399 * Exception Context - Register contents at the time of an exception.
400 */
401 struct ExcContext {
402
403 BIOS.ThreadType threadType;
404
405 Ptr threadHandle;
406
407 Ptr threadStack;
408
409
410 SizeT threadStackSize;
411
412
413 Ptr r0;
414 Ptr r1;
415 Ptr r2;
416 Ptr r3;
417 Ptr r4;
418 Ptr r5;
419 Ptr r6;
420 Ptr r7;
421 Ptr r8;
422 Ptr r9;
423 Ptr r10;
424 Ptr r11;
425 Ptr r12;
426 Ptr sp;
427 Ptr lr;
428 Ptr pc;
429 Ptr psr;
430
431
432 Ptr ICSR;
433 Ptr MMFSR;
434 Ptr BFSR;
435 Ptr UFSR;
436 Ptr HFSR;
437 Ptr DFSR;
438 Ptr MMAR;
439 Ptr BFAR;
440 Ptr AFSR;
441 }
442
443 struct Struct2__ {
444 Ptr fxns;
445 UArg arg;
446 FuncPtr fxn;
447 Irp irp;
448 UInt8 priority;
449 Int16 intNum;
450 Ptr hookEnv;
451 Types.CordAddr name;
452 };
453
454 typedef Struct2__ Struct2;
455
456 /*! @_nodoc */
457 metaonly struct BasicView {
458 Ptr halHwiHandle;
459 String label;
460 String type;
461 Int intNum;
462 Int priority;
463 Int group;
464 Int subPriority;
465 String fxn;
466 UArg arg;
467 };
468
469 /*! @_nodoc */
470 metaonly struct DetailedView {
471 Ptr halHwiHandle;
472 String label;
473 String type;
474 Int intNum;
475 Int priority;
476 Int group;
477 Int subPriority;
478 String fxn;
479 UArg arg;
480 Ptr irp;
481 String status;
482 Int coreId;
483 };
484
485 /*! @_nodoc */
486 metaonly struct ModuleView {
487 String options[4];
488 String activeInterrupt;
489 String pendingInterrupt;
490 String exception;
491 String hwiStackPeak;
492 SizeT hwiStackSize;
493 Ptr hwiStackBase;
494 };
495
496 /*! @_nodoc */
497 @Facet
498 metaonly config ViewInfo.Instance rovViewInfo =
499 ViewInfo.create({
500 viewMap: [
501 ['Basic',
502 {
503 type: ViewInfo.INSTANCE,
504 viewInitFxn: 'viewInitBasic',
505 structName: 'BasicView'
506 }
507 ],
508 ['Detailed',
509 {
510 type: ViewInfo.INSTANCE,
511 viewInitFxn: 'viewInitDetailed',
512 structName: 'DetailedView'
513 }
514 ],
515 ['Module',
516 {
517 type: ViewInfo.MODULE,
518 viewInitFxn: 'viewInitModule',
519 structName: 'ModuleView'
520 }
521 ],
522 ['Exception',
523 {
524 type: ViewInfo.TREE,
525 viewInitFxn: 'viewInitException',
526 structName: 'ExcContext'
527 }
528 ]
529 ]
530 });
531
532
533
534
535
536 /*!
537 * Issued just prior to Hwi function invocation (with interrupts disabled)
538 */
539 config Log.Event LM_begin = {
540 mask: Diags.USER1 | Diags.USER2,
541 msg: "LM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x"
542 };
543
544 /*!
545 * Issued just after return from Hwi function (with interrupts disabled)
546 */
547 config Log.Event LD_end = {
548 mask: Diags.USER2,
549 msg: "LD_end: hwi: 0x%x"
550 };
551
552
553
554 /*! Assert when bad maskSetting parameter provided */
555 config Assert.Id A_unsupportedMaskingOption = {
556 msg: "A_unsupportedMaskingOption: unsupported maskSetting."
557 };
558
559
560
561 /*!
562 * Error raised when Hwi is already defined
563 */
564 config Error.Id E_alreadyDefined = {
565 msg: "E_alreadyDefined: Hwi already defined: intr# %d"
566 };
567
568 /*!
569 * Error raised when the number of interrupts being created
570 * exceeds the number supported.
571 */
572 config Error.Id E_hwiLimitExceeded = {
573 msg: "E_hwiLimitExceeded: Too many interrupts defined"
574 };
575
576 /*!
577 * Error raised when an exception occurs
578 */
579 config Error.Id E_exception = {
580 msg: "E_exception: id = %d, pc = %08x.\nTo see more exception detail, set ti.sysbios.family.arm.m3.Hwi.enableException = true or,\nexamine the Exception view for the ti.sysbios.family.arm.m3.Hwi module using ROV."
581 };
582
583 /*!
584 * Error raised when an uninitialized interrupt occurs
585 */
586 config Error.Id E_noIsr = {
587 msg: "E_noIsr: id = %d, pc = %08x"
588 };
589
590 /*!
591 * Error raised when NMI exception occurs
592 */
593 config Error.Id E_NMI = {
594 msg: "E_NMI: %s"
595 };
596
597 /*!
598 * Error raised when hard fault exception occurs
599 */
600 config Error.Id E_hardFault = {
601 msg: "E_hardFault: %s"
602 };
603
604 /*!
605 * Error raised when memory fault exception occurs
606 */
607 config Error.Id E_memFault = {
608 msg: "E_memFault: %s, address: %08x"
609 };
610
611 /*!
612 * Error raised when bus fault exception occurs
613 */
614 config Error.Id E_busFault = {
615 msg: "E_busFault: %s, address: %08x"
616 };
617
618 /*!
619 * Error raised when usage fault exception occurs
620 */
621 config Error.Id E_usageFault = {
622 msg: "E_usageFault: %s"
623 };
624
625 /*!
626 * Error raised when svCall exception occurs
627 */
628 config Error.Id E_svCall = {
629 msg: "E_svCall: svNum = %d"
630 };
631
632 /*!
633 * Error raised when debugMon exception occurs
634 */
635 config Error.Id E_debugMon = {
636 msg: "E_debugMon: %s"
637 };
638
639 /*!
640 * Error raised when reserved exception occurs
641 */
642 config Error.Id E_reserved = {
643 msg: "E_reserved: %s %d"
644 };
645
646
647
648 /*!
649 * Size (in number of interrupts) of the table used by the interrupt
650 * dispatcher to locate the corresponding Hwi object. By default,
651 * Hwi.dispatchTableSize will be internally set
652 * to the number of interrupts supported by the device.
653 *
654 * When the Hwi dispatch table size is equal to the number of interrupts
655 * supported {@link #NUM_INTERRUPTS} by the device, a linear-indexed
656 * dispatch table mechanism is used that will consume 4 bytes of RAM
657 * for each interrupt supported.
658 *
659 * If the dispatch table size is set to a number less than the number
660 * of interrupts supported by the device, then a non linear-indexed
661 * dispatch table mechanism is employed that uses 12 bytes of RAM for
662 * each interrupt supported.
663 *
664 * Consequently, for applications that use less than 1/3 of the total
665 * number of interrupts supported by the device, setting this parameter
666 * to the number of interrupts ACTUALLY USED will result in less RAM
667 * memory being used than otherwise.
668 *
669 * For applications that use very few interrupts, this can be a significant RAM memory savings.</p>
670 */
671 metaonly config UInt dispatchTableSize;
672
673 /*!
674 * Location of the Runtime Interrupt Vector Table.
675 * Default is device dependent.
676 *
677 * This parameter allows the user to override the default placement
678 * of the runtime interrupt vector table.
679 * The NVIC's Vector Table Offset
680 * Register (VTOR) is also programmed to this value.
681 *
682 * Some systems require the runtime vector table to be placed at
683 * an address
684 * other than 0 but still need a copy of the two M3/M4 boot vectors
685 * (SP and reset PC), located there. To achieve this, a separate
686 * parameter {@link #resetVectorAdress} is provided. If the
687 * resetVectorAddress has a different value then the vectorTableAddress
688 * then a separate vector table is generated and placed at that
689 * address.
690 *
691 * The vector table must be placed at an address at or lower than
692 * 0x3FFFFC00 and must be aligned on an even 64 word boundary.
693 */
694 metaonly config Ptr vectorTableAddress = 0x00000000;
695
696 /*!
697 * Reset vector table address. Default is 0x00000000.
698 *
699 * This parameter is the address of the vector table used
700 * at system reset time. Typically this is placed at 0x00000000.
701 *
702 * If the Hwi.resetVectorAddress has a different value than
703 * the {@link #vectorTableAddress Hwi.vectorTableAddress}
704 * then two vector tables are generated, one at the Hwi.resetVectorAddress
705 * and another at the {@link #vectorTableAddress Hwi.vectorTableAddress}.
706 *
707 * After the initial boot code has been executed at startup, the NVIC's
708 * Vector Table Offset Register will be programmed to point to the
709 * vector table at the {@link #vectorTableAddress Hwi.vectorTableAddress}.
710 *
711 * is created and placed in the ".resetVecs" section.
712 */
713 metaonly config Ptr resetVectorAddress = 0x00000000;
714
715 /*! Reset Handler (ID/vector #1). Default is c_int00 */
716 metaonly config VectorFuncPtr resetFunc;
717
718 /*! NMI Handler (ID/vector #2). Default is set to an internal exception handler */
719 metaonly config VectorFuncPtr nmiFunc;
720
721 /*! Hard Fault Handler (ID/vector #3). Default is set to an internal exception handler */
722 metaonly config VectorFuncPtr hardFaultFunc;
723
724 /*! Mem Fault Handler (ID/vector #4). Default is set to an internal exception handler */
725 metaonly config VectorFuncPtr memFaultFunc;
726
727 /*! Bus Fault Handler (ID/vector #5). Default is set to an internal exception handler */
728 metaonly config VectorFuncPtr busFaultFunc;
729
730 /*! Usage Fault Handler (ID/vector #6). Default is set to an internal exception handler */
731 metaonly config VectorFuncPtr usageFaultFunc;
732
733 /*! SVCall Handler (ID/vector #11). Default is set to an internal exception handler */
734 metaonly config VectorFuncPtr svCallFunc;
735
736 /*! Debug Mon Handler (ID/vector #12). Default is set to an internal exception handler */
737 metaonly config VectorFuncPtr debugMonFunc;
738
739 /*! Reserved Exception Handler (ID/vector #13). Default is set to an internal exception handler */
740 metaonly config VectorFuncPtr reservedFunc;
741
742 /*! Uninitialized ISR Handler. Default is set to an internal exception handler */
743 config VectorFuncPtr nullIsrFunc;
744
745 /*! Hwi exception handler function type definition. */
746 typedef Void (*ExcHandlerFuncPtr)(UInt *, UInt);
747
748 /*!
749 * Exception handler function pointer.
750 *
751 * The default is determined by the value of Hwi.enableException.
752 *
753 * If the user does NOT set this parameter, then the following default
754 * behavior is followed:
755 *
756 * If Hwi.enableException is true, then the internal 'Hwi_excHandlerMax'
757 * function is used. This exception handler saves the exception context
758 * then does a complete exception decode and dump to the console, then
759 * raises an Error. The exception context can be viewed within CCS
760 * in the ROV Hwi module's Exception view.
761 *
762 * If Hwi.enableException is false, then the internal 'Hwi_excHandlerMin'
763 * function is used. This exception handler saves the exception context
764 * then raises an Error. The exception context can be viewed within CCS
765 * in the ROV Hwi module's Exception view.
766 *
767 * If the user sets this parameter to their own function, then the user's
768 * function will be invoked with the following arguments:
769 *
770 * Void myExceptionHandler(UInt *excStack, UInt lr);
771 *
772 * Where 'excStack' is the address of the stack containing the
773 * register context at the time of the exception, and 'lr' is the
774 * link register value when the low-level-assembly-coded exception
775 * handler was vectored to.
776 *
777 * If this parameter is set to 'null', then an infinite while loop is
778 * entered when an exception occurs. This setting minimizes code and
779 * data footprint but provides no automatic exception decoding.
780 */
781 config ExcHandlerFuncPtr excHandlerFunc = excHandlerMax;
782
783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809
810 metaonly config UInt8 intAffinity[];
811
812 /*!
813 * Enable full exception decoding
814 *
815 * When this is enabled, the exception handler will fully
816 * decode an exception and dump the registers to the
817 * system console.
818 */
819 metaonly config Bool enableException = true;
820
821 /*!
822 * User Exception Context Buffer Address
823 *
824 * By default, when an exception occurs, an {@link #ExcContext}
825 * structure is allocated on the ISR stack and filled in within the
826 * exception handler.
827 *
828 * If {@link #excContextBuffer} is initialized by the user, the
829 * {@link #ExcContext} structure will be placed at that address instead.
830 *
831 * The buffer must be large enough to contain an {@link #ExcContext}
832 * structure.
833 */
834 metaonly config Ptr excContextBuffer;
835 metaonly config Ptr excContextBuffers[];
836
837 /*!
838 * User Exception Stack Buffer Address
839 *
840 * By default, when an exception occurs, a pointer to the base address
841 * of the stack being used by the thread causing the exception is placed
842 *
843 * If {@link #excStackBuffer} is initialized by the user, the
844 * stack contents of the thread causing the exception will be
845 * copied to that address instead.
846 *
847 * The buffer must be large enough to contain the largest task stack
848 * or ISR stack defined in the application.
849 */
850 metaonly config Ptr excStackBuffer;
851 metaonly config Ptr excStackBuffers[];
852
853
854 /*!
855 * User Exception hook function.
856 *
857 * Called just after the exception context has been initialized.
858 *
859 * This function will be run on the ISR stack.
860 *
861 * This function must run to completion.
862 *
863 * It is called without any Task or Swi scheduling protection
864 * and therefore can not call any functions that may cause a Swi or Task
865 * scheduling operation (Swi_post(), Semaphore_post(), Event_post(), etc).
866 */
867 config ExceptionHookFuncPtr excHookFunc = null;
868 config ExceptionHookFuncPtr excHookFuncs[];
869
870 /*!
871 * NVIC CCR register settings
872 *
873 * These setting are written to Hwi_nvic.CCR at startup time.
874 *
875 * See the {@link http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/Bhcjabhi.html Configuration and Control Register}
876 * description provided by ARM for more details
877 * on the meanings of these parameters.
878 */
879 metaonly config CCR nvicCCR = {
880 STKALIGN: 1,
881 BFHFNMIGN: 0,
882 DIV_0_TRP: 0,
883 UNALIGN_TRP: 0,
884 USERSETMPEND: 0,
885 NONEBASETHRDENA: 0
886 };
887
888 /*!
889 * The priority that BASEPRI is set to by Hwi_disable().
890 *
891 * All interrupts configured with equal or less priority (equal or
892 * higher number) than disablePriority are disabled by
893 * {@link #disable Hwi_disable}.
894 * Interrupts configured with higher priority (smaller number) than
895 * Hwi.disablePriority are non-maskable (ie zero-latency).
896 *
897 * The default setting is the second highest interrupt priority
898 * defined for the device (typically '0x20' for devices
899 * which support 8 priority values).
900 * This results in priority 0 (and all
901 * other values in the same priority group, ie 0x00 thru 0x1f)
902 * being the zero-latency, non-maskable interrupt priority.
903 * All other priorities are disabled with Hwi_disable().
904 */
905 config UInt disablePriority;
906
907 /*!
908 * The PRIGROUP setting. Default is 0.
909 *
910 * This value will be written to the PRIGROUP field
911 * within the NVIC's Application Interrupt and Reset Control
912 * Register (Hwi_nvic.AIRCR). It defines how the 8 bit priority
913 * values are interpreted by the hardware.
914 *
915 * Valid settings are 0-7.
916 *
917 * The default setting of 0 causes bits 7-1 of an interrupt's
918 * priority value to be used as pre-emption priority, while bit 0
919 * is used to determine which of two simultaneous interrupts with
920 * the same pre-emption priority will be serviced first.
921 *
922 * For most TI MCU devices, this means that each of the 8 supported
923 * priority values are unique pre-emption priorities and are not
924 * subdivided into priority groups.
925 *
926 * For more details regarding priority groups see the
927 * {@link http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/Cihehdge.html AIRCR}
928 * register description provided by ARM.
929 */
930 config UInt priGroup = 0;
931
932
933
934 /*!
935 * ======== construct2 ========
936 * Construct a Hwi object
937 *
938 * Hwi_construct2 constructs a Hwi object. This function is identical
939 * to Hwi_construct(), but does not take an Error_Block parameter, and
940 * returns a Hwi_Handle.
941 *
942 * The following C code sets Hwi parameters and
943 * constructs a Hwi object:
944 *
945 * @p(code)
946 *
947 * Hwi_Struct2 hwiStruct2;
948 * Hwi_Handle hwi;
949 *
950 * Void main()
951 * {
952 * Hwi_Params hwiParams;
953 *
954 * Hwi_Params_init(&hwiParams);
955 * hwiParams.arg = (UArg)arg;
956 * hwiParams.priority = intPriority;
957 *
958 * hwi = Hwi_construct2(&hwiStruct2, intNum, hwiFxn, &hwiParams);
959 * if (hwi == NULL) {
960 * // Failure
961 * }
962 *
963 * BIOS_start();
964 * }
965 * @p
966 *
967 * @param(hwi) Pointer to Hwi_Struct2 object.
968 * @param(intNum) Interrupt priority
969 * @param(hwiFxn) Hwi Function
970 * @param(prms) Pointer to Hwi_Params structure
971 *
972 * @b(returns) A Hwi handle
973 */
974 Handle construct2(Struct2 *hwi, Int intNum, FuncPtr hwiFxn,
975 const Params *prms);
976
977 /*!
978 * ======== disable ========
979 * Disable all non zero-latency interrupts
980 *
981 * Hwi_disable disables all non zero-latency hardware interrupts and
982 * returns an
983 * opaque key indicating whether interrupts were globally enabled or
984 * disabled on entry to Hwi_disable().
985 * The actual value of the key is target/device specific and is meant
986 * to be passed to Hwi_restore().
987 *
988 * Call Hwi_disable before a portion of a function that needs
989 * to run without interruption. When critical processing is complete, call
990 * Hwi_restore or Hwi_enable to reenable hardware interrupts.
991 *
992 * Servicing of interrupts that occur while interrupts are disabled is
993 * postponed until interrupts are reenabled. However, if the same type
994 * of interrupt occurs several times while interrupts are disabled,
995 * the interrupt's function is executed only once when interrupts are
996 * reenabled.
997 *
998 * A context switch can occur when calling Hwi_enable or Hwi_restore if
999 * an enabled interrupt occurred while interrupts are disabled.
1000 *
1001 * Hwi_disable may be called from main(). However, since Hwi interrupts
1002 * are already disabled in main(), such a call has no effect.
1003 *
1004 * @a(Implementation Note)
1005 * In order to support zero latency interrupts, rather
1006 * than setting PRIMASK (which would globally disable all NVIC
1007 * interrupts), Hwi_disable() instead writes the value of
1008 * {@link #disablePriority Hwi.disablePriority}
1009 * to the BASEPRI register. In doing so, all interrupts of equal or
1010 * lower priority than Hwi.disablePriority are disabled.
1011 *
1012 * @a(constraints)
1013 * If a Task switching API such as
1014 * {@link ti.sysbios.knl.Semaphore#pend Semaphore_pend()},
1015 * {@link ti.sysbios.knl.Semaphore#post Semaphore_post()},
1016 * {@link ti.sysbios.knl.Task#sleep Task_sleep()}, or
1017 * {@link ti.sysbios.knl.Task#yield Task_yield()}
1018 * is invoked which results in a context switch while
1019 * interrupts are disabled, an embedded call to
1020 * {@link #enable Hwi_enable} occurs
1021 * on the way to the new thread context which unconditionally re-enables
1022 * interrupts. Interrupts will remain enabled until a subsequent
1023 * {@link #disable Hwi_disable}
1024 * invocation.
1025 *
1026 * Swis always run with interrupts enabled.
1027 * See {@link ti.sysbios.knl.Swi#post Swi_post()} for a discussion Swis and
1028 * interrupts.
1029 *
1030 * @b(returns) opaque key for use by Hwi_restore()
1031 */
1032 @Macro
1033 override UInt disable();
1034
1035 /*!
1036 * ======== enable ========
1037 */
1038 @Macro
1039 override UInt enable();
1040
1041 /*!
1042 * ======== restore ========
1043 */
1044 @Macro
1045 override Void restore(UInt key);
1046
1047 /*!
1048 * @_nodoc
1049 * ======== disableFxn ========
1050 * function call implementation
1051 */
1052 UInt disableFxn();
1053
1054 /*!
1055 * @_nodoc
1056 * ======== enableFxn ========
1057 * function call implementation
1058 */
1059 UInt enableFxn();
1060
1061 /*!
1062 * @_nodoc
1063 * ======== restoreFxn ========
1064 * function call implementation
1065 */
1066 Void restoreFxn(UInt key);
1067
1068 /*!
1069 * ======== inUseMeta ========
1070 * @_nodoc
1071 * Check for Hwi already in use.
1072 * For internal SYS/BIOS use only.
1073 * Should be called prior to any internal Hwi.create().
1074 *
1075 * @param(intNum) interrupt number
1076 */
1077 metaonly Bool inUseMeta(UInt intNum);
1078
1079 /*!
1080 * ======== plug ========
1081 * Plug a non dispatched interrupt vector with an ISR address.
1082 *
1083 * Used internally by Hwi_create() and Hwi_construct().
1084 *
1085 * This API is provided for external use primarily to allow users
1086 * to plug the NMI vector (interrupt #2) at runtime.
1087 *
1088 * @a(Note)
1089 * Interrupt vectors plugged using Hwi_plug() are NOT managed by
1090 * the Hwi interrupt dispatcher. Consequently, it is not safe to
1091 * call SYS/BIOS APIs from within these ISRs.
1092 *
1093 * @param(intNum) interrupt number
1094 * @param(fxn) pointer to ISR function
1095 */
1096 Void plug(UInt intNum, Void *fxn);
1097
1098 /*!
1099 * ======== getHandle ========
1100 * Returns Hwi_handle associated with intNum
1101 *
1102 * @param(intNum) interrupt number
1103 */
1104 Handle getHandle(UInt intNum);
1105
1106 /*!
1107 * ======== setPriority ========
1108 * Set an interrupt's relative priority.
1109 *
1110 * Valid priorities are 0 - 255. 0 is highest priority.
1111 *
1112 * @a(WARNING)
1113 * Setting the priority of a dispatched Hwi to a value higher
1114 * than {@link #disablePriority Hwi.disablePriority} will make
1115 * it become non-maskable by {@link #disable Hwi_disable()}.
1116 * The behavior of your application after that will be
1117 * unpredictable and will likely yield catastrophic results!
1118 *
1119 * @param(intNum) ID of interrupt
1120 * @param(priority) priority
1121 */
1122 Void setPriority(UInt intNum, UInt priority);
1123
1124 /*!
1125 * ======== excSetBuffers ========
1126 * Set the exception context and stack buffer pointers
1127 *
1128 * @param(excContextBuffer) Address to place ExcContext
1129 * @param(excStackBuffer) Address to place ExcStack
1130 */
1131 Void excSetBuffers(Ptr excContextBuffer, Ptr excStackBuffer);
1132
1133 /*!
1134 * @_nodoc
1135 * ======== initNVIC ========
1136 * initialize everything but leave ints disabled
1137 */
1138 Void initNVIC();
1139
1140 /*!
1141 * @_nodoc
1142 * ======== initStacks ========
1143 * set up M3 split stacks
1144 */
1145 Void initStacks(Ptr hwiStack);
1146
1147 /*!
1148 * @_nodoc
1149 * ======== flushVnvic ========
1150 * Reconfigure a dispatched interrupt.
1151 *
1152 * Called by the internal function "Hwi_updateNvic()".
1153 *
1154 * This is a public API because it is also called by "Core_hwiFunc()".
1155 */
1156 Void flushVnvic();
1157
1158 instance:
1159
1160 /*!
1161 * Interrupt priority.
1162 * The default is 255 which is the lowest priority.
1163 *
1164 * Priority 0 is the highest priority and by default is
1165 * reserved for zero latency interrupts
1166 * (see {@link #disablePriority}).
1167 *
1168 * Valid priorities values are device dependent and their
1169 * nesting behaviors depend on the {@link #priGroup} setting.
1170 *
1171 * See the Cortex M3 architecture reference manual for details
1172 * on the meanings of these parameters.
1173 */
1174 override config Int priority = 255;
1175
1176 /*!
1177 * Interrupt Masking Option. Only MaskingOption_LOWER is supported.
1178 *
1179 * The NVIC interrupt controller is designed for priority based
1180 * interrupts. No support is provided for anything but
1181 * Hwi.MaskingOption_LOWER.
1182 */
1183 override config IHwi.MaskingOption maskSetting = IHwi.MaskingOption_LOWER;
1184
1185 /*!
1186 * Use the interrupt dispatcher with this interrupt. Default is true.
1187 *
1188 * If set to false, the interrupt dispatcher is NOT used. Instead,
1189 * the configured Hwi function address is placed directly in the
1190 * vector table, which results in the dispatcher being bypassed.
1191 *
1192 * @a(Warning)
1193 * Interrupts configured to bupass the dispatcher are not allowed
1194 * to call ANY SYS/BIOS APIs that effect thread scheduling. Examples
1195 * of API that should no be invoked are:
1196 *
1197 * @p(dlist)
1198 * - Swi_post(),
1199 * - Semaphore_post(),
1200 * - Event_post(),
1201 * - Task_yield()
1202 * @p
1203 *
1204 * Additionally, although the signature for a non-dispatched interrupt
1205 * function is the same as that for a dispatched interrupt
1206 * (see {@link #FuncPtr}), no argument is actually passed
1207 * to the non-dispatched ISR handler.
1208 */
1209 config Bool useDispatcher = true;
1210
1211 /*!
1212 * ======== reconfig ========
1213 * Reconfigure a dispatched interrupt.
1214 */
1215 Void reconfig(FuncPtr fxn, const Params *params);
1216
1217 internal:
1218
1219 /*!
1220 * If Hwi.dispatchTableSize is initialized by the user then
1221 * Hwi.numSparseInterrupts is set to the value of Hwi.dispatchTableSize
1222 *
1223 * If Hwi.dispatchTableSize is NOT set by the user, the normal
1224 * intNum-indexed Hwi dispatchTable mechanism is used by
1225 * the dispatcher to find the corresponding Hwi object.
1226 *
1227 * If Hwi.dispatchTableSize is set by the user, then a
1228 * RAM-based fixed sized interrupt jump table is generated
1229 * that contains a repeating pattern of the following 3 word
1230 * assembly code snippets:
1231 *
1232 * hwiX: ldr r3, hwiObjectX
1233 * ldr pc, ti_sysbios_family_arm_m3_Hwi_dispatch__I
1234 * hwiObjectX: .word 0
1235 * hwiY: ldr r3, hwiObjectY
1236 * ldr pc, ti_sysbios_family_arm_m3_Hwi_dispatch__I
1237 * hwiObjectY: .word 0
1238 * ...
1239 *
1240 * Each dispatched interrupt vector is then initialized to point
1241 * to one of these tuples, and the address of the corresponding Hwi
1242 * object is written into the hwiObjectX field.
1243 *
1244 * The low level assembly code in Hwi_dispatch__I preserves the
1245 * value of r3 when it calls Hwi_dispatchC(), which results in
1246 * the Hwi object being passed as the arg3.
1247 *
1248 * Depending on the boolean value of Hwi_numSparseInterrupts, the
1249 * dispatcher either uses the value passed in arg3 as the
1250 * Hwi object, or uses intNum to index into the standard
1251 * dispatchTable to fetch the Hwi object.
1252 */
1253 config UInt numSparseInterrupts = 0;
1254
1255 1256 1257 1258
1259 metaonly config Bool isTiva = false;
1260
1261 1262 1263 1264 1265 1266 1267 1268 1269
1270 metaonly config Bool enableWA1_1 = false;
1271
1272 1273 1274 1275 1276 1277
1278 config UInt (*swiDisable)();
1279 config Void (*swiRestoreHwi)(UInt);
1280 config UInt (*taskDisable)();
1281 config Void (*taskRestoreHwi)(UInt);
1282
1283
1284 config UInt32 ccr;
1285
1286 /*!
1287 * const array to hold all HookSet objects.
1288 */
1289 config HookSet hooks[length] = [];
1290
1291 1292 1293 1294
1295 Int postInit(Object *hwi, Error.Block *eb);
1296
1297 /*!
1298 * ======== updateNvic ========
1299 * Internal SMP function to cause the virtual NVIC to be flushed to the
1300 * actual NVIC.
1301 *
1302 * This function is called by the various user APIs that manipulate
1303 * individual NVIC register bits
1304 * (ie Hwi_enable/disable/restore/clearInterrupt())
1305 *
1306 * If the current core is the owner of "intNum", flushVnvic() is called
1307 * immediately.
1308 *
1309 * Otherwise an intercore interrupt is generated to force the other core
1310 * to perform the flushVnvic().
1311 *
1312 */
1313 Void updateNvic(UInt intNum);
1314
1315 /*!
1316 * ======== excHandlerAsm ========
1317 * asm code exception handler
1318 */
1319 Void excHandlerAsm();
1320
1321 /*!
1322 * ======== excHandler ========
1323 * exception Handler routes to
1324 * either min, max, or spin exception handler
1325 */
1326 Void excHandler(UInt *excStack, UInt lr);
1327
1328 /*!
1329 * ======== excHandlerMin ========
1330 * Minimal Exception Handler
1331 */
1332 Void excHandlerMin(UInt *excStack, UInt lr);
1333
1334 /*!
1335 * ======== excHandlerMax ========
1336 * Full Featured Exception Handler
1337 */
1338 Void excHandlerMax(UInt *excStack, UInt lr);
1339
1340 /*!
1341 * ======== excFillContext ========
1342 */
1343 Void excFillContext(UInt *excStack);
1344
1345 /*!
1346 * ======== excNmi ========
1347 */
1348 Void excNmi(UInt *excStack);
1349
1350 /*!
1351 * ======== excHardFault ========
1352 */
1353 Void excHardFault(UInt *excStack);
1354
1355 /*!
1356 * ======== excMemFault ========
1357 */
1358 Void excMemFault(UInt *excStack);
1359
1360 /*!
1361 * ======== excBusFault ========
1362 */
1363 Void excBusFault(UInt *excStack);
1364
1365 /*!
1366 * ======== excUsageFault ========
1367 */
1368 Void excUsageFault(UInt *excStack);
1369
1370 /*!
1371 * ======== excSvCall ========
1372 */
1373 Void excSvCall(UInt *excStack);
1374
1375 /*!
1376 * ======== excDebugMon ========
1377 */
1378 Void excDebugMon(UInt *excStack);
1379
1380 /*!
1381 * ======== excReserved ========
1382 */
1383 Void excReserved(UInt *excStack, UInt excNum);
1384
1385 /*!
1386 * ======== excNoIsr ========
1387 */
1388 Void excNoIsr(UInt *excStack, UInt excNum);
1389
1390 /*!
1391 * ======== excDumpRegs ========
1392 */
1393 Void excDumpRegs(UInt lr);
1394
1395 /*!
1396 * ======== pendSV ========
1397 * Used by dispatcher
1398 */
1399 Void pendSV();
1400
1401 /*! Hwi vector function type definition. */
1402 typedef Void (*HandlerFuncPtr)(Handle, UInt);
1403
1404
1405 Void dispatch();
1406
1407 1408 1409 1410 1411 1412
1413 Void romInitNVIC();
1414
1415 1416 1417 1418
1419 UInt dispatchC(Irp irp, UInt32 dummy1, UInt32 dummy2, Object *hwi);
1420
1421
1422 Void doSwiRestore(UInt tskKey);
1423
1424
1425 Void doTaskRestore(UInt tskKey);
1426
1427 /*! Meta World Only Hwi Configuration Object. */
1428 metaonly struct InterruptObj {
1429 String name;
1430 Bool used;
1431 Bool useDispatcher;
1432 UInt priority;
1433 FuncPtr fxn;
1434 Handle hwi;
1435 };
1436
1437 /*!
1438 * Meta-only array of interrupt objects.
1439 * This meta-only array of Hwi config objects is initialized
1440 * in Hwi.xs:module$meta$init().
1441 */
1442 metaonly config InterruptObj interrupt[];
1443
1444 struct Instance_State {
1445 UArg arg;
1446 FuncPtr fxn;
1447 Irp irp;
1448
1449 UInt8 priority;
1450 Int16 intNum;
1451
1452
1453 Ptr hookEnv[];
1454 };
1455
1456 struct Module_State {
1457 Char *taskSP;
1458
1459 Bool excActive[];
1460 ExcContext *excContext[];
1461 Ptr excStack[];
1462 Ptr isrStack;
1463 Ptr isrStackBase;
1464 Ptr isrStackSize;
1465 Ptr vectorTableBase;
1466 UInt swiTaskKeys;
1467 Ptr dispatchTable;
1468 volatile Bool vnvicFlushRequired;
1469
1470 UInt8 intAffinity[];
1471 UInt32 intAffinityMasks[][];
1472 };
1473 }