GCC Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 7.2.1

BIOS Version: bios_6_55_00_05_eng

XDCTools Version: xdctools_3_50_05_11_core_eng

Benchmark	Cycles
Interrupt Latency	152
Hwi_restore()	8
Hwi_disable()	9
Hwi dispatcher prolog	141
Hwi dispatcher epilog	239
Hwi dispatcher	371
Hardware Interrupt to Blocked Task	678
Hardware Interrupt to Software Interrupt	403
Swi_enable()	72
Swi_disable()	14
Post Software Interrupt Again	30
Post Software Interrupt without Context Switch	83
Post Software Interrupt with Context Switch	189
Create a New Task without Context Switch	3286
Set a Task Priority without a Context Switch	154
Task_yield()	287
Post Semaphore No Waiting Task	96
Post Semaphore No Task Switch	249
Post Semaphore with Task Switch	388
Pend on Semaphore No Context Switch	53
Pend on Semaphore with Task Switch	386
Clock_getTicks()	8
POSIX Create a New Task without Context Switch	6581
POSIX Set a Task Priority without a Context Switch	225
POSIX Post Semaphore No Waiting Task	107
POSIX Post Semaphore No Task Switch	262
POSIX Post Semaphore with Task Switch	401
POSIX Pend on Semaphore No Context Switch	66
POSIX Pend on Semaphore with Task Switch	397

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings:

“-mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -Dti_sysbios_Build_useHwiMacros -Dfar= -D__DYNAMIC_REENT__”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.