Instance: PKA_INT
Component: PKA_INT
Base address: 0x40027000
Integrated module which includes the PKA K
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RO |
32 |
0x0000 0102 |
0x0000 0FF8 |
0x4002 7FF8 |
|
|
RO |
32 |
0x0200 6996 |
0x0000 0FFC |
0x4002 7FFC |
| Address Offset | 0x0000 0FF8 | ||
| Physical Address | 0x4002 7FF8 | Instance | 0x4002 7FF8 |
| Description | PKA Options register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:11 | RESERVED11 | Ignore on read | RO | 0b0 0000 0000 0000 0000 0000 | ||
| 10 | AIC_PRESENT | When set to '1', indicates that an EIP201 AIC is included in the EIP150 | RO | 0 | ||
| 9 | EIP76_PRESENT | When set to '1', indicates that the EIP76 TRNG is included in the EIP150 | RO | 0 | ||
| 8 | EIP28_PRESENT | When set to '1', indicates that the EIP28 PKA is included in the EIP150 | RO | 1 | ||
| 7:4 | RESERVED4 | Ignore on read | RO | 0x0 | ||
| 3 | AXI_INTERFACE | When set to '1', indicates that the EIP150 is equipped with a AXI interface | RO | 0 | ||
| 2 | AHB_IS_ASYNC | When set to '1', indicates that AHB interface is asynchronous Only applicable when AHB_INTERFACE is 1 | RO | 0 | ||
| 1 | AHB_INTERFACE | When set to '1', indicates that the EIP150 is equipped with a AHB interface | 1 | |||
| 0 | PLB_INTERFACE | When set to '1', indicates that the EIP150 is equipped with a PLB interface | 0 | |||
| Address Offset | 0x0000 0FFC | ||
| Physical Address | 0x4002 7FFC | Instance | 0x4002 7FFC |
| Description | PKA hardware revision register This register allows the host access to the hardware revision number of the PKA engine for software driver matching and diagnostic purposes. It is always located at the highest address in the access space of the module and contains an encoding of the EIP number (with its complement as signature) for recognition of the hardware module. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RESERVED28 | These bits should be ignored on read | RO | 0x0 | ||
| 27:24 | MAJOR_REVISION | These bits encode the major version number for this module | RO | 0x2 | ||
| 23:20 | MINOR_REVISION | These bits encode the minor version number for this module | RO | 0x0 | ||
| 19:16 | PATCH_LEVEL | These bits encode the hardware patch level for this module they start at value 0 on the first release | RO | 0x0 | ||
| 15:8 | COMP_EIP_NUM | These bits simply contain the complement of bits [7:0], used by a driver to ascertain that the EIP150 revision register is indeed read | RO | 0x69 | ||
| 7:0 | EIP_NUM | These bits encode the AuthenTec EIP number for the EIP150 | RO | 0x96 | ||
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