Instance: PKA
Component: PKA
Base address: 0x40025000
Integrated module which combines the Public Key Acceleration module, optional True Random Gnerator, optional interrupt controller and a standard bus interface
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4002 5000 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4002 5004 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4002 5008 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4002 500C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x4002 5010 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x4002 5014 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4002 5018 |
|
|
RW |
32 |
0x0000 8000 |
0x0000 001C |
0x4002 501C |
|
|
RO |
32 |
0x0000 0001 |
0x0000 0020 |
0x4002 5020 |
|
|
RO |
32 |
0x0000 8000 |
0x0000 0024 |
0x4002 5024 |
|
|
RO |
32 |
0x0000 8000 |
0x0000 0028 |
0x4002 5028 |
|
|
RW |
32 |
0x0000 0100 |
0x0000 00C8 |
0x4002 50C8 |
|
|
RO |
32 |
0x0000 0020 |
0x0000 00F4 |
0x4002 50F4 |
|
|
RO |
32 |
0x2150 0000 |
0x0000 00F8 |
0x4002 50F8 |
|
|
RO |
32 |
0x0151 E31C |
0x0000 00FC |
0x4002 50FC |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x4002 5000 | Instance | 0x4002 5000 |
| Description | PKA Vector A Address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:11 | RESERVED11 | Set to zero on write, ignore on read | RW | 0b0 0000 0000 0000 0000 0000 | ||
| 10:0 | APTR | This register specifies the location of vector A within the PKA RAM. Vectors are identified through the location of their least-significant 32-bit word. Note that bit [0] must be zero to ensure that the vector starts at an 8-byte boundary. | RW | 0b000 0000 0000 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x4002 5004 | Instance | 0x4002 5004 |
| Description | PKA Vector B Address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:11 | RESERVED11 | Set to zero on write, ignore on read | RW | 0b0 0000 0000 0000 0000 0000 | ||
| 10:0 | BPTR | This register specifies the location of vector B within the PKA RAM. Vectors are identified through the location of their least-significant 32-bit word. Note that bit [0] must be zero to ensure that the vector starts at an 8-byte boundary. | RW | 0b000 0000 0000 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0x4002 5008 | Instance | 0x4002 5008 |
| Description | PKA Vector C Address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:11 | RESERVED11 | Set to zero on write, ignore on read | RW | 0b0 0000 0000 0000 0000 0000 | ||
| 10:0 | CPTR | This register specifies the location of vector C within the PKA RAM. Vectors are identified through the location of their least-significant 32-bit word. Note that bit [0] must be zero to ensure that the vector starts at an 8-byte boundary. | RW | 0b000 0000 0000 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0x4002 500C | Instance | 0x4002 500C |
| Description | PKA Vector D Address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:11 | RESERVED11 | Set to zero on write, ignore on read | RW | 0b0 0000 0000 0000 0000 0000 | ||
| 10:0 | DPTR | This register specifies the location of vector D within the PKA RAM. Vectors are identified through the location of their least-significant 32-bit word. Note that bit [0] must be zero to ensure that the vector starts at an 8-byte boundary. | RW | 0b000 0000 0000 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0x4002 5010 | Instance | 0x4002 5010 |
| Description | PKA Vector A Length During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:9 | RESERVED11 | Set to zero on write, ignore on read | RW | 0b000 0000 0000 0000 0000 0000 | ||
| 8:0 | ALENGTH | This register specifies the length (in 32-bit words) of Vector A. | RW | 0b0 0000 0000 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0x4002 5014 | Instance | 0x4002 5014 |
| Description | PKA Vector B Length During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:9 | RESERVED11 | Set to zero on write, ignore on read | RW | 0b000 0000 0000 0000 0000 0000 | ||
| 8:0 | BLENGTH | This register specifies the length (in 32-bit words) of Vector B. | RW | 0b0 0000 0000 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0x4002 5018 | Instance | 0x4002 5018 |
| Description | PKA Bit Shift Value For basic PKCP operations, modifying the contents of this register is made impossible while the operation is being performed. For the ExpMod-variable and ExpMod-CRT operations, this register is used to indicate the number of odd powers to use (directly as a value in the range 1-16). For the ModInv and ECC operations, this register is used to hold a completion code. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED11 | Set to zero on write, ignore on read | RW | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4:0 | NUM_BITS_TO_SHIFT | This register specifies the number of bits to shift the input vector (in the range 0-31) during a Rshift or Lshift operation. | RW | 0b0 0000 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0x4002 501C | Instance | 0x4002 501C |
| Description | PKA Function This register contains the control bits to start basic PKCP as well as complex sequencer operations. The run bit can be used to poll for the completion of the operation. Modifying bits [11:0] is made impossible during the execution of a basic PKCP operation. During the execution of sequencer-controlled complex operations, this register is modified, the run and stall result bits are set to zero at the conclusion, but other bits are undefined. NOTE: Continuously reading this register to poll the run bit is not allowed when executing complex sequencer operations (the sequencer cannot access the PKCP when this is done). Leave at least one sysclk cycle between poll operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:25 | RESERVED25 | Set to zero on write, ignore on read | RW | 0b000 0000 | ||
| 24 | STALL_RESULT | When written with a 1b, updating of the COMPARE bit, MSW and DIVMSW registers, as well as resetting the run bit is stalled beyond the point that a running operation is actually finished. Use this to allow software enough time to read results from a previous operation when the newly started operation is known to take only a short amount of time. If a result is waiting, the result registers is updated and the run bit is reset in the clock cycle following writing the stall result bit back to 0b. The Stall result function may only be used for basic PKCP operations. | RW | 0 | ||
| 23:16 | RESERVED16 | Set to zero on write, ignore on read | RW | 0x00 | ||
| 15 | RUN | The host sets this bit to instruct the PKA module to begin processing the basic PKCP or complex sequencer operation. This bit is reset low automatically when the operation is complete. After a reset, the run bit is always set to 1b. Depending on the option, program ROM or program RAM, the following applies: Program ROM - The first sequencer instruction sets the bit to 0b. This is done immediately after the hardware reset is released. Program RAM - The sequencer must set the bit to 0b. As a valid firmware may not have been loaded, the sequencer is held in software reset after the hardware reset is released (the SEQCTRL.RESET bit is set to 1b). After the FW image is loaded and the Reset bit is cleared, the sequencer starts to execute the FW. The first instruction clears the run bit. In both cases a few clock cycles are needed before the first instruction is executed and the run bit state has been propagated. |
RW | 1 | ||
| 14:12 | SEQUENCER_OPERATIONS | These bits select the complex sequencer operation to perform: 0x0: None 0x1: ExpMod-CRT 0x2: ECmontMUL 0x3: ECC-ADD (if available in firmware, otherwise reserved) 0x4: ExpMod-ACT2 0x5: ECC-MUL (if available in firmware, otherwise reserved) 0x6: ExpMod-variable 0x7: ModInv (if available in firmware, otherwise reserved) The encoding of these operations is determined by sequencer firmware. |
RW | 0b000 | ||
| 11 | COPY | Perform copy operation | RW | 0 | ||
| 10 | COMPARE | Perform compare operation | RW | 0 | ||
| 9 | MODULO | Perform modulo operation | RW | 0 | ||
| 8 | DIVIDE | Perform divide operation | RW | 0 | ||
| 7 | LSHIFT | Perform left shift operation | RW | 0 | ||
| 6 | RSHIFT | Perform right shift operation | RW | 0 | ||
| 5 | SUBTRACT | Perform subtract operation | RW | 0 | ||
| 4 | ADD | Perform add operation | RW | 0 | ||
| 3 | MS_ONE | Loads the location of the Most Significant one bit within the result word indicated in the MSW register into bits [4:0] of the DIVMSW.MSW_ADDRESS register - can only be used with basic PKCP operations, except for Divide, Modulo and Compare. | RW | 0 | ||
| 2 | RESERVED2 | Set to zero on write, ignore on read | RW | 0 | ||
| 1 | ADDSUB | Perform combined add/subtract operation | RW | 0 | ||
| 0 | MULTIPLY | Perform multiply operation | RW | 0 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0x4002 5020 | Instance | 0x4002 5020 |
| Description | PKA compare result This register provides the result of a basic PKCP compare operation. It is updated when the FUNCTION.RUN bit is reset at the end of that operation. Status after a complex sequencer operation is unknown |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:3 | RESERVED3 | Ignore on read | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | ||
| 2 | A_GREATER_THAN_B | Vector_A is greater than Vector_B | RO | 0 | ||
| 1 | A_LESS_THAN_B | Vector_A is less than Vector_B | RO | 0 | ||
| 0 | A_EQUALS_B | Vector_A is equal to Vector_B | RO | 1 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0x4002 5024 | Instance | 0x4002 5024 |
| Description | PKA most-significant-word of result vector This register indicates the (word) address in the PKA RAM where the most significant nonzero 32-bit word of the result is stored. Should be ignored for modulo operations. For basic PKCP operations, this register is updated FUNCTION.RUN bit is reset at the end of the operation. For the complex-sequencer controlled operations, updating of the final value matching the actual result is done near the end of the operation; note that the result is only meaningful if no errors were detected and that for ECC operations, this register will provide information for the x-coordinate of the result point only. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Ignore on read | RO | 0x0000 | ||
| 15 | RESULT_IS_ZERO | The result vector is all zeroes, ignore the address returned in bits [10:0] | RO | 1 | ||
| 14:11 | RESERVED11 | Ignore on read | RO | 0x0 | ||
| 10:0 | MSW_ADDRESS | Address of the most-significant nonzero 32-bit word of the result vector in PKA RAM | RO | 0b000 0000 0000 | ||
| Address Offset | 0x0000 0028 | ||
| Physical Address | 0x4002 5028 | Instance | 0x4002 5028 |
| Description | PKA most-significant-word of divide remainder This register indicates the (32-bit word) address in the PKA RAM where the most significant nonzero 32-bit word of the remainder result for the basic divide and modulo operations is stored. Bits [4:0] are loaded with the bit number of the most-significant nonzero bit in the most-significant nonzero word when MS one control bit is set. For divide, modulo, and MS one reporting, this register is updated when FUNCTION.RUN bit is reset at the end of the operation. For the complex sequencer controlled operations, updating of bits [4:0] of this register with the most-significant bit location of the actual result is done near the end of the operation. The result is meaningful only if no errors were detected and that for ECC operations; this register provides information for the x-coordinate of the result point only. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Ignore on read | RO | 0x0000 | ||
| 15 | RESULT_IS_ZERO | The result vector is all zeroes, ignore the address returned in bits [10:0] | RO | 1 | ||
| 14:11 | RESERVED11 | Ignore on read | RO | 0x0 | ||
| 10:0 | MSW_ADDRESS | Address of the most significant nonzero 32-bit word of the remainder result vector in PKA RAM | RO | 0b000 0000 0000 | ||
| Address Offset | 0x0000 00C8 | ||
| Physical Address | 0x4002 50C8 | Instance | 0x4002 50C8 |
| Description | PKA sequencer control and status register The sequencer is interfaced with the outside world through a single control and status register. With the exception of bit [31], the actual use of bits in the separate sub-fields of this register is determined by the sequencer firmware. This register need only be accessed when the sequencer program is stored in RAM. The reset value of the RESET bit depends upon the option chosen for sequencer program storage. NOTE: For Agama the sequencer firmware is executed from ROM. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | RESET | Option program ROM: Reset value = 0. Read/Write, reset value 0b (ZERO). Writing 1b resets the sequencer, write to 0b to restart operations again. As the reset value is 0b, the sequencer will automatically start operations executing from program ROM. This bit should always be written with zero and ignored when reading this register. Option Program RAM: Reset value =1. Read/Write, reset value 1b (ONE). When 1b, the sequencer is held in a reset state and the PKA_PROGRAM area is accessible for loading the sequencer program (while the PKA_DATA_RAM is inaccessible), write to 0b to (re)start sequencer operations and disable PKA_PROGRAM area accessibility (also enables the PKA_DATA_RAM accesses). Resetting the sequencer (in order to load other firmware) should only be done when the PKA Engine is not performing any operations (i.e. the FUNCTION.RUN bit should be zero). |
RW | 0 | ||
| 30:16 | RESERVED16 | Set to zero on write, ignore on read | RW | 0b000 0000 0000 0000 | ||
| 15:8 | SEQUENCER_STAT | These read-only bits can be used by the sequencer to communicate status to the outside world. Bit [8] is also used as sequencer interrupt, with the complement of this bit ORed into the FUNCTION.RUN bit. This field should always be written with zeroes and ignored when reading this register. | RO | 0x01 | ||
| 7:0 | SW_CONTROL_STAT | These bits can be used by software to trigger sequencer operations. External logic can set these bits by writing 1b, cannot reset them by writing 0b. The sequencer can reset these bits by writing 0b, cannot set them by writing 1b. Setting the FUNCTION.RUN bit together with a nonzero sequencer operations field automatically sets bit [0] here. This field should always be written with zeroes and ignored when reading this register. | RW | 0x00 | ||
| Address Offset | 0x0000 00F4 | ||
| Physical Address | 0x4002 50F4 | Instance | 0x4002 50F4 |
| Description | PKA hardware options register This register provides the host with a means to determine the hardware configuration implemented in this PKA engine, focused on options that have an effect on software interacting with the module. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:12 | RESERVED12 | Ignore on read | RO | 0x0 0000 | ||
| 11 | INT_MASKING | Interrupt Masking 0x0: indicates that the main interrupt output (bit [1] of the interrupts output bus) is the direct complement of the run bit in the PKA_CONTROL register, 0x1 : indicates that interrupt masking logic is present for this output. Note: Reset value is undefined |
RO | 0 | ||
| 10:8 | PROTECTION_OPTION | Protection Option 0x0: indicates no additional protection against side channel attacks, 0x1: indicates the SCAP option 0x2: Reserved 0x3: indicates the PROT option; Note: Reset value is undefined |
RO | 0b000 | ||
| 7 | PROGRAM_RAM | Program RAM 0x1: indicates sequencer program storage in RAM, 0x0: indicates sequencer program storage in ROM. Note: Reset value is undefined |
RO | 0 | ||
| 6:5 | SEQUENCER_CONFIGURATION | Sequencer Configuration 0x0: Reserved 0x1 : Indicates a standard sequencer 0x2: Reserved 0x3: Reserved | RO | 0b01 | ||
| 4:2 | RESERVED2 | Ignore on read | RO | 0b000 | ||
| 1:0 | PKCP_CONFIGURATION | PKCP Configuration 0x0 : Reserved 0x1 : Indicates a PKCP with a 16x16 multiplier, 0x2: indicates a PKCP with a 32x32 multiplier, 0x3 : Reserved Note: Reset value is undefined. |
RO | 0b00 | ||
| Address Offset | 0x0000 00F8 | ||
| Physical Address | 0x4002 50F8 | Instance | 0x4002 50F8 |
| Description | PKA firmware revision and capabilities register This register allows the host access to the internal firmware revision number of the PKA Engine for software driver matching and diagnostic purposes. This register also contains a field that encodes the capabilities of the embedded firmware. This register is written by the firmware within a few clock cycles after starting up that firmware. The hardware reset value is zero, indicating that the information has not been written yet. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | FW_CAPABILITIES | Firmware Capabilities 4-bit binary encoding for the functionality implemented in the firmware. 0x0: indicates basic ModExp with/without CRT. 0x1: adds Modular Inversion, 0x2: value 2 adds Modular Inversion and ECC operations. 0x3-0xF : Reserved. | RO | 0x2 | ||
| 27:24 | MAJOR_FW_REVISION | 4-bit binary encoding of the major firmware revision number | RO | 0x1 | ||
| 23:20 | MINOR_FW_REVISION | 4-bit binary encoding of the minor firmware revision number | RO | 0x5 | ||
| 19:16 | FW_PATCH_LEVEL | 4-bit binary encoding of the firmware patch level, initial release will carry value zero Patches are used to remove bugs without changing the functionality or interface of a module. |
RO | 0x0 | ||
| 15:0 | RESERVED0 | Ignore on read | RO | 0x0000 | ||
| Address Offset | 0x0000 00FC | ||
| Physical Address | 0x4002 50FC | Instance | 0x4002 50FC |
| Description | PKA hardware revision register This register allows the host access to the hardware revision number of the PKA engine for software driver matching and diagnostic purposes. It is always located at the highest address in the access space of the module and contains an encoding of the EIP number (with its complement as signature) for recognition of the hardware module. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RESERVED28 | Ignore on read | RO | 0x0 | ||
| 27:24 | MAJOR_HW_REVISION | 4-bit binary encoding of the major hardware revision number | RO | 0x1 | ||
| 23:20 | MINOR_HW_REVISION | 4-bit binary encoding of the minor hardware revision number | RO | 0x5 | ||
| 19:16 | HW_PATCH_LEVEL | 4-bit binary encoding of the hardware patch level, initial release will carry value zero Patches are used to remove bugs without changing the functionality or interface of a module. |
RO | 0x1 | ||
| 15:8 | COMPLEMENT_OF_BASIC_EIP_NUMBER | Bit-by-bit logic complement of bits [7:0], EIP-28 gives 0xE3 | RO | 0xE3 | ||
| 7:0 | BASIC_EIP_NUMBER | 8-bit binary encoding of the EIP number, EIP-28 gives 0x1C | RO | 0x1C | ||
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