Instance: CRYPTO
Component: CRYPTO
Base address: 0x40024000
DMA Crypto Core is a low power low gate count crypto core with DMA capability and local key storage.
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4002 4000 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4002 4004 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4002 400C |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0018 |
0x4002 4018 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 001C |
0x4002 401C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x4002 4020 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4002 4024 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x4002 402C |
|
|
RW |
32 |
0x0000 2400 |
0x0000 0078 |
0x4002 4078 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 007C |
0x4002 407C |
|
|
RO |
32 |
0x0101 2ED1 |
0x0000 00FC |
0x4002 40FC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0400 |
0x4002 4400 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0404 |
0x4002 4404 |
|
|
RW |
32 |
0x0000 0001 |
0x0000 0408 |
0x4002 4408 |
|
|
RW |
32 |
0x0000 0008 |
0x0000 040C |
0x4002 440C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0500 - 0x0000 050C |
0x4002 4500 - 0x4002 450C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0510 - 0x0000 051C |
0x4002 4510 - 0x4002 451C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0540 - 0x0000 054C |
0x4002 4540 - 0x4002 454C |
|
|
RW |
32 |
0x8000 0000 |
0x0000 0550 |
0x4002 4550 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0554 |
0x4002 4554 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0558 |
0x4002 4558 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 055C |
0x4002 455C |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0560 |
0x4002 4560 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0560 |
0x4002 4560 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0564 |
0x4002 4564 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0564 |
0x4002 4564 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0568 |
0x4002 4568 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0568 |
0x4002 4568 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 056C |
0x4002 456C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 056C |
0x4002 456C |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0570 - 0x0000 057C |
0x4002 4570 - 0x4002 457C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0604 |
0x4002 4604 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0608 |
0x4002 4608 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 060C |
0x4002 460C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0610 |
0x4002 4610 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0614 |
0x4002 4614 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0618 |
0x4002 4618 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 061C |
0x4002 461C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0620 |
0x4002 4620 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0624 |
0x4002 4624 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0628 |
0x4002 4628 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 062C |
0x4002 462C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0630 |
0x4002 4630 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0634 |
0x4002 4634 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0638 |
0x4002 4638 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 063C |
0x4002 463C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0640 |
0x4002 4640 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0644 |
0x4002 4644 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0648 |
0x4002 4648 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 064C |
0x4002 464C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0650 |
0x4002 4650 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0654 |
0x4002 4654 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0658 |
0x4002 4658 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 065C |
0x4002 465C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0660 |
0x4002 4660 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0664 |
0x4002 4664 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0668 |
0x4002 4668 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 066C |
0x4002 466C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0670 |
0x4002 4670 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0674 |
0x4002 4674 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0678 |
0x4002 4678 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 067C |
0x4002 467C |
|
|
RW |
32 |
0x0000 0004 |
0x0000 0680 |
0x4002 4680 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0684 |
0x4002 4684 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0688 |
0x4002 4688 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 068C |
0x4002 468C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06C0 |
0x4002 46C0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06C4 |
0x4002 46C4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06C8 |
0x4002 46C8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06CC |
0x4002 46CC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06D0 |
0x4002 46D0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06D4 |
0x4002 46D4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06D8 |
0x4002 46D8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06DC |
0x4002 46DC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06E0 |
0x4002 46E0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06E4 |
0x4002 46E4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06E8 |
0x4002 46E8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06EC |
0x4002 46EC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06F0 |
0x4002 46F0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06F4 |
0x4002 46F4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06F8 |
0x4002 46F8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 06FC |
0x4002 46FC |
|
|
RW |
32 |
0b0000 0000 0000 0000 0000 0000 0000 X000 |
0x0000 0700 |
0x4002 4700 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0704 |
0x4002 4704 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0740 |
0x4002 4740 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0780 |
0x4002 4780 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0784 |
0x4002 4784 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0788 |
0x4002 4788 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 078C |
0x4002 478C |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0790 |
0x4002 4790 |
|
|
RO |
32 |
0x9200 8778 |
0x0000 07FC |
0x4002 47FC |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x4002 4000 | Instance | 0x4002 4000 |
| Description | Channel 0 Control This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | PRIO | Channel priority 0: Low 1: High If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests. |
RW | 0 | ||
| 0 | EN | Channel enable 0: Disabled 1: Enable Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested. |
RW | 0 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x4002 4004 | Instance | 0x4002 4004 |
| Description | Channel 0 External Address | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ADDR | Channel external address value When read during operation, it holds the last updated external address after being sent to the master interface. Note: The crypto DMA copies out upto 3 bytes until it hits a word boundary, thus the address need not be word aligned. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0x4002 400C | Instance | 0x4002 400C |
| Description | Channel 0 DMA Length | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0000 | ||
| 15:0 | DMALEN | Channel DMA length in bytes During configuration, this register contains the DMA transfer length in bytes. During operation, it contains the last updated value of the DMA transfer length after being sent to the master interface. Note: Setting this register to a nonzero value starts the transfer if the channel is enabled. Therefore, this register must be written last when setting up a DMA channel. |
RW | 0x0000 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0x4002 4018 | Instance | 0x4002 4018 |
| Description | DMAC Status This register provides the actual state of each DMA channel. It also reports port errors in case these were received by the master interface module during the data transfer. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||
| 17 | PORT_ERR | Reflects possible transfer errors on the AHB port. | RO | 0 | ||
| 16:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 | ||
| 1 | CH1_ACT | A value of 1 indicates that channel 1 is active (DMA transfer on-going). | RO | 0 | ||
| 0 | CH0_ACT | A value of 1 indicates that channel 0 is active (DMA transfer on-going). | RO | 0 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0x4002 401C | Instance | 0x4002 401C |
| Description | DMAC Software Reset Software reset is used to reset the DMAC to stop all transfers and clears the port error status register. After the software reset is performed, all the channels are disabled and no new requests are performed by the channels. The DMAC waits for the existing (active) requests to finish and accordingly sets the DMASTAT. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | SWRES | Software reset enable 0 : Disabled 1 : Enabled (self-cleared to 0) Completion of the software reset must be checked through the DMASTAT |
WO | 0 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0x4002 4020 | Instance | 0x4002 4020 |
| Description | Channel 1 Control This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | PRIO | Channel priority 0: Low 1: High If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests. |
RW | 0 | ||
| 0 | EN | Channel enable 0: Disabled 1: Enable Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested. |
RW | 0 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0x4002 4024 | Instance | 0x4002 4024 |
| Description | Channel 1 External Address | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ADDR | Channel external address value. When read during operation, it holds the last updated external address after being sent to the master interface. Note: The crypto DMA copies out upto 3 bytes until it hits a word boundary, thus the address need not be word aligned. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 002C | ||
| Physical Address | 0x4002 402C | Instance | 0x4002 402C |
| Description | Channel 1 DMA Length | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0000 | ||
| 15:0 | DMALEN | Channel DMA length in bytes. During configuration, this register contains the DMA transfer length in bytes. During operation, it contains the last updated value of the DMA transfer length after being sent to the master interface. Note: Setting this register to a nonzero value starts the transfer if the channel is enabled. Therefore, this register must be written last when setting up a DMA channel. |
RW | 0x0000 | ||
| Address Offset | 0x0000 0078 | ||
| Physical Address | 0x4002 4078 | Instance | 0x4002 4078 |
| Description | DMAC Master Run-time Parameters This register defines all the run-time parameters for the AHB master interface port. These parameters are required for the proper functioning of the EIP-101m AHB master adapter. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0000 | ||||||||||||||||||||
| 15:12 | AHB_MST1_BURST_SIZE | Maximum burst size that can be performed on the AHB bus
|
RW | 0x2 | ||||||||||||||||||||
| 11 | AHB_MST1_IDLE_EN | Idle insertion between consecutive burst transfers on AHB
|
RW | 0 | ||||||||||||||||||||
| 10 | AHB_MST1_INCR_EN | Burst length type of AHB transfer
|
RW | 1 | ||||||||||||||||||||
| 9 | AHB_MST1_LOCK_EN | Locked transform on AHB
|
RW | 0 | ||||||||||||||||||||
| 8 | AHB_MST1_BIGEND | Endianess for the AHB master
|
RW | 0 | ||||||||||||||||||||
| 7:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 | ||||||||||||||||||||
| Address Offset | 0x0000 007C | ||
| Physical Address | 0x4002 407C | Instance | 0x4002 407C |
| Description | DMAC Port Error Raw Status This register provides the actual status of individual port errors. It also indicates which channel is serviced by an external AHB port (which is frozen by a port error). A port error aborts operations on all serviced channels (channel enable bit is forced to 0) and prevents further transfers via that port until the error is cleared by writing to the DMASWRESET register. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 | ||
| 12 | PORT1_AHB_ERROR | A value of 1 indicates that the EIP-101 has detected an AHB bus error | RO | 0 | ||
| 11:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 9 | PORT1_CHANNEL | Indicates which channel has serviced last (channel 0 or channel 1) by AHB master port. | RO | 0 | ||
| 8:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 | ||
| Address Offset | 0x0000 00FC | ||
| Physical Address | 0x4002 40FC | Instance | 0x4002 40FC |
| Description | DMAC Version This register contains an indication (or signature) of the EIP type of this DMAC, as well as the hardware version/patch numbers. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RESERVED28 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 27:24 | HW_MAJOR_VERSION | Major version number | RO | 0x1 | ||
| 23:20 | HW_MINOR_VERSION | Minor version number | RO | 0x0 | ||
| 19:16 | HW_PATCH_LEVEL | Patch level Starts at 0 at first delivery of this version |
RO | 0x1 | ||
| 15:8 | EIP_NUMBER_COMPL | Bit-by-bit complement of the EIP_NUMBER field bits. | RO | 0x2E | ||
| 7:0 | EIP_NUMBER | Binary encoding of the EIP-number of this DMA controller (209) | RO | 0xD1 | ||
| Address Offset | 0x0000 0400 | ||
| Physical Address | 0x4002 4400 | Instance | 0x4002 4400 |
| Description | Key Store Write Area This register defines where the keys should be written in the key store RAM. After writing this register, the key store module is ready to receive the keys through a DMA operation. In case the key data transfer triggered an error in the key store, the error will be available in the interrupt status register after the DMA is finished. The key store write-error is asserted when the programmed/selected area is not completely written. This error is also asserted when the DMA operation writes to ram areas that are not selected. The key store RAM is divided into 8 areas of 128 bits. 192-bit keys written in the key store RAM should start on boundaries of 256 bits. This means that writing a 192-bit key to the key store RAM must be done by writing 256 bits of data with the 64 most-significant bits set to 0. These bits are ignored by the AES engine. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 0000 | |||||||||||
| 7 | RAM_AREA7 | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA7 is not selected to be written. 1: RAM_AREA7 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
|
RW | 0 | |||||||||||
| 6 | RAM_AREA6 | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA6 is not selected to be written. 1: RAM_AREA6 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
|
RW | 0 | |||||||||||
| 5 | RAM_AREA5 | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA5 is not selected to be written. 1: RAM_AREA5 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
|
RW | 0 | |||||||||||
| 4 | RAM_AREA4 | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA4 is not selected to be written. 1: RAM_AREA4 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
|
RW | 0 | |||||||||||
| 3 | RAM_AREA3 | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA3 is not selected to be written. 1: RAM_AREA3 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
|
RW | 0 | |||||||||||
| 2 | RAM_AREA2 | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA2 is not selected to be written. 1: RAM_AREA2 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
|
RW | 0 | |||||||||||
| 1 | RAM_AREA1 | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA1 is not selected to be written. 1: RAM_AREA1 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
|
RW | 0 | |||||||||||
| 0 | RAM_AREA0 | Each RAM_AREAx represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written 0: RAM_AREA0 is not selected to be written. 1: RAM_AREA0 is selected to be written. Writing to multiple RAM locations is possible only when the selected RAM areas are sequential. Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 0404 | ||
| Physical Address | 0x4002 4404 | Instance | 0x4002 4404 |
| Description | Key Store Written Area This register shows which areas of the key store RAM contain valid written keys. When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first. This can be done by writing this register before the new key is written to the key store memory. Attempting to write to a key area that already contains a valid key is not allowed and results in an error. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 0000 | |||||||||||
| 7 | RAM_AREA_WRITTEN7 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
|
RW | 0 | |||||||||||
| 6 | RAM_AREA_WRITTEN6 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
|
RW | 0 | |||||||||||
| 5 | RAM_AREA_WRITTEN5 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
|
RW | 0 | |||||||||||
| 4 | RAM_AREA_WRITTEN4 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
|
RW | 0 | |||||||||||
| 3 | RAM_AREA_WRITTEN3 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
|
RW | 0 | |||||||||||
| 2 | RAM_AREA_WRITTEN2 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
|
RW | 0 | |||||||||||
| 1 | RAM_AREA_WRITTEN1 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
|
RW | 0 | |||||||||||
| 0 | RAM_AREA_WRITTEN0 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory. |
RW | 0 | |||||||||||
| Address Offset | 0x0000 0408 | ||
| Physical Address | 0x4002 4408 | Instance | 0x4002 4408 |
| Description | Key Store Size This register defines the size of the keys that are written with DMA. This register should be configured before writing to the KEY_STORE_WRITE_AREA register. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||||||||||||||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||||||||||||||
| 1:0 | SIZE | Key size: 00: Reserved When writing this to this register, the KEY_STORE_WRITTEN_AREA register is reset.
|
RW | 0b01 | ||||||||||||||
| Address Offset | 0x0000 040C | ||
| Physical Address | 0x4002 440C | Instance | 0x4002 440C |
| Description | Key Store Read Area This register selects the key store RAM area from where the key needs to be read that will be used for an AES operation. The operation directly starts after writing this register. When the operation is finished, the status of the key store read operation is available in the interrupt status register. Key store read error is asserted when a RAM area is selected which does not contain valid written key. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||
| 31 | BUSY | Key store operation busy status flag (read only): 0: Operation is complete. 1: Operation is not completed and the key store is busy. |
RO | 0 | ||||||||||||||||||||||||||||||||
| 30:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||
| 3:0 | RAM_AREA | Selects the area of the key store RAM from where the key needs to be read that will be writen to the AES engine RAM_AREA: RAM areas RAM_AREA0, RAM_AREA2, RAM_AREA4 and RAM_AREA6 are the only valid read areas for 192 and 256 bits key sizes. Only RAM areas that contain valid written keys can be selected.
|
RW | 0x8 | ||||||||||||||||||||||||||||||||
| Address Offset | 0x0000 0500 - 0x0000 050C | ||
| Physical Address | 0x4002 4500 - 0x4002 450C | Instance | 0x4002 4500 - 0x4002 450C |
| Description | AES_KEY2_0 / AES_GHASH_H_IN_0 Second Key / GHASH Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | AES_KEY2 | AES_KEY2/AES_GHASH_H[31:0] For GCM: -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these registers. Only used for modes that use the GHASH function (GCM). -[255:128] - This register is used to store intermediate values and is initialized with 0s when loading a new key. For CCM: -[255:0] - This register is used to store intermediate values. For CBC-MAC: -[255:0] - ZEROES - This register must remain 0. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0510 - 0x0000 051C | ||
| Physical Address | 0x4002 4510 - 0x4002 451C | Instance | 0x4002 4510 - 0x4002 451C |
| Description | AES_KEY3_0 / AES_KEY2_4 Third Key / Second Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | AES_KEY3 | AES_KEY3[31:0]/AES_KEY2[159:128] For GCM: -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these registers. Only used for modes that use the GHASH function (GCM). -[255:128] - This register is used to store intermediate values and is initialized with 0s when loading a new key. For CCM: -[255:0] - This register is used to store intermediate values. For CBC-MAC: -[255:0] - ZEROES - This register must remain 0. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0540 - 0x0000 054C | ||
| Physical Address | 0x4002 4540 - 0x4002 454C | Instance | 0x4002 4540 - 0x4002 454C |
| Description | AES initialization vector registers These registers are used to provide and read the IV from the AES engine. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | AES_IV | AES_IV[31:0] Initialization vector Used for regular non-ECB modes (CBC/CTR): -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers must be written with a new 128-bit IV. After an operation, these registers contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode is selected, this value is incremented with 0x1: After first use - When a new data block is submitted to the engine For GCM: -[127:0] - AES_IV - For GCM operations, these registers must be written with a new 128-bit IV. After an operation, these registers contain the updated 128-bit result IV, generated by the EIP-120t. Note that bits [127:96] of the IV represent the initial counter value (which is 1 for GCM) and must therefore be initialized to 0x01000000. This value is incremented with 0x1: After first use - When a new data block is submitted to the engine. For CCM: -[127:0] - A0: For CCM this field must be written with value A0, this value is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and counter value. 'L' must be a copy from the 'L' value of the AES_CTRL register. This 'L' indicates the width of the Nonce and counter. The loaded counter must be initialized to 0. The total width of A0 is 128-bit. For CBC-MAC: -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the start of each operation. After an operation, these registers contain the 128-bit TAG output, generated by the EIP-120t. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0550 | ||
| Physical Address | 0x4002 4550 | Instance | 0x4002 4550 |
| Description | AES Control AES input/output buffer control and mode register This register specifies the AES mode of operation for the EIP-120t. Electronic codebook (ECB) mode is automatically selected if bits [28:5] of this register are all 0. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||||||||
| 31 | CONTEXT_READY | If 1, this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context. | RO | 1 | |||||||||||||||||
| 30 | SAVED_CONTEXT_RDY | If 1, this status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the host to retrieve. This bit is only asserted if the save_context bit is set to 1. The bit is mutual exclusive with the context_ready bit. Writing one clears the bit to 0, indicating the AES core can start its next operation. This bit is also cleared when the 4th word of the output TAG and/or IV is read. Note: All other mode bit writes are ignored when this mode bit is written with 1. Note: This bit is controlled automatically by the EIP-120t for TAG read DMA operations. |
RW | 0 | |||||||||||||||||
| 29 | SAVE_CONTEXT | This bit indicates that an authentication TAG or result IV needs to be stored as a result context. Typically this bit must be set for authentication modes returning a TAG (CBC-MAC, GCM and CCM), or for basic encryption modes that require future continuation with the current result IV. If this bit is set, the engine retains its full context until the TAG and/or IV registers are read. The TAG or IV must be read before the AES engine can start a new operation. |
RW | 0 | |||||||||||||||||
| 28:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0 | |||||||||||||||||
| 24:22 | CCM_M | Defines M, which indicates the length of the authentication field for CCM operations; the authentication field length equals two times (the value of CCM-M plus one). Note: The EIP-120t always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported. |
RW | 0b000 | |||||||||||||||||
| 21:19 | CCM_L | Defines L, which indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one. All values are supported. | RW | 0b000 | |||||||||||||||||
| 18 | CCM | If set to 1, AES-CCM is selected AES-CCM is a combined mode, using AES for authentication and encryption. Note: Selecting AES-CCM mode requires writing of the AAD length register after all other registers. Note: The CTR mode bit in this register must also be set to 1 to enable AES-CTR; selecting other AES modes than CTR mode is invalid. |
RW | 0 | |||||||||||||||||
| 17:16 | GCM | Set these bits to 11 to select AES-GCM mode. AES-GCM is a combined mode, using the Galois field multiplier GF(2 to the power of 128) for authentication and AES-CTR mode for encryption. Note: The CTR mode bit in this register must also be set to 1 to enable AES-CTR Bit combination description: 00 = No GCM mode 01 = Reserved, do not select 10 = Reserved, do not select 11 = Autonomous GHASH (both H- and Y0-encrypted calculated internally) Note: The EIP-120t-1 configuration only supports mode 11 (autonomous GHASH), other GCM modes are not allowed. |
RW | 0b00 | |||||||||||||||||
| 15 | CBC_MAC | Set to 1 to select AES-CBC MAC mode. The direction bit must be set to 1 for this mode. Selecting this mode requires writing the length register after all other registers. |
RW | 0 | |||||||||||||||||
| 14:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 | |||||||||||||||||
| 8:7 | CTR_WIDTH | Specifies the counter width for AES-CTR mode 00 = 32-bit counter 01 = 64-bit counter 10 = 96-bit counter 11 = 128-bit counter
|
RW | 0b00 | |||||||||||||||||
| 6 | CTR | If set to 1, AES counter mode (CTR) is selected. Note: This bit must also be set for GCM and CCM, when encryption/decryption is required. |
RW | 0 | |||||||||||||||||
| 5 | CBC | If set to 1, cipher-block-chaining (CBC) mode is selected. | RW | 0 | |||||||||||||||||
| 4:3 | KEY_SIZE | This read-only field specifies the key size. The key size is automatically configured when a new key is loaded through the key store module. 00 = N/A - Reserved 01 = 128-bit 10 = 192-bit 11 = 256-bit |
RO | 0b00 | |||||||||||||||||
| 2 | DIR | If set to 1 an encrypt operation is performed. If set to 0 a decrypt operation is performed. This bit must be written with a 1 when CBC-MAC is selected. |
RW | 0 | |||||||||||||||||
| 1 | INPUT_READY | If 1, this status bit indicates that the 16-byte AES input buffer is empty. The host is permitted to write the next block of data. Writing 0 clears the bit to 0 and indicates that the AES core can use the provided input data block. Writing 1 to this bit is ignored. Note: For DMA operations, this bit is automatically controlled by the EIP-120t. After reset, this bit is 0. After writing a context, this bit becomes 1. |
RW | 0 | |||||||||||||||||
| 0 | OUTPUT_READY | If 1, this status bit indicates that an AES output block is available to be retrieved by the host. Writing 0 clears the bit to 0 and indicates that output data is read by the host. The AES core can provide a next output data block. Writing 1 to this bit is ignored. Note: For DMA operations, this bit is automatically controlled by the EIP-120t. |
RW | 0 | |||||||||||||||||
| Address Offset | 0x0000 0554 | ||
| Physical Address | 0x4002 4554 | Instance | 0x4002 4554 |
| Description | AES Crypto Length 0 (LSW) These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM, and CCM) no (new) data requests are done if the length decrements to or equals 0. It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written. When writing a new mode without writing the length registers, the length register values from the previous context is reused. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | C_LENGTH | C_LENGTH[31:0] Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to 0. Data lengths up to (261: 1) bytes are allowed. For GCM, any value up to 236 - 32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 - 2, resulting in a maximum number of bytes of 236 - 32. A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note: For the combined modes (GCM and CCM), this length does not include the authentication only data; the authentication length is specified in the AESAUTHLEN register All modes must have a length greater than 0. For the combined modes, it is allowed to have one of the lengths equal to 0. For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program zero to the length field; in that case the length is assumed infinite. All data must be byte (8-bit) aligned for stream cipher modes; bit aligned data streams are not supported by the EIP-120t. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes. For a host read operation, these registers return all-0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0558 | ||
| Physical Address | 0x4002 4558 | Instance | 0x4002 4558 |
| Description | AES Crypto Length 1 (MSW) These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM and CCM) no (new) data requests are done if the length decrements to or equals 0. It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written. When writing a new mode without writing the length registers, the length register values from the previous context is reused. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0b000 | ||
| 28:0 | C_LENGTH | C_LENGTH[60:32] Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to 0. Data lengths up to (261: 1) bytes are allowed. For GCM, any value up to 236 - 32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 - 2, resulting in a maximum number of bytes of 236 - 32. A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note: For the combined modes (GCM and CCM), this length does not include the authentication only data; the authentication length is specified in the AESAUTHLEN register All modes must have a length greater than 0. For the combined modes, it is allowed to have one of the lengths equal to 0. For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program zero to the length field; in that case the length is assumed infinite. All data must be byte (8-bit) aligned for stream cipher modes; bit aligned data streams are not supported by the EIP-120t. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes. For a host read operation, these registers return all-0s. |
WO | 0b0 0000 0000 0000 0000 0000 0000 0000 | ||
| Address Offset | 0x0000 055C | ||
| Physical Address | 0x4002 455C | Instance | 0x4002 455C |
| Description | AES Authentication Length | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | AUTH_LENGTH | Bits [31:0] of the authentication length register store the authentication data length in bytes for combined modes only (GCM or CCM). Supported AAD-lengths for CCM are from 0 to (2^16 - 2^8) bytes. For GCM any value up to (2^32 - 1) bytes can be used. Once processing with this context is started, this length decrements to 0. A write to this register triggers the engine to start using this context for GCM and CCM. For a host read operation, these registers return all-0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0560 | ||
| Physical Address | 0x4002 4560 | Instance | 0x4002 4560 |
| Description | Data Input/Output | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | DATA | Data register 0 for output block data from the Crypto peripheral. These bits = AES Output Data[31:0] of {127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0560 | ||
| Physical Address | 0x4002 4560 | Instance | 0x4002 4560 |
| Description | AES Data Input_Output 0 The data registers are typically accessed through the DMA and not with host writes and/or reads. However, for debugging purposes the data input/output registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | AES_DATA_IN_OUT | AES input data[31:0] / AES output data[31:0] Data registers for input/output block data to/from the EIP-120t. For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register. For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0564 | ||
| Physical Address | 0x4002 4564 | Instance | 0x4002 4564 |
| Description | Data Input/Output | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | DATA | Data register 0 for output block data from the Crypto peripheral. These bits = AES Output Data[31:0] of {127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0564 | ||
| Physical Address | 0x4002 4564 | Instance | 0x4002 4564 |
| Description | AES Data Input_Output 0 The data registers are typically accessed through the DMA and not with host writes and/or reads. However, for debugging purposes the data input/output registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | AES_DATA_IN_OUT | AES input data[31:0] / AES output data[63:32] Data registers for input/output block data to/from the EIP-120t. For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register. For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0568 | ||
| Physical Address | 0x4002 4568 | Instance | 0x4002 4568 |
| Description | Data Input/Output | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | DATA | Data register 0 for output block data from the Crypto peripheral. These bits = AES Output Data[31:0] of {127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0568 | ||
| Physical Address | 0x4002 4568 | Instance | 0x4002 4568 |
| Description | AES Data Input_Output 2 The data registers are typically accessed via DMA and not with host writes and/or reads. However, for debugging purposes the Data Input/Output Registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | AES_DATA_IN_OUT | AES input data[95:64] / AES output data[95:64] Data registers for input/output block data to/from the EIP-120t. For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register. For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 056C | ||
| Physical Address | 0x4002 456C | Instance | 0x4002 456C |
| Description | Data Input/Output | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | DATA | Data register 0 for output block data from the Crypto peripheral. These bits = AES Output Data[31:0] of {127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
RO | 0x0000 0000 | ||
| Address Offset | 0x0000 056C | ||
| Physical Address | 0x4002 456C | Instance | 0x4002 456C |
| Description | AES Data Input_Output 3 The data registers are typically accessed via DMA and not with host writes and/or reads. However, for debugging purposes the Data Input/Output Registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | AES_DATA_IN_OUT | AES input data[127:96] / AES output data[127:96] Data registers for input/output block data to/from the EIP-120t. For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register. For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0570 - 0x0000 057C | ||
| Physical Address | 0x4002 4570 - 0x4002 457C | Instance | 0x4002 4570 - 0x4002 457C |
| Description | AES Tag Out 0 The tag registers can be accessed via DMA or directly with host reads. These registers buffer the TAG from the EIP-120t. The registers are shared with the intermediate authentication result registers, but cannot be read until the processing is finished. While processing, a read from these registers returns 0s. If an operation does not return a TAG, reading from these registers returns an IV. If an operation returns a TAG plus an IV and both need to be read by the host, the host must first read the TAG followed by the IV. Reading these in reverse order will return the IV twice. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | AES_TAG | AES_TAG[31:0] Bits [31:0] of this register stores the authentication value for the combined and authentication only modes. For a host read operation, these registers contain the last 128-bit TAG output of the EIP-120t; the TAG is available until the next context is written. This register will only contain valid data if the TAG is available and when the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for operations/modes that do not return a TAG, reads from this register return data from the IV register. |
RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0604 | ||
| Physical Address | 0x4002 4604 | Instance | 0x4002 4604 |
| Description | HASH Data Input 1 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[63:32] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0608 | ||
| Physical Address | 0x4002 4608 | Instance | 0x4002 4608 |
| Description | HASH Data Input 2 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[95:64] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 060C | ||
| Physical Address | 0x4002 460C | Instance | 0x4002 460C |
| Description | HASH Data Input 3 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[127:96] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when the rfd_in bit of the HASH_IO_BUF_CTRL register is high. If the rfd_in bit is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASH_IO_BUF_CTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0610 | ||
| Physical Address | 0x4002 4610 | Instance | 0x4002 4610 |
| Description | HASH Data Input 4 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[159:128] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is '1'. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0614 | ||
| Physical Address | 0x4002 4614 | Instance | 0x4002 4614 |
| Description | HASH Data Input 5 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[191:160] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0618 | ||
| Physical Address | 0x4002 4618 | Instance | 0x4002 4618 |
| Description | HASH Data Input 6 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[223:192] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 061C | ||
| Physical Address | 0x4002 461C | Instance | 0x4002 461C |
| Description | HASH Data Input 7 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[255:224] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0620 | ||
| Physical Address | 0x4002 4620 | Instance | 0x4002 4620 |
| Description | HASH Data Input 8 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[287:256] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0624 | ||
| Physical Address | 0x4002 4624 | Instance | 0x4002 4624 |
| Description | HASH Data Input 9 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[319:288] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0628 | ||
| Physical Address | 0x4002 4628 | Instance | 0x4002 4628 |
| Description | HASH Data Input 10 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[351:320] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 062C | ||
| Physical Address | 0x4002 462C | Instance | 0x4002 462C |
| Description | HASH Data Input 11 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[383:352] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0630 | ||
| Physical Address | 0x4002 4630 | Instance | 0x4002 4630 |
| Description | HASH Data Input 12 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[415:384] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0634 | ||
| Physical Address | 0x4002 4634 | Instance | 0x4002 4634 |
| Description | HASH Data Input 13 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[447:416] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0638 | ||
| Physical Address | 0x4002 4638 | Instance | 0x4002 4638 |
| Description | HASH Data Input 14 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[479:448] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 063C | ||
| Physical Address | 0x4002 463C | Instance | 0x4002 463C |
| Description | HASH Data Input 15 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[511:480] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0640 | ||
| Physical Address | 0x4002 4640 | Instance | 0x4002 4640 |
| Description | HASH Data Input 16 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[543:512] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0644 | ||
| Physical Address | 0x4002 4644 | Instance | 0x4002 4644 |
| Description | HASH Data Input 17 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[575:544] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0648 | ||
| Physical Address | 0x4002 4648 | Instance | 0x4002 4648 |
| Description | HASH Data Input 18 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[607:576] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 064C | ||
| Physical Address | 0x4002 464C | Instance | 0x4002 464C |
| Description | HASH Data Input 19 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[639:608] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0650 | ||
| Physical Address | 0x4002 4650 | Instance | 0x4002 4650 |
| Description | HASH Data Input 20 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[671:640] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0654 | ||
| Physical Address | 0x4002 4654 | Instance | 0x4002 4654 |
| Description | HASH Data Input 21 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[703:672] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0658 | ||
| Physical Address | 0x4002 4658 | Instance | 0x4002 4658 |
| Description | HASH Data Input 22 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[735:704] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 065C | ||
| Physical Address | 0x4002 465C | Instance | 0x4002 465C |
| Description | HASH Data Input 23 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[767:736] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0660 | ||
| Physical Address | 0x4002 4660 | Instance | 0x4002 4660 |
| Description | HASH Data Input 24 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[799:768] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0664 | ||
| Physical Address | 0x4002 4664 | Instance | 0x4002 4664 |
| Description | HASH Data Input 25 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[831:800] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0668 | ||
| Physical Address | 0x4002 4668 | Instance | 0x4002 4668 |
| Description | HASH Data Input 26 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[863:832] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 066C | ||
| Physical Address | 0x4002 466C | Instance | 0x4002 466C |
| Description | HASH Data Input 27 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[895:864] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0670 | ||
| Physical Address | 0x4002 4670 | Instance | 0x4002 4670 |
| Description | HASH Data Input 28 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[923:896] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0674 | ||
| Physical Address | 0x4002 4674 | Instance | 0x4002 4674 |
| Description | HASH Data Input 29 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[959:924] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0678 | ||
| Physical Address | 0x4002 4678 | Instance | 0x4002 4678 |
| Description | HASH Data Input 30 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[991:960] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 067C | ||
| Physical Address | 0x4002 467C | Instance | 0x4002 467C |
| Description | HASH Data Input 31 The data input registers should be used to provide input data to the hash module through the slave interface. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DATA_IN | HASH_DATA_IN[1023:992] These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer. Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data. For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0680 | ||
| Physical Address | 0x4002 4680 | Instance | 0x4002 4680 |
| Description | HASH Input_Output Buffer Control This register pair shares a single address location and contains bits that control and monitor the data flow between the host and the hash engine. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 0000 | ||
| 7 | PAD_DMA_MESSAGE | Note: This bit must only be used when data is supplied through the DMA. It should not be used when data is supplied through the slave interface. This bit indicates whether the hash engine has to pad the message, received through the DMA and finalize the hash. When set to 1, the hash engine pads the last block using the programmed length. After padding, the final hash result is calculated. When set to 0, the hash engine treats the last written block as block-size aligned and calculates the intermediate digest. This bit is automatically cleared when the last DMA data block is arrived in the hash engine. |
RW | 0 | ||
| 6 | GET_DIGEST | Note: The bit description below is only applicable when data is sent through the slave interface. This bit must be set to 0 when data is received through the DMA. This bit indicates whether the hash engine should provide the hash digest. When provided simultaneously with data_in_av, the hash digest is provided after processing the data that is currently in the HASHDATAINn register. When provided without data_in_av, the current internal digest buffer value is copied to the HASHDIGESTn registers. The host must write a 1 to this bit to make the intermediate hash digest available. Writing 0 to this bit has no effect. This bit is automatically cleared (that is, reads 0) when the hash engine has processed the contents of the HASHDATAINn register. In the period between this bit is set by the host and the actual HASHDATAINn processing, this bit reads 1. |
RW | 0 | ||
| 5 | PAD_MESSAGE | Note: The bit description below is only applicable when data is sent through the slave interface. This bit must be set to 0 when data is received through the DMA. This bit indicates that the HASHDATAINn registers hold the last data of the message and hash padding must be applied. The host must write this bit to 1 in order to indicate to the hash engine that the HASHDATAINn register currently holds the last data of the message. When pad_message is set to 1, the hash engine will add padding bits to the data currently in the HASHDATAINn register. When the last message block is smaller than 512 bits, the pad_message bit must be set to 1 together with the data_in_av bit. When the last message block is equal to 512 bits, pad_message may be set together with data_in_av. In this case the pad_message bit may also be set after the last data block has been written to the hash engine (so when the rfd_in bit has become 1 again after writing the last data block). Writing 0 to this bit has no effect. This bit is automatically cleared (i.e. reads 0) by the hash engine. This bit reads 1 between the time it was set by the host and the hash engine interpreted its value. |
RW | 0 | ||
| 4:3 | RESERVED3 | Write 0s and ignore on reading | RW | 0b00 | ||
| 2 | RFD_IN | Note: The bit description below is only applicable when data is sent through the slave interface. This bit can be ignored when data is received through the DMA. Read-only status of the input buffer of the hash engine. When 1, the input buffer of the hash engine can accept new data; the HASHDATAINn registers can safely be populated with new data. When 0, the input buffer of the hash engine is processing the data that is currently in HASHDATAINn; writing new data to these registers is not allowed. |
RW | 1 | ||
| 1 | DATA_IN_AV | Note: The bit description below is only applicable when data is sent through the slave interface. This bit must be set to 0 when data is received through the DMA. This bit indicates that the HASHDATAINn registers contain new input data for processing. The host must write a 1 to this bit to start processing the data in HASHDATAINn; the hash engine will process the new data as soon as it is ready for it (rfd_in bit is 1). Writing 0 to this bit has no effect. This bit is automatically cleared (i.e. reads as 0) when the hash engine starts processing the HASHDATAINn contents. This bit reads 1 between the time it was set by the host and the hash engine actually starts processing the input data block. |
RW | 0 | ||
| 0 | OUTPUT_FULL | Indicates that the output buffer registers (HASHDIGESTn) are available for reading by the host. When this bit reads 0, the output buffer registers are released; the hash engine is allowed to write new data to it. In this case, the registers should not be read by the host. When this bit reads 1, the hash engine has stored the result of the latest hash operation in the output buffer registers. As long as this bit reads 1, the host may read output buffer registers and the hash engine is prevented from writing new data to the output buffer. After retrieving the hash result data from the output buffer, the host must write a 1 to this bit to clear it. This makes the digest output buffer available for the hash engine to store new hash results. Writing 0 to this bit has no effect. Note: If this bit is asserted (1) no new operation should be started before the digest is retrieved from the hash engine and this bit is cleared (0). |
RW | 0 | ||
| Address Offset | 0x0000 0684 | ||
| Physical Address | 0x4002 4684 | Instance | 0x4002 4684 |
| Description | HASH Mode | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:7 | RESERVED7 | Write 0s and ignore on reading | WO | 0b0 0000 0000 0000 0000 0000 0000 | ||
| 6 | SHA384_MODE | The host must write this bit with 1 prior to processing a SHA 384 session. | WO | 0 | ||
| 5 | SHA512_MODE | The host must write this bit with 1 prior to processing a SHA 512 session. | WO | 0 | ||
| 4 | SHA224_MODE | The host must write this bit with 1 prior to processing a SHA 224 session. | WO | 0 | ||
| 3 | SHA256_MODE | The host must write this bit with 1 prior to processing a SHA 256 session. | WO | 0 | ||
| 2:1 | RESERVED1 | Write 0s and ignore on reading | WO | 0b00 | ||
| 0 | NEW_HASH | When set to 1, it indicates that the hash engine must start processing a new hash session. The [HASHDIGESTn.* ] registers will automatically be loaded with the initial hash algorithm constants of the selected hash algorithm. When this bit is 0 while the hash processing is started, the initial hash algorithm constants are not loaded in the HASHDIGESTn registers. The hash engine will start processing with the digest that is currently in its internal HASHDIGESTn registers. This bit is automatically cleared when hash processing is started. |
WO | 0 | ||
| Address Offset | 0x0000 0688 | ||
| Physical Address | 0x4002 4688 | Instance | 0x4002 4688 |
| Description | HASH Input Length LSB | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | LENGTH_IN | LENGTH_IN[31:0] Message length registers. The content of these registers is used by the hash engine during the message padding phase of the hash session. The data lines of this registers are directly connected to the interface of the hash engine. For a write operation by the host, these registers should be written with the message length in bits. Final hash operations: The total input data length must be programmed for new hash operations that require finalization (padding). The input data must be provided through the slave or DMA interface. Continued hash operations (finalized): For continued hash operations that require finalization, the total message length must be programmed, including the length of previously hashed data that corresponds to the written input digest. Non-final hash operations: For hash operations that do not require finalization (input data length is multiple of 512-bits which is SHA-256 data block size), the length field does not need to be programmed since not used by the operation. If the message length in bits is below (2^32-1), then only this register needs to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s in this case. The host may write the length register at any time during the hash session when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written before the last data of the active hash session is written into the hash engine. host read operations from these register locations will return 0s. Note: When getting data from DMA, this register must be programmed before DMA is programmed to start. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 068C | ||
| Physical Address | 0x4002 468C | Instance | 0x4002 468C |
| Description | HASH Input Length MSB | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | LENGTH_IN | LENGTH_IN[63:32] Message length registers. The content of these registers is used by the hash engine during the message padding phase of the hash session. The data lines of this registers are directly connected to the interface of the hash engine. For a write operation by the host, these registers should be written with the message length in bits. Final hash operations: The total input data length must be programmed for new hash operations that require finalization (padding). The input data must be provided through the slave or DMA interface. Continued hash operations (finalized): For continued hash operations that require finalization, the total message length must be programmed, including the length of previously hashed data that corresponds to the written input digest. Non-final hash operations: For hash operations that do not require finalization (input data length is multiple of 512-bits which is SHA-256 data block size), the length field does not need to be programmed since not used by the operation. If the message length in bits is below (2^32-1), then only HASHINLENL needs to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s in this case. The host may write the length register at any time during the hash session when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written before the last data of the active hash session is written into the hash engine. host read operations from these register locations will return 0s. Note: When getting data from DMA, this register must be programmed before DMA is programmed to start. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 06C0 | ||
| Physical Address | 0x4002 46C0 | Instance | 0x4002 46C0 |
| Description | HASH Digest A The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[31:0] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06C4 | ||
| Physical Address | 0x4002 46C4 | Instance | 0x4002 46C4 |
| Description | HASH Digest B The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[63:32] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06C8 | ||
| Physical Address | 0x4002 46C8 | Instance | 0x4002 46C8 |
| Description | HASH Digest C The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[95:64] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06CC | ||
| Physical Address | 0x4002 46CC | Instance | 0x4002 46CC |
| Description | HASH Digest D The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[127:96] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06D0 | ||
| Physical Address | 0x4002 46D0 | Instance | 0x4002 46D0 |
| Description | HASH Digest E The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[159:128] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06D4 | ||
| Physical Address | 0x4002 46D4 | Instance | 0x4002 46D4 |
| Description | HASH Digest F The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[191:160] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06D8 | ||
| Physical Address | 0x4002 46D8 | Instance | 0x4002 46D8 |
| Description | HASH Digest G The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[223:192] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06DC | ||
| Physical Address | 0x4002 46DC | Instance | 0x4002 46DC |
| Description | HASH Digest H The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[255:224] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06E0 | ||
| Physical Address | 0x4002 46E0 | Instance | 0x4002 46E0 |
| Description | HASH Digest I The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[287:256] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06E4 | ||
| Physical Address | 0x4002 46E4 | Instance | 0x4002 46E4 |
| Description | HASH Digest J The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[319:288] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06E8 | ||
| Physical Address | 0x4002 46E8 | Instance | 0x4002 46E8 |
| Description | HASH Digest K The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[351:320] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06EC | ||
| Physical Address | 0x4002 46EC | Instance | 0x4002 46EC |
| Description | HASH Digest L The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[383:352] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06F0 | ||
| Physical Address | 0x4002 46F0 | Instance | 0x4002 46F0 |
| Description | HASH Digest M The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[415:384] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06F4 | ||
| Physical Address | 0x4002 46F4 | Instance | 0x4002 46F4 |
| Description | HASH Digest N The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[447:416] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06F8 | ||
| Physical Address | 0x4002 46F8 | Instance | 0x4002 46F8 |
| Description | HASH Digest 0 The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[479:448] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 06FC | ||
| Physical Address | 0x4002 46FC | Instance | 0x4002 46FC |
| Description | HASH Digest P The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | HASH_DIGEST | HASH_DIGEST[511:480] Hash digest registers Write operation: Continued hash: These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session). New hash: When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written. Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0700 | ||
| Physical Address | 0x4002 4700 | Instance | 0x4002 4700 |
| Description | Algorithm Select This algorithm selection register configures the internal destination of the DMA controller. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 32 | HASH_SHA_512 | If set to one, selects the hash engine in 512B mode as destination for the DMA The maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out through the DMA). |
RW | 0 | ||
| 31 | TAG | If this bit is cleared to 0, the DMA operation involves only data. If this bit is set, the DMA operation includes a TAG (Authentication Result / Digest). For SHA-256 operation, a DMA must be set up for both input data and TAG. For any other selected module, setting this bit only allows a DMA that reads the TAG. No data allowed to be transferred to or from the selected module via the DMA. |
RW | 0 | ||
| 30:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 2 | HASH_SHA_256 | If set to one, selects the hash engine in 256B mode as destination for the DMA The maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out through the DMA). |
RW | 0 | ||
| 1 | AES | If set to one, selects the AES engine as source/destination for the DMA The read and write maximum transfer size to the DMA engine is set to 16 bytes. |
RW | 0 | ||
| 0 | KEY_STORE | If set to one, selects the Key Store as destination for the DMA The maximum transfer size to DMA engine is set to 32 bytes (however transfers of 16, 24 and 32 bytes are allowed) |
RW | 0 | ||
| Address Offset | 0x0000 0704 | ||
| Physical Address | 0x4002 4704 | Instance | 0x4002 4704 |
| Description | DMA Protection Control Master PROT privileged access enable This register enables the second bit (bit [1]) of the AHB HPROT bus of the AHB master interface when a read action of key(s) is performed on the AHB master interface for writing keys into the store module. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | PROT_EN | Select AHB transfer protection control for DMA transfers using the key store area as destination. 0 : transfers use 'USER' type access. 1 : transfers use 'PRIVILEGED' type access. |
RW | 0 | ||
| Address Offset | 0x0000 0740 | ||
| Physical Address | 0x4002 4740 | Instance | 0x4002 4740 |
| Description | Software Reset | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | SW_RESET | If this bit is set to 1, the following modules are reset: - Master control internal state is reset. That includes interrupt, error status register, and result available interrupt generation FSM. - Key store module state is reset. That includes clearing the written area flags; therefore, the keys must be reloaded to the key store module. Writing 0 has no effect. The bit is self cleared after executing the reset. |
RW | 0 | ||
| Address Offset | 0x0000 0780 | ||
| Physical Address | 0x4002 4780 | Instance | 0x4002 4780 |
| Description | Control Interrupt Configuration | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | LEVEL | If this bit is 0, the interrupt output is a pulse. If this bit is set to 1, the interrupt is a level interrupt that must be cleared by writing the interrupt clear register. This bit is applicable for both interrupt output signals. |
RW | 0 | ||
| Address Offset | 0x0000 0784 | ||
| Physical Address | 0x4002 4784 | Instance | 0x4002 4784 |
| Description | Control Interrupt Enable | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DMA_IN_DONE | If this bit is set to 0, the DMA input done (irq_dma_in_done) interrupt output is disabled and remains 0. If this bit is set to 1, the DMA input done interrupt output is enabled. |
RW | 0 | ||
| 0 | RESULT_AVAIL | If this bit is set to 0, the result available (irq_result_av) interrupt output is disabled and remains 0. If this bit is set to 1, the result available interrupt output is enabled. |
RW | 0 | ||
| Address Offset | 0x0000 0788 | ||
| Physical Address | 0x4002 4788 | Instance | 0x4002 4788 |
| Description | Control Interrupt Clear | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | DMA_BUS_ERR | If 1 is written to this bit, the DMA bus error status is cleared. Writing 0 has no effect. |
WO | 0 | ||
| 30 | KEY_ST_WR_ERR | If 1 is written to this bit, the key store write error status is cleared. Writing 0 has no effect. |
WO | 0 | ||
| 29 | KEY_ST_RD_ERR | If 1 is written to this bit, the key store read error status is cleared. Writing 0 has no effect. |
WO | 0 | ||
| 28:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DMA_IN_DONE | If 1 is written to this bit, the DMA in done (irq_dma_in_done) interrupt output is cleared. Writing 0 has no effect. Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE). |
WO | 0 | ||
| 0 | RESULT_AVAIL | If 1 is written to this bit, the result available (irq_result_av) interrupt output is cleared. Writing 0 has no effect. Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE). |
WO | 0 | ||
| Address Offset | 0x0000 078C | ||
| Physical Address | 0x4002 478C | Instance | 0x4002 478C |
| Description | Control Interrupt Set | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DMA_IN_DONE | If 1 is written to this bit, the DMA data in done (irq_dma_in_done) interrupt output is set to one. Writing 0 has no effect. If the interrupt configuration register is programmed to pulse, clearing the DMA data in done (irq_dma_in_done) interrupt is not needed. If it is programmed to level, clearing the interrupt output should be done by writing the interrupt clear register (IRQCLR.DMA_IN_DONE). |
WO | 0 | ||
| 0 | RESULT_AVAIL | If 1 is written to this bit, the result available (irq_result_av) interrupt output is set to one. Writing 0 has no effect. If the interrupt configuration register is programmed to pulse, clearing the result available (irq_result_av) interrupt is not needed. If it is programmed to level, clearing the interrupt output should be done by writing the interrupt clear register (IRQCLR.RESULT_AVAIL). |
WO | 0 | ||
| Address Offset | 0x0000 0790 | ||
| Physical Address | 0x4002 4790 | Instance | 0x4002 4790 |
| Description | Control Interrupt Status | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | DMA_BUS_ERR | This bit is set when a DMA bus error is detected during a DMA operation. The value of this register is held until it is cleared through the IRQCLR.DMA_BUS_ERR Note: This error is asserted if an error is detected on the AHB master interface during a DMA operation. |
RO | 0 | ||
| 30 | KEY_ST_WR_ERR | This bit is set when a write error is detected during the DMA write operation to the key store memory. The value of this register is held until it is cleared through the IRQCLR.KEY_ST_WR_ERR register. Note: This error is asserted if a DMA operation does not cover a full key area or more areas are written than expected. |
RO | 0 | ||
| 29 | KEY_ST_RD_ERR | This bit is set when a read error is detected during the read of a key from the key store, while copying it to the AES core. The value of this register is held until it is cleared through the IRQCLR.KEY_ST_RD_ERR register. Note: This error is asserted if a key location is selected in the key store that is not available. |
RO | 0 | ||
| 28:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DMA_IN_DONE | This read only bit returns the actual DMA data in done (irq_data_in_done) interrupt status of the DMA data in done interrupt output pin (irq_data_in_done). | RO | 0 | ||
| 0 | RESULT_AVAIL | This read only bit returns the actual result available (irq_result_av) interrupt status of the result available interrupt output pin (irq_result_av). | RO | 0 | ||
| Address Offset | 0x0000 07FC | ||
| Physical Address | 0x4002 47FC | Instance | 0x4002 47FC |
| Description | Hardware Version | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RESERVED28 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x9 | ||
| 27:24 | HW_MAJOR_VER | Major version number | RO | 0x2 | ||
| 23:20 | HW_MINOR_VER | Minor version number | RO | 0x0 | ||
| 19:16 | HW_PATCH_LVL | Patch level Starts at 0 at first delivery of this version |
RO | 0x0 | ||
| 15:8 | VER_NUM_COMPL | These bits simply contain the complement of bits [7:0] (0x87), used by a driver to ascertain that the EIP-120t register is indeed read. | RO | 0x87 | ||
| 7:0 | VER_NUM | These bits encode the EIP number for the EIP-120t, this field contains the value 120 (decimal) or 0x78. | RO | 0x78 | ||
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