Instance: AUX_TIMER01
Component: AUX_TIMER01
Base address: 0x400C7000
AUX Timer 0 and AUX Timer 1 (AUX_TIMER01) are two 16-bit timers capable of generating one event each:
- AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV.
- AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV.
The events are described in T0TARGET and T1TARGET. Subscribers to the AUX event bus can use these events to sequence and trigger actions.
AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the peripheral clock frequency used by the prescaler, timer, and event logic to SCE or AUX bus rate. To use AUX_TIMER01:
- AUX_SCE must set AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE to SCE_RATE.
- System CPU must set AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE to BUS_RATE.
- The timers must only subscribe to events updated at the peripheral clock frequency or lower.
Unexpected execution behavior can result if software does not obey these rules.
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x400C 7000 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x400C 7004 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x400C 7008 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 000C |
0x400C 700C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x400C 7010 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x400C 7014 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C 7018 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 001C |
0x400C 701C |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x400C 7000 | Instance | 0x400C 7000 |
| Description | Timer 0 Configuration | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 | |||||||||||
| 14 | TICK_SRC_POL | Tick source polarity for Timer 0.
|
RW | 0 | |||||||||||
| 13:8 | TICK_SRC | Select Timer 0 tick source from the synchronous event bus. | RW | 0b00 0000 | |||||||||||
| 7:4 | PRE | Prescaler division ratio is 2^PRE: 0x0: Divide by 1. 0x1: Divide by 2. 0x2: Divide by 4. ... 0xF: Divide by 32,768. |
RW | 0x0 | |||||||||||
| 3:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||
| 1 | MODE | Timer 0 mode. Configure source for Timer 0 prescaler.
|
RW | 0 | |||||||||||
| 0 | RELOAD | Timer 0 reload mode.
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x400C 7004 | Instance | 0x400C 7004 |
| Description | Timer 0 Control | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | EN | Timer 0 enable. 0: Disable Timer 0. 1: Enable Timer 0. The counter restarts from 0 when you enable Timer 0. |
RW | 0 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0x400C 7008 | Instance | 0x400C 7008 |
| Description | Timer 0 Target | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:0 | VALUE | Timer 0 target value. Manual Reload Mode: - Timer 0 increments until the counter value becomes equal to or greater than VALUE. - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter value is equal to or greater than VALUE. Note: When VALUE is 0, Timer 0 counts to 1. AUX_TIMER0_EV pulses high for 1 peripheral clock period. Continuous Reload Mode: - Timer 0 increments until the counter value becomes equal to or greater than ( VALUE - 1), then restarts from 0. - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter value is 0, except for when you enable the timer. Note: When VALUE is less than 2, Timer 0 counter value remains 0. AUX_TIMER0_EV goes high and remains high 1 peripheral clock period after you enable the timer. It is allowed to update the VALUE while the timer runs. |
RW | 0x0000 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0x400C 700C | Instance | 0x400C 700C |
| Description | Timer 0 Counter | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:0 | VALUE | Timer 0 counter value. | RO | 0x0000 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0x400C 7010 | Instance | 0x400C 7010 |
| Description | Timer 1 Configuration | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 | |||||||||||
| 14 | TICK_SRC_POL | Tick source polarity for Timer 1.
|
RW | 0 | |||||||||||
| 13:8 | TICK_SRC | Select Timer 1 tick source from the synchronous event bus. | RW | 0b00 0000 | |||||||||||
| 7:4 | PRE | Prescaler division ratio is 2^PRE: 0x0: Divide by 1. 0x1: Divide by 2. 0x2: Divide by 4. ... 0xF: Divide by 32,768. |
RW | 0x0 | |||||||||||
| 3:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||
| 1 | MODE | Timer 1 mode. Configure source for Timer 1 prescaler.
|
RW | 0 | |||||||||||
| 0 | RELOAD | Timer 1 reload mode.
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0x400C 7014 | Instance | 0x400C 7014 |
| Description | Timer 1 Control | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | EN | Timer 1 enable. 0: Disable Timer 1. 1: Enable Timer 1. The counter restarts from 0 when you enable Timer 1. |
RW | 0 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0x400C 7018 | Instance | 0x400C 7018 |
| Description | Timer 1 Target Timer 1 counter target value |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:0 | VALUE | Timer 1 target value. Manual Reload Mode: - Timer 1 increments until the counter value becomes equal to or greater than VALUE. - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter value is equal to or greater than VALUE. Note: When VALUE is 0, Timer 1 counts to 1. AUX_TIMER1_EV pulses high for 1 peripheral clock period. Continuous Reload Mode: - Timer 1 increments until the counter value becomes equal to or greater than ( VALUE - 1), then restarts from 0. - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter value is 0, except for when you enable the timer. Note: When VALUE is less than 2, Timer 1 counter value remains 0. AUX_TIMER1_EV goes high and remains high 1 peripheral clock period after you enable the timer. It is allowed to update the VALUE while the timer runs. |
RW | 0x0000 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0x400C 701C | Instance | 0x400C 701C |
| Description | Timer 1 Counter | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:0 | VALUE | Timer 1 counter value. | RO | 0x0000 | ||
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