AUX_ANAIF

Instance: AUX_ANAIF
Component: AUX_ANAIF
Base address: 0x400C9000

AUX Analog Interface (AUX_ANAIF) encapsulates direct data and control interfaces between AUX digital and AUX analog circuits. It lets AUX_SCE, UDMA0, and system CPU:
-Trigger ADC sample and conversion process.
- Write ADC samples to FIFO.
- Charge analog nodes by the use of the analog ISRC module. See ADI_4_AUX:ISRC and ADI_4_AUX:COMP.COMPA_REF_CURR_EN for further information.
- Use the DAC to generate a programmable voltage on COMPB_REF, COMPA_REF, or COMPA_IN analog nodes.

To use:
- ADC : AUX_SCE must request active operational mode with AON_PMCTL:AUXSCECLK.SRC set to SCLK_HFDIV2. There are no requirements for system CPU.
- ISRC : AUX_SCE must request active operational mode. There are no requirements for system CPU.
- DAC : AUX_SCE must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to SCE_RATE as long as DAC state machine generates the sample clock. System CPU must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE as long as DAC state machine generates the sample clock. See DACSMPLCTL.EN for further information.

TOP:AUX_ANAIF Register Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset	Physical Address
ADCCTL	RW	32	0x0000 3F00	0x0000 0010	0x400C 9010
ADCFIFOSTAT	RO	32	0x0000 0001	0x0000 0014	0x400C 9014
ADCFIFO	RW	32	0x0000 0000	0x0000 0018	0x400C 9018
ADCTRIG	RW	32	0x0000 0000	0x0000 001C	0x400C 901C
ISRCCTL	RW	32	0x0000 0001	0x0000 0020	0x400C 9020
DACCTL	RW	32	0x0000 0000	0x0000 0030	0x400C 9030
LPMBIASCTL	RW	32	0x0000 0000	0x0000 0034	0x400C 9034
DACSMPLCTL	RW	32	0x0000 0000	0x0000 0038	0x400C 9038
DACSMPLCFG0	RW	32	0x0000 0000	0x0000 003C	0x400C 903C
DACSMPLCFG1	RW	32	0x0000 0000	0x0000 0040	0x400C 9040
DACVALUE	RW	32	0x0000 0000	0x0000 0044	0x400C 9044
DACSTAT	RO	32	0x0000 0000	0x0000 0048	0x400C 9048

TOP:AUX_ANAIF Register Descriptions

TOP:AUX_ANAIF:ADCCTL

Address Offset	0x0000 0010
Physical Address	0x400C 9010	Instance	0x400C 9010
Description	ADC Control Configuration of ADI_4_AUX:ADC0.SMPL_MODE decides if the ADC trigger starts sampling or conversion.
Type	RW

Bits

Field Name

Description

Type

Reset

31:15

RESERVED15

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000

START_POL

Select active polarity for START_SRC event.

Value	ENUM Name	Description
0x0	RISE	Set ADC trigger on rising edge of event source.
0x1	FALL	Set ADC trigger on falling edge of event source.

13:8

START_SRC

Select ADC trigger event source from the asynchronous AUX event bus.

Set START_SRC to NO_EVENT if you want to trigger the ADC manually through ADCTRIG.START.

If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read.

Value	ENUM Name	Description
0x0	AUXIO0	AUX_EVCTL:EVSTAT0.AUXIO0
0x1	AUXIO1	AUX_EVCTL:EVSTAT0.AUXIO1
0x2	AUXIO2	AUX_EVCTL:EVSTAT0.AUXIO2
0x3	AUXIO3	AUX_EVCTL:EVSTAT0.AUXIO3
0x4	AUXIO4	AUX_EVCTL:EVSTAT0.AUXIO4
0x5	AUXIO5	AUX_EVCTL:EVSTAT0.AUXIO5
0x6	AUXIO6	AUX_EVCTL:EVSTAT0.AUXIO6
0x7	AUXIO7	AUX_EVCTL:EVSTAT0.AUXIO7
0x8	AUXIO8	AUX_EVCTL:EVSTAT0.AUXIO8
0x9	AUXIO9	AUX_EVCTL:EVSTAT0.AUXIO9
0xA	AUXIO10	AUX_EVCTL:EVSTAT0.AUXIO10
0xB	AUXIO11	AUX_EVCTL:EVSTAT0.AUXIO11
0xC	AUXIO12	AUX_EVCTL:EVSTAT0.AUXIO12
0xD	AUXIO13	AUX_EVCTL:EVSTAT0.AUXIO13
0xE	AUXIO14	AUX_EVCTL:EVSTAT0.AUXIO14
0xF	AUXIO15	AUX_EVCTL:EVSTAT0.AUXIO15
0x10	AUXIO16	AUX_EVCTL:EVSTAT1.AUXIO16
0x11	AUXIO17	AUX_EVCTL:EVSTAT1.AUXIO17
0x12	AUXIO18	AUX_EVCTL:EVSTAT1.AUXIO18
0x13	AUXIO19	AUX_EVCTL:EVSTAT1.AUXIO19
0x14	AUXIO20	AUX_EVCTL:EVSTAT1.AUXIO20
0x15	AUXIO21	AUX_EVCTL:EVSTAT1.AUXIO21
0x16	AUXIO22	AUX_EVCTL:EVSTAT1.AUXIO22
0x17	AUXIO23	AUX_EVCTL:EVSTAT1.AUXIO23
0x18	AUXIO24	AUX_EVCTL:EVSTAT1.AUXIO24
0x19	AUXIO25	AUX_EVCTL:EVSTAT1.AUXIO25
0x1A	AUXIO26	AUX_EVCTL:EVSTAT1.AUXIO26
0x1B	AUXIO27	AUX_EVCTL:EVSTAT1.AUXIO27
0x1C	AUXIO28	AUX_EVCTL:EVSTAT1.AUXIO28
0x1D	AUXIO29	AUX_EVCTL:EVSTAT1.AUXIO29
0x1E	AUXIO30	AUX_EVCTL:EVSTAT1.AUXIO30
0x1F	AUXIO31	AUX_EVCTL:EVSTAT1.AUXIO31
0x20	MANUAL_EV	AUX_EVCTL:EVSTAT2.MANUAL_EV
0x21	AON_RTC_CH2	AUX_EVCTL:EVSTAT2.AON_RTC_CH2
0x22	AON_RTC_CH2_DLY	AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
0x23	AON_RTC_4KHZ	AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
0x24	AON_BATMON_BAT_UPD	AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
0x25	AON_BATMON_TEMP_UPD	AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
0x26	SCLK_LF	AUX_EVCTL:EVSTAT2.SCLK_LF
0x27	PWR_DWN	AUX_EVCTL:EVSTAT2.PWR_DWN
0x28	MCU_ACTIVE	AUX_EVCTL:EVSTAT2.MCU_ACTIVE
0x29	VDDR_RECHARGE	AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
0x2A	ACLK_REF	AUX_EVCTL:EVSTAT2.ACLK_REF
0x2B	MCU_EV	AUX_EVCTL:EVSTAT2.MCU_EV
0x2E	AUX_COMPA	AUX_EVCTL:EVSTAT2.AUX_COMPA
0x2F	AUX_COMPB	AUX_EVCTL:EVSTAT2.AUX_COMPB
0x30	AUX_TIMER2_EV0	AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
0x31	AUX_TIMER2_EV1	AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
0x32	AUX_TIMER2_EV2	AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
0x33	AUX_TIMER2_EV3	AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
0x34	AUX_TIMER2_PULSE	AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
0x35	AUX_TIMER1_EV	AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
0x36	AUX_TIMER0_EV	AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
0x37	AUX_TDC_DONE	AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
0x38	AUX_ISRC_RESET_N	AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
0x3D	AUX_SMPH_AUTOTAKE_DONE	AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
0x3F	NO_EVENT	No event.

0b11 1111

7:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000

1:0

CMD

ADC interface command.

Non-enumerated values are not supported. The written value is returned when read.

Value	ENUM Name	Description
0x0	DIS	Disable ADC interface.
0x1	EN	Enable ADC interface.
0x3	FLUSH	Flush ADC FIFO. You must set CMD to EN or DIS after flush. System CPU must wait two clock cycles before it sets CMD to EN or DIS.

0b00

TOP:AUX_ANAIF:ADCFIFOSTAT

Address Offset	0x0000 0014
Physical Address	0x400C 9014	Instance	0x400C 9014
Description	ADC FIFO Status FIFO can hold up to four ADC samples.
Type	RO

Bits	Field Name	Description	Type	Reset
31:5	RESERVED5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b000 0000 0000 0000 0000 0000 0000
4	OVERFLOW	FIFO overflow flag. 0: FIFO has not overflowed. 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. When the flag is set, the ADC FIFO write pointer is static. It is not possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag.	RO	0
3	UNDERFLOW	FIFO underflow flag. 0: FIFO has not underflowed. 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. When the flag is set, the ADC FIFO read pointer is static. Read returns the previous sample that was read. Flush FIFO to clear the flag.	RO	0
2	FULL	FIFO full flag. 0: FIFO is not full, there is less than 4 samples in the FIFO. 1: FIFO is full, there are 4 samples in the FIFO. When the flag is set, it is not possible to add more samples to the ADC FIFO. An attempt to add samples sets the OVERFLOW flag.	RO	0
1	ALMOST_FULL	FIFO almost full flag. 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL flag is also asserted in the latter case. 1: There are 3 samples in the FIFO, there is room for one more sample.	RO	0
0	EMPTY	FIFO empty flag. 0: FIFO contains one or more samples. 1: FIFO is empty. When the flag is set, read returns the previous sample that was read and sets the UNDERFLOW flag.	RO	1

TOP:AUX_ANAIF:ADCFIFO

Address Offset	0x0000 0018
Physical Address	0x400C 9018	Instance	0x400C 9018
Description	ADC FIFO
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	RESERVED12	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0 0000
11:0	DATA	FIFO data. Read: Get oldest ADC sample from FIFO. Write: Write dummy sample to FIFO. This is useful for code development when you do not have real ADC samples.	RW	0x000

TOP:AUX_ANAIF:ADCTRIG

Address Offset	0x0000 001C
Physical Address	0x400C 901C	Instance	0x400C 901C
Description	ADC Trigger
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	RESERVED1	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b000 0000 0000 0000 0000 0000 0000 0000
0	START	Manual ADC trigger. 0: No effect. 1: Single ADC trigger. To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to avoid conflict with event-driven ADC trigger.	WO	0

TOP:AUX_ANAIF:ISRCCTL

Address Offset	0x0000 0020
Physical Address	0x400C 9020	Instance	0x400C 9020
Description	Current Source Control
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	RESERVED1	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b000 0000 0000 0000 0000 0000 0000 0000
0	RESET_N	ISRC reset control. 0: ISRC drives 0 uA. 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN.	RW	1

TOP:AUX_ANAIF:DACCTL

Address Offset	0x0000 0030
Physical Address	0x400C 9030	Instance	0x400C 9030
Description	DAC Control This register controls the analog part of the DAC.
Type	RW

Bits

Field Name

Description

Type

Reset

31:6

RESERVED6

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000

DAC_EN

DAC module enable.

0: Disable DAC.
1: Enable DAC.

The Sensor Controller must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA.

The System CPU must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA in Standby TI-RTOS power mode. The System CPU must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE to use the DAC in Active and Idle TI-RTOS power modes.

DAC_BUFFER_EN

DAC buffer enable.

DAC buffer reduces the time required to produce the programmed voltage at the expense of increased current consumption.

0: Disable DAC buffer.
1: Enable DAC buffer.

Enable buffer when DAC_VOUT_SEL equals COMPA_IN.

Do not enable the buffer when AUX_SYSIF:OPMODEREQ.REQ equals PDA or PDLP.

DAC_PRECHARGE_EN

DAC precharge enable.

Only enable precharge when ADI_4_AUX:MUX2.DAC_VREF_SEL equals DCOUPL and VDDS is higher than 2.65 V.

DAC output voltage range:

0: 0 V to 1.28 V.
1: 1.28 V to 2.56 V.

Otherwise, see ADI_4_AUX:MUX2.DAC_VREF_SEL for DAC output voltage range.

Enable precharge 1 us before you enable the DAC and the buffer.

2:0

DAC_VOUT_SEL

DAC output connection.

An analog node must only have one driver. Other drivers for the following analog nodes are configured in [ANATOP_MMAP::ADI_4_AUX:*].

Value	ENUM Name	Description
0x0	NC	Connect to nothing It is recommended to use NC as intermediate step when you change DAC_VOUT_SEL.
0x1	COMPB_REF	Connect to COMPB_REF analog node. Required setting to use Comparator B.
0x2	COMPA_REF	Connect to COMPA_REF analog node. It is not possible to drive external loads connected to COMPA_REF I/O mux with this setting.
0x4	COMPA_IN	Connect to COMPA_IN analog node. Required setting to drive external load selected in ADI_4_AUX:MUX1.COMPA_IN.

0b000

TOP:AUX_ANAIF:LPMBIASCTL

Address Offset	0x0000 0034
Physical Address	0x400C 9034	Instance	0x400C 9034
Description	Low Power Mode Bias Control The low power mode bias module provides bias current to DAC and Comparator A when AUX_SYSIF:OPMODEREQ.REQ differers from A.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	RESERVED1	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b000 0000 0000 0000 0000 0000 0000 0000
0	EN	Module enable. 0: Disable low power mode bias module. 1: Enable low power mode bias module. Set EN to 1 15 us before you enable the DAC or Comparator A.	RW	0

TOP:AUX_ANAIF:DACSMPLCTL

Address Offset	0x0000 0038
Physical Address	0x400C 9038	Instance	0x400C 9038
Description	DAC Sample Control The DAC sample clock maintains the DAC voltage stored in the sample-and-hold capacitor. The DAC sample clock waveform consists of a setup phase followed by a hold phase. In the setup phase the sample-and-hold capacitor charges to the programmed voltage. The hold phase maintains the voltage with minimal power. DACSMPLCFG0 and DACSMPLCFG1 configure the DAC sample clock waveform.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b000 0000 0000 0000 0000 0000 0000 0000
0	EN	DAC sample clock enable. 0: Disable sample clock. The sample clock stops low and DACSTAT becomes 0 when the current sample clock period completes. 1: Enable DAC sample clock. DACSTAT must be 0 before you enable sample clock.	RW	0

TOP:AUX_ANAIF:DACSMPLCFG0

Address Offset	0x0000 003C
Physical Address	0x400C 903C	Instance	0x400C 903C
Description	DAC Sample Configuration 0
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	RESERVED6	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b00 0000 0000 0000 0000 0000 0000
5:0	CLKDIV	Clock division. AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE divided by (CLKDIV + 1) determines the sample clock base frequency. 0: Divide by 1. 1: Divide by 2. ... 63: Divide by 64.	RW	0b00 0000

TOP:AUX_ANAIF:DACSMPLCFG1

Address Offset	0x0000 0040
Physical Address	0x400C 9040	Instance	0x400C 9040
Description	DAC Sample Configuration 1 The sample clock period equals (high time + low time) * base period. DACSMPLCFG0.CLKDIV determines the base period. Timing requirements (DAC Buffer On / DAC Buffer Off): - (high time + low time) * base period > (4 us / 1 us) - (high time * base period) > (2 us / 0.5 us) - (low time * base period) > (2 us / 0.5 us) - (low time * base period + HOLD_INTERVAL * sample clock period) < 32 us If AUX_SYSIF:OPMODEREQ.REQ equals PDLP, you must set: - H_PER = L_PER = HOLD_INTERVAL = 0.
Type	RW

Bits	Field Name	Description	Type	Reset
31:15	RESERVED15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b0 0000 0000 0000 0000
14	H_PER	High time. The sample clock period is high for this many base periods. 0: 2 periods 1: 4 periods	RW	0
13:12	L_PER	Low time. The sample clock period is low for this many base periods. 0: 1 period 1: 2 periods 2: 3 periods 3: 4 periods	RW	0b00
11:8	SETUP_CNT	Setup count. Number of active sample clock periods during the setup phase. 0: 1 sample clock period 1: 2 sample clock periods ... 15 : 16 sample clock periods	RW	0x0
7:0	HOLD_INTERVAL	Hold interval. Number of inactive sample clock periods between each active sample clock period during hold phase. The sample clock is low when inactive. The range is 0 to 255.	RW	0x00

TOP:AUX_ANAIF:DACVALUE

Address Offset	0x0000 0044
Physical Address	0x400C 9044	Instance	0x400C 9044
Description	DAC Value
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x00 0000
7:0	VALUE	DAC value. Digital data word for the DAC. Only change VALUE when DACCTL.DAC_EN is 0. Then wait 1 us before you enable the DAC.	RW	0x00

TOP:AUX_ANAIF:DACSTAT

Address Offset	0x0000 0048
Physical Address	0x400C 9048	Instance	0x400C 9048
Description	DAC Status
Type	RO

Bits	Field Name	Description	Type	Reset
31:2	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b00 0000 0000 0000 0000 0000 0000 0000
1	SETUP_ACTIVE	DAC setup phase status. 0: Sample clock is disabled or setup phase is complete. 1: Setup phase in progress.	RO	0
0	HOLD_ACTIVE	DAC hold phase status. 0: Sample clock is disabled or DAC is not in hold phase. 1: Hold phase in progress.	RO	0