AUX_AIODIO3

Instance: AUX_AIODIO3
Component: AUX_AIODIO
Base address: 0x400CF000


AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can:
- be connected to analog AUX modules, such as comparators and ADC.
- be used by AUX_SCE.
- connect to AUX_SPIM SCLK, MISO and MOSI signals.
- connect to the asynchronous AUX event bus.

Enabled digital inputs are synchronized at SCE clock rate.

Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO[n] does not map to DIO[n]. AUXIO-DIO remapping is handled by Sensor Controller Studio.

TOP:AUX_AIODIO3 Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

IOMODE

RW

32

0x0000 0000

0x0000 0000

0x400C F000

GPIODIE

RW

32

0x0000 0000

0x0000 0004

0x400C F004

IOPOE

RW

32

0x0000 0000

0x0000 0008

0x400C F008

GPIODOUT

RW

32

0x0000 0000

0x0000 000C

0x400C F00C

GPIODIN

RO

32

0x0000 0000

0x0000 0010

0x400C F010

GPIODOUTSET

RW

32

0x0000 0000

0x0000 0014

0x400C F014

GPIODOUTCLR

RW

32

0x0000 0000

0x0000 0018

0x400C F018

GPIODOUTTGL

RW

32

0x0000 0000

0x0000 001C

0x400C F01C

IO0PSEL

RW

32

0x0000 0000

0x0000 0020

0x400C F020

IO1PSEL

RW

32

0x0000 0000

0x0000 0024

0x400C F024

IO2PSEL

RW

32

0x0000 0000

0x0000 0028

0x400C F028

IO3PSEL

RW

32

0x0000 0000

0x0000 002C

0x400C F02C

IO4PSEL

RW

32

0x0000 0000

0x0000 0030

0x400C F030

IO5PSEL

RW

32

0x0000 0000

0x0000 0034

0x400C F034

IO6PSEL

RW

32

0x0000 0000

0x0000 0038

0x400C F038

IO7PSEL

RW

32

0x0000 0000

0x0000 003C

0x400C F03C

IOMODEL

RW

32

0x0000 0000

0x0000 0040

0x400C F040

IOMODEH

RW

32

0x0000 0000

0x0000 0044

0x400C F044

TOP:AUX_AIODIO3 Register Descriptions

TOP:AUX_AIODIO3:IOMODE

Address Offset 0x0000 0000
Physical Address 0x400C F000 Instance 0x400C F000
Description Input Output Mode

This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:14 IO7 Selects mode for AUXIO[8i+7].
Value ENUM Name Description
0x0 OUT Output Mode:

When IOPOE bit 7 is 0: GPIODOUT bit 7 drives AUXIO[8i+7].

When IOPOE bit 7 is 1: The signal selected by IO7PSEL.SRC drives AUXIO[8i+7].
0x1 IN Input Mode:

When GPIODIE bit 7 is 0: AUXIO[8i+7] is enabled for analog signal transfer.

When GPIODIE bit 7 is 1: AUXIO[8i+7] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When IOPOE bit 7 is 0:
- If GPIODOUT bit 7 is 0: AUXIO[8i+7] is driven low.
- If GPIODOUT bit 7 is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When IOPOE bit 7 is 1:
- If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is driven low.
- If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When IOPOE bit 7 is 0:
- If GPIODOUT bit 7 is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 7 is 1: AUXIO[8i+7] is driven high.

When IOPOE bit 7 is 1:
- If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is driven high.
RW 0b00
13:12 IO6 Selects mode for AUXIO[8i+6].
Value ENUM Name Description
0x0 OUT Output Mode:

When IOPOE bit 6 is 0: GPIODOUT bit 6 drives AUXIO[8i+6].

When IOPOE bit 6 is 1: The signal selected by IO6PSEL.SRC drives AUXIO[8i+6].
0x1 IN Input Mode:

When GPIODIE bit 6 is 0: AUXIO[8i+6] is enabled for analog signal transfer.

When GPIODIE bit 6 is 1: AUXIO[8i+6] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When IOPOE bit 6 is 0:
- If GPIODOUT bit 6 is 0: AUXIO[8i+6] is driven low.
- If GPIODOUT bit 6 is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When IOPOE bit 6 is 1:
- If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is driven low.
- If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When IOPOE bit 6 is 0:
- If GPIODOUT bit 6 is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 6 is 1: AUXIO[8i+6] is driven high.

When IOPOE bit 6 is 1:
- If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is driven high.
RW 0b00
11:10 IO5 Selects mode for AUXIO[8i+5].
Value ENUM Name Description
0x0 OUT Output Mode:

When IOPOE bit 5 is 0: GPIODOUT bit 5 drives AUXIO[8i+5].

When IOPOE bit 5 is 1: The signal selected by IO5PSEL.SRC drives AUXIO[8i+5].
0x1 IN Input Mode:

When GPIODIE bit 5 is 0: AUXIO[8i+5] is enabled for analog signal transfer.

When GPIODIE bit 5 is 1: AUXIO[8i+5] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When IOPOE bit 5 is 0:
- If GPIODOUT bit 5 is 0: AUXIO[8i+5] is driven low.
- If GPIODOUT bit 5 is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When IOPOE bit 5 is 1:
- If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is driven low.
- If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When IOPOE bit 5 is 0:
- If GPIODOUT bit 5 is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 5 is 1: AUXIO[8i+5] is driven high.

When IOPOE bit 5 is 1:
- If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is driven high.
RW 0b00
9:8 IO4 Selects mode for AUXIO[8i+4].
Value ENUM Name Description
0x0 OUT Output Mode:

When IOPOE bit 4 is 0: GPIODOUT bit 4 drives AUXIO[8i+4].

When IOPOE bit 4 is 1: The signal selected by IO4PSEL.SRC drives AUXIO[8i+4].
0x1 IN Input Mode:

When GPIODIE bit 4 is 0: AUXIO[8i+4] is enabled for analog signal transfer.

When GPIODIE bit 4 is 1: AUXIO[8i+4] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When IOPOE bit 4 is 0:
- If GPIODOUT bit 4 is 0: AUXIO[8i+4] is driven low.
- If GPIODOUT bit 4 is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When IOPOE bit 4 is 1:
- If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is driven low.
- If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When IOPOE bit 4 is 0:
- If GPIODOUT bit 4 is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 4 is 1: AUXIO[8i+4] is driven high.

When IOPOE bit 4 is 1:
- If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is driven high.
RW 0b00
7:6 IO3 Selects mode for AUXIO[8i+3].
Value ENUM Name Description
0x0 OUT Output Mode:

When IOPOE bit 3 is 0: GPIODOUT bit 3 drives AUXIO[8i+3].

When IOPOE bit 3 is 1: The signal selected by IO3PSEL.SRC drives AUXIO[8i+3].
0x1 IN Input Mode:

When GPIODIE bit 3 is 0: AUXIO[8i+3] is enabled for analog signal transfer.

When GPIODIE bit 3 is 1: AUXIO[8i+3] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When IOPOE bit 3 is 0:
- If GPIODOUT bit 3 is 0: AUXIO[8i+3] is driven low.
- If GPIODOUT bit 3 is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When IOPOE bit 3 is 1:
- If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low.
- If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When IOPOE bit 3 is 0:
- If GPIODOUT bit 3 is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 3 is 1: AUXIO[8i+3] is driven high.

When IOPOE bit 3 is 1:
- If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high.
RW 0b00
5:4 IO2 Select mode for AUXIO[8i+2].
Value ENUM Name Description
0x0 OUT Output Mode:

When IOPOE bit 2 is 0: GPIODOUT bit 2 drives AUXIO[8i+2].

When IOPOE bit 2 is 1: The signal selected by IO2PSEL.SRC drives AUXIO[8i+2].
0x1 IN Input Mode:

When GPIODIE bit 2 is 0: AUXIO[8i+2] is enabled for analog signal transfer.

When GPIODIE bit 2 is 1: AUXIO[8i+2] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When IOPOE bit 2 is 0:
- If GPIODOUT bit 2 is 0: AUXIO[8i+2] is driven low.
- If GPIODOUT bit 2 is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When IOPOE bit 2 is 1:
- If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is driven low.
- If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When IOPOE bit 2 is 0:
- If GPIODOUT bit 2 is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 2 is 1: AUXIO[8i+2] is driven high.

When IOPOE bit 2 is 1:
- If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is driven high.
RW 0b00
3:2 IO1 Select mode for AUXIO[8i+1].
Value ENUM Name Description
0x0 OUT Output Mode:

When IOPOE bit 1 is 0: GPIODOUT bit 1 drives AUXIO[8i+1].

When IOPOE bit 1 is 1: The signal selected by IO1PSEL.SRC drives AUXIO[8i+1].
0x1 IN Input Mode:

When GPIODIE bit 1 is 0: AUXIO[8i+1] is enabled for analog signal transfer.

When GPIODIE bit 1 is 1: AUXIO[8i+1] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When IOPOE bit 1 is 0:
- If GPIODOUT bit 1 is 0: AUXIO[8i+1] is driven low.
- If GPIODOUT bit 1 is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When IOPOE bit 1 is 1:
- If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is driven low.
- If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When IOPOE bit 1 is 0:
- If GPIODOUT bit 1 is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 1 is 1: AUXIO[8i+1] is driven high.

When IOPOE bit 1 is 1:
- If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is driven high.
RW 0b00
1:0 IO0 Select mode for AUXIO[8i+0].
Value ENUM Name Description
0x0 OUT Output Mode:

When IOPOE bit 0 is 0: GPIODOUT bit 0 drives AUXIO[8i+0].

When IOPOE bit 0 is 1: The signal selected by IO0PSEL.SRC drives AUXIO[8i+0].
0x1 IN Input Mode:

When GPIODIE bit 0 is 0: AUXIO[8i+0] is enabled for analog signal transfer.

When GPIODIE bit 0 is 1: AUXIO[8i+0] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When IOPOE bit 0 is 0:
- If GPIODOUT bit 0 is 0: AUXIO[8i+0] is driven low.
- If GPIODOUT bit 0 is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When IOPOE bit 0 is 1:
- If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low.
- If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When IOPOE bit 0 is 0:
- If GPIODOUT bit 0 is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 0 is 1: AUXIO[8i+0] is driven high.

When IOPOE bit 0 is 1:
- If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high.
RW 0b00

TOP:AUX_AIODIO3:GPIODIE

Address Offset 0x0000 0004
Physical Address 0x400C F004 Instance 0x400C F004
Description General Purpose Input Output Digital Input Enable

This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 IO7_0 Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n].
Write 0 to bit index n in this bit vector to disable digital input buffer for AUXIO[8i+n].

You must enable the digital input buffer for AUXIO[8i+n] to read the pin value in GPIODIN.
You must disable the digital input buffer for analog input or pins that float to avoid current leakage.		 RW 0x00

TOP:AUX_AIODIO3:IOPOE

Address Offset 0x0000 0008
Physical Address 0x400C F008 Instance 0x400C F008
Description Input Output Peripheral Output Enable

This register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 IO7_0 Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from source given in IOnPSEL.
Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from bit n in GPIODOUT.		 RW 0x00

TOP:AUX_AIODIO3:GPIODOUT

Address Offset 0x0000 000C
Physical Address 0x400C F00C Instance 0x400C F00C
Description General Purpose Input Output Data Out

The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 IO7_0 Write 1 to bit index n in this bit vector to set AUXIO[8i+n].
Write 0 to bit index n in this bit vector to clear AUXIO[8i+n].

You must clear bit n in IOPOE to connect bit n in this bit vector to AUXIO[8i+n].		 RW 0x00

TOP:AUX_AIODIO3:GPIODIN

Address Offset 0x0000 0010
Physical Address 0x400C F010 Instance 0x400C F010
Description General Purpose Input Output Data In

This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 IO7_0 Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set. Otherwise, bit n is read as 0. RO 0x00

TOP:AUX_AIODIO3:GPIODOUTSET

Address Offset 0x0000 0014
Physical Address 0x400C F014 Instance 0x400C F014
Description General Purpose Input Output Data Out Set

Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 IO7_0 Write 1 to bit index n in this bit vector to set GPIODOUT bit n.

Read value is 0.		 RW 0x00

TOP:AUX_AIODIO3:GPIODOUTCLR

Address Offset 0x0000 0018
Physical Address 0x400C F018 Instance 0x400C F018
Description General Purpose Input Output Data Out Clear

Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 IO7_0 Write 1 to bit index n in this bit vector to clear GPIODOUT bit n.

Read value is 0.		 RW 0x00

TOP:AUX_AIODIO3:GPIODOUTTGL

Address Offset 0x0000 001C
Physical Address 0x400C F01C Instance 0x400C F01C
Description General Purpose Input Output Data Out Toggle

Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 IO7_0 Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n.

Read value is 0.		 RW 0x00

TOP:AUX_AIODIO3:IO0PSEL

Address Offset 0x0000 0020
Physical Address 0x400C F020 Instance 0x400C F020
Description Input Output 0 Peripheral Select

This register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1.

To avoid glitches on AUXIO[8i+0] you must configure this register while IOPOE bit 0 is 0.

In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 SRC Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is set.
Value ENUM Name Description
0x0 AUX_EV_OBS Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
0x1 AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
0x2 AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
0x3 AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
0x4 AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
0x5 AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
0x6 AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
0x7 AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
RW 0b000

TOP:AUX_AIODIO3:IO1PSEL

Address Offset 0x0000 0024
Physical Address 0x400C F024 Instance 0x400C F024
Description Input Output 1 Peripheral Select

This register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1.

To avoid glitches on AUXIO[8i+1] you must configure this register while IOPOE bit 1 is 0.

In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 SRC Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is set.
Value ENUM Name Description
0x0 AUX_EV_OBS Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
0x1 AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
0x2 AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
0x3 AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
0x4 AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
0x5 AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
0x6 AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
0x7 AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
RW 0b000

TOP:AUX_AIODIO3:IO2PSEL

Address Offset 0x0000 0028
Physical Address 0x400C F028 Instance 0x400C F028
Description Input Output 2 Peripheral Select

This register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1.

To avoid glitches on AUXIO[8i+2] you must configure this register while IOPOE bit 2 is 0.

In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 SRC Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is set.
Value ENUM Name Description
0x0 AUX_EV_OBS Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
0x1 AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
0x2 AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
0x3 AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
0x4 AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
0x5 AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
0x6 AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
0x7 AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
RW 0b000

TOP:AUX_AIODIO3:IO3PSEL

Address Offset 0x0000 002C
Physical Address 0x400C F02C Instance 0x400C F02C
Description Input Output 3 Peripheral Select

This register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1.

To avoid glitches on AUXIO[8i+3] you must configure this register while IOPOE bit 3 is 0.

In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 SRC Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is set.
Value ENUM Name Description
0x0 AUX_EV_OBS Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
0x1 AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
0x2 AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
0x3 AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
0x4 AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
0x5 AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
0x6 AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
0x7 AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
RW 0b000

TOP:AUX_AIODIO3:IO4PSEL

Address Offset 0x0000 0030
Physical Address 0x400C F030 Instance 0x400C F030
Description Input Output 4 Peripheral Select

This register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1.

To avoid glitches on AUXIO[8i+4] you must configure this register while IOPOE bit 4 is 0.

In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 SRC Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is set.
Value ENUM Name Description
0x0 AUX_EV_OBS Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
0x1 AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
0x2 AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
0x3 AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
0x4 AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
0x5 AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
0x6 AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
0x7 AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
RW 0b000

TOP:AUX_AIODIO3:IO5PSEL

Address Offset 0x0000 0034
Physical Address 0x400C F034 Instance 0x400C F034
Description Input Output 5 Peripheral Select

This register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1.

To avoid glitches on AUXIO[8i+5] you must configure this register while IOPOE bit 5 is 0.

In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 SRC Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is set.
Value ENUM Name Description
0x0 AUX_EV_OBS Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
0x1 AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
0x2 AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
0x3 AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
0x4 AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
0x5 AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
0x6 AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
0x7 AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
RW 0b000

TOP:AUX_AIODIO3:IO6PSEL

Address Offset 0x0000 0038
Physical Address 0x400C F038 Instance 0x400C F038
Description Input Output 6 Peripheral Select

This register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1.

To avoid glitches on AUXIO[8i+6] you must configure this register while IOPOE bit 6 is 0.

In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 SRC Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is set.
Value ENUM Name Description
0x0 AUX_EV_OBS Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
0x1 AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
0x2 AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
0x3 AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
0x4 AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
0x5 AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
0x6 AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
0x7 AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
RW 0b000

TOP:AUX_AIODIO3:IO7PSEL

Address Offset 0x0000 003C
Physical Address 0x400C F03C Instance 0x400C F03C
Description Input Output 7 Peripheral Select

This register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1.

To avoid glitches on AUXIO[8i+7] you must configure this register while IOPOE bit 7 is 0.

In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 SRC Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is set.
Value ENUM Name Description
0x0 AUX_EV_OBS Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
0x1 AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
0x2 AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
0x3 AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
0x4 AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
0x5 AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
0x6 AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
0x7 AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
RW 0b000

TOP:AUX_AIODIO3:IOMODEL

Address Offset 0x0000 0040
Physical Address 0x400C F040 Instance 0x400C F040
Description Input Output Mode Low

This is an alias register for IOMODE.IO0 thru IOMODE.IO3.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:6 IO3 See IOMODE.IO3. RW 0b00
5:4 IO2 See IOMODE.IO2. RW 0b00
3:2 IO1 See IOMODE.IO1. RW 0b00
1:0 IO0 See IOMODE.IO0. RW 0b00

TOP:AUX_AIODIO3:IOMODEH

Address Offset 0x0000 0044
Physical Address 0x400C F044 Instance 0x400C F044
Description Input Output Mode High

This is an alias register for IOMODE.IO4 thru IOMODE.IO7.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:6 IO7 See IOMODE.IO7. RW 0b00
5:4 IO6 See IOMODE.IO6. RW 0b00
3:2 IO5 See IOMODE.IO5. RW 0b00
1:0 IO4 See IOMODE.IO4. RW 0b00


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