Instance: TRNG
Component: TRNG
Base address: 0x40028000
True Random Number Generator
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RO |
32 |
0x0000 0000 |
0x0000 0000 |
0x4002 8000 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0004 |
0x4002 8004 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0008 |
0x4002 8008 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4002 800C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0010 |
0x4002 8010 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x4002 8014 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4002 8018 |
|
|
RW |
32 |
0x0000 00FF |
0x0000 001C |
0x4002 801C |
|
|
RW |
32 |
0x00FF FFFF |
0x0000 0020 |
0x4002 8020 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4002 8024 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x4002 8028 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x4002 802C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0x4002 8030 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0x4002 8034 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x4002 8038 |
|
|
RO |
32 |
0x0000 0600 |
0x0000 0078 |
0x4002 8078 |
|
|
RO |
32 |
0x0200 B44B |
0x0000 007C |
0x4002 807C |
|
|
RO |
32 |
0x0000 0000 |
0x0000 1FD8 |
0x4002 9FD8 |
|
|
RO |
32 |
0x0000 0020 |
0x0000 1FE0 |
0x4002 9FE0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 1FEC |
0x4002 9FEC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 1FF0 |
0x4002 9FF0 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 1FF8 |
0x4002 9FF8 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x4002 8000 | Instance | 0x4002 8000 |
| Description | Random Number Lower Word Readout Value | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | VALUE_31_0 | LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x4002 8004 | Instance | 0x4002 8004 |
| Description | Random Number Upper Word Readout Value | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | VALUE_63_32 | MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0x4002 8008 | Instance | 0x4002 8008 |
| Description | Interrupt Status | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | NEED_CLOCK | 1: Indicates that the TRNG is busy generating entropy or is in one of its test modes - clocks may not be turned off and the power supply voltage must be kept stable. 0: TRNG is idle and can be shut down |
RO | 0 | ||
| 30:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | SHUTDOWN_OVF | 1: The number of FROs shut down (i.e. the number of '1' bits in the ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. |
RO | 0 | ||
| 0 | RDY | 1: Data are available in OUT0 and OUT1. Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears this bit to '0'. If a new number is already available in the internal register of the TRNG, the number is directly clocked into the result register. In this case the status bit is asserted again, after one clock cycle. |
RO | 0 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0x4002 800C | Instance | 0x4002 800C |
| Description | Interrupt Mask | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | SHUTDOWN_OVF | 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this module. | RW | 0 | ||
| 0 | RDY | 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. | RW | 0 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0x4002 8010 | Instance | 0x4002 8010 |
| Description | Interrupt Flag Clear | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | SHUTDOWN_OVF | 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. | WO | 0 | ||
| 0 | RDY | 1: Clear IRQFLAGSTAT.RDY. | WO | 0 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0x4002 8014 | Instance | 0x4002 8014 |
| Description | Control | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | STARTUP_CYCLES | This field determines the number of samples (between 2^8 and 2^24) taken to gather entropy from the FROs during startup. If the written value of this field is zero, the number of samples is 2^24, otherwise the number of samples equals the written value times 2^8. 0x0000: 2^24 samples 0x0001: 1*2^8 samples 0x0002: 2*2^8 samples 0x0003: 3*2^8 samples ... 0x8000: 32768*2^8 samples 0xC000: 49152*2^8 samples ... 0xFFFF: 65535*2^8 samples This field can only be modified while TRNG_EN is 0. If 1 an update will be ignored. |
RW | 0x0000 | ||
| 15:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 | ||
| 10 | TRNG_EN | 0: Forces all TRNG logic back into the idle state immediately. 1: Starts TRNG, gathering entropy from the FROs for the number of samples determined by STARTUP_CYCLES. |
RW | 0 | ||
| 9:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
| 2 | NO_LFSR_FB | 1: Remove XNOR feedback from the main LFSR, converting it into a normal shift register for the XOR-ed outputs of the FROs (shifting data in on the LSB side). A '1' also forces the LFSR to sample continuously. This bit can only be set to '1' when TEST_MODE is also set to '1' and should not be used for other than test purposes |
RW | 0 | ||
| 1 | TEST_MODE | 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2 registers (the latter are automatically cleared before enabling access) and keeps IRQFLAGSTAT.NEED_CLOCK at '1'. This bit shall not be used unless you need to change the LFSR seed prior to creating a new random value. All other testing is done external to register control. |
RW | 0 | ||
| 0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0x4002 8018 | Instance | 0x4002 8018 |
| Description | Configuration 0 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | MAX_REFILL_CYCLES | This field determines the maximum number of samples (between 2^8 and 2^24) taken to re-generate entropy from the FROs after reading out a 64 bits random number. If the written value of this field is zero, the number of samples is 2^24, otherwise the number of samples equals the written value times 2^8. 0x0000: 2^24 samples 0x0001: 1*2^8 samples 0x0002: 2*2^8 samples 0x0003: 3*2^8 samples ... 0x8000: 32768*2^8 samples 0xC000: 49152*2^8 samples ... 0xFFFF: 65535*2^8 samples This field can only be modified while CTL.TRNG_EN is 0. |
RW | 0x0000 | ||
| 15:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 11:8 | SMPL_DIV | This field directly controls the number of clock cycles between samples taken from the FROs. Default value 0 indicates that samples are taken every clock cycle, maximum value 0xF takes one sample every 16 clock cycles. This field must be set to a value such that the slowest FRO (even under worst-case conditions) has a cycle time less than twice the sample period. This field can only be modified while CTL.TRNG_EN is '0'. |
RW | 0x0 | ||
| 7:0 | MIN_REFILL_CYCLES | This field determines the minimum number of samples (between 2^6 and 2^14) taken to re-generate entropy from the FROs after reading out a 64 bits random number. If the value of this field is zero, the number of samples is fixed to the value determined by the MAX_REFILL_CYCLES field, otherwise the minimum number of samples equals the written value times 64 (which can be up to 2^14). To ensure same entropy in all generated random numbers the value 0 should be used. Then MAX_REFILL_CYCLES controls the minimum refill interval. The number of samples defined here cannot be higher than the number defined by the 'max_refill_cycles' field (i.e. that field takes precedence). No random value will be created if min refill > max refill. This field can only be modified while CTL.TRNG_EN = 0. 0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers have same entropy) 0x01: 1*2^6 samples 0x02: 2*2^6 samples ... 0xFF: 255*2^6 samples |
RW | 0x00 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0x4002 801C | Instance | 0x4002 801C |
| Description | Alarm Control | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | RESERVED30 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 29:24 | SHUTDOWN_CNT | Read-only, indicates the number of '1' bits in ALARMSTOP register. The maximum value equals the number of FROs. |
RW | 0b00 0000 | ||
| 23:21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 20:16 | SHUTDOWN_THR | Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. | RW | 0b0 0000 | ||
| 15:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 7:0 | ALARM_THR | Alarm detection threshold for the repeating pattern detectors on each FRO. An FRO 'alarm event' is declared when a repeating pattern (of up to four samples length) is detected continuously for the number of samples defined by this field's value. Reset value 0xFF should keep the number of 'alarm events' to a manageable level. | RW | 0xFF | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0x4002 8020 | Instance | 0x4002 8020 |
| Description | FRO Enable | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 23:0 | FRO_MASK | Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'. Default state is all '1's to enable all FROs after power-up. Note that they are not actually started up before the CTL.TRNG_EN bit is set to '1'. Bits are automatically forced to '0' here (and cannot be written to '1') while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. |
RW | 0xFF FFFF | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0x4002 8024 | Instance | 0x4002 8024 |
| Description | FRO De-tune Bit | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 23:0 | FRO_MASK | De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run approximately 5% faster. The value of one of these bits may only be changed while the corresponding FRO is turned off (by temporarily writing a '0' in the corresponding bit of the FROEN.FRO_MASK register). |
RW | 0x00 0000 | ||
| Address Offset | 0x0000 0028 | ||
| Physical Address | 0x4002 8028 | Instance | 0x4002 8028 |
| Description | Alarm Event | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 | ||
| 23:0 | FRO_MASK | Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] indicates FRO 'n' experienced an 'alarm event'. | RW | 0x00 0000 | ||
| Address Offset | 0x0000 002C | ||
| Physical Address | 0x4002 802C | Instance | 0x4002 802C |
| Description | Alarm Shutdown | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 23:0 | FRO_FLAGS | Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] indicates FRO 'n' experienced more than one 'alarm event' in quick succession and has been turned off. A '1' in this field forces the corresponding bit in FROEN.FRO_MASK to '0'. | RW | 0x00 0000 | ||
| Address Offset | 0x0000 0030 | ||
| Physical Address | 0x4002 8030 | Instance | 0x4002 8030 |
| Description | LFSR Readout Value | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | LFSR_31_0 | Bits [31:0] of the main entropy accumulation LFSR. Register can only be accessed when CTL.TEST_MODE = 1. Register contents will be cleared to zero before access is enabled. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0034 | ||
| Physical Address | 0x4002 8034 | Instance | 0x4002 8034 |
| Description | LFSR Readout Value | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | LFSR_63_32 | Bits [63:32] of the main entropy accumulation LFSR. Register can only be accessed when CTL.TEST_MODE = 1. Register contents will be cleared to zero before access is enabled. |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0038 | ||
| Physical Address | 0x4002 8038 | Instance | 0x4002 8038 |
| Description | LFSR Readout Value | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 0000 0000 0000 | ||
| 16:0 | LFSR_80_64 | Bits [80:64] of the main entropy accumulation LFSR. Register can only be accessed when CTL.TEST_MODE = 1. Register contents will be cleared to zero before access is enabled. |
RW | 0b0 0000 0000 0000 0000 | ||
| Address Offset | 0x0000 0078 | ||
| Physical Address | 0x4002 8078 | Instance | 0x4002 8078 |
| Description | TRNG Engine Options Information | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | ||
| 11:6 | NR_OF_FROS | Number of FROs implemented in this TRNG, value 24 (decimal). | RO | 0b01 1000 | ||
| 5:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | ||
| Address Offset | 0x0000 007C | ||
| Physical Address | 0x4002 807C | Instance | 0x4002 807C |
| Description | HW Version 0 EIP Number And Core Revision |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RESERVED28 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 27:24 | HW_MAJOR_VER | 4 bits binary encoding of the major hardware revision number. | RO | 0x2 | ||
| 23:20 | HW_MINOR_VER | 4 bits binary encoding of the minor hardware revision number. | RO | 0x0 | ||
| 19:16 | HW_PATCH_LVL | 4 bits binary encoding of the hardware patch level, initial release will carry value zero. | RO | 0x0 | ||
| 15:8 | EIP_NUM_COMPL | Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. | RO | 0xB4 | ||
| 7:0 | EIP_NUM | 8 bits binary encoding of the module number. This TRNG gives 0x4B. | RO | 0x4B | ||
| Address Offset | 0x0000 1FD8 | ||
| Physical Address | 0x4002 9FD8 | Instance | 0x4002 9FD8 |
| Description | Interrupt Status After Masking | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | SHUTDOWN_OVF | Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with IRQFLAGMASK.SHUTDOWN_OVF) | RO | 0 | ||
| 0 | RDY | New random value available (result of IRQFLAGSTAT.RDY AND'ed with IRQFLAGMASK.RDY) | RO | 0 | ||
| Address Offset | 0x0000 1FE0 | ||
| Physical Address | 0x4002 9FE0 | Instance | 0x4002 9FE0 |
| Description | HW Version 1 TRNG Revision Number |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | REV | The revision number of this module is Rev 2.0. | RO | 0x20 | ||
| Address Offset | 0x0000 1FEC | ||
| Physical Address | 0x4002 9FEC | Instance | 0x4002 9FEC |
| Description | Interrupt Set | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RDY | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0000 0000 | ||
| Address Offset | 0x0000 1FF0 | ||
| Physical Address | 0x4002 9FF0 | Instance | 0x4002 9FF0 |
| Description | SW Reset Control | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | RESET | Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 for reset to be completed. | RW | 0 | ||
| Address Offset | 0x0000 1FF8 | ||
| Physical Address | 0x4002 9FF8 | Instance | 0x4002 9FF8 |
| Description | Interrupt Status | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | STAT | TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and IRQFLAGSTAT.RDY | RO | 0 | ||
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