Instance: RFC_PWR
Component: RFC_PWR
Base address: 0x40040000
RF Core Power Management
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0001 |
0x0000 0000 |
0x4004 0000 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x4004 0000 | Instance | 0x4004 0000 |
| Description | RF Core Power Management and Clock Enable | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | ||
| 10 | RFCTRC | Enable clock to the RF Core Tracer (RFCTRC) module. | RW | 0 | ||
| 9 | FSCA | Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) module. | RW | 0 | ||
| 8 | PHA | Enable clock to the Packet Handling Accelerator (PHA) module. | RW | 0 | ||
| 7 | RAT | Enable clock to the Radio Timer (RAT) module. | RW | 0 | ||
| 6 | RFERAM | Enable clock to the RF Engine RAM module. | RW | 0 | ||
| 5 | RFE | Enable clock to the RF Engine (RFE) module. | RW | 0 | ||
| 4 | MDMRAM | Enable clock to the Modem RAM module. | RW | 0 | ||
| 3 | MDM | Enable clock to the Modem (MDM) module. | RW | 0 | ||
| 2 | CPERAM | Enable clock to the Command and Packet Engine (CPE) RAM module. As part of RF Core initialization, set this bit together with CPE bit to enable CPE to boot. | RW | 0 | ||
| 1 | CPE | Enable processor clock (hclk) to the Command and Packet Engine (CPE). As part of RF Core initialization, set this bit together with CPERAM bit to enable CPE to boot. | RW | 0 | ||
| 0 | RFC | Enable essential clocks for the RF Core interface. This includes the interconnect, the radio doorbell DBELL command interface, the power management (PWR) clock control module, and bus clock (sclk) for the CPE. To remove possibility of locking yourself out from the RF Core, this bit can not be cleared. If you need to disable all clocks to the RF Core, see the PRCM:RFCCLKG.CLK_EN register. | RO | 1 | ||
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