Instance: I2C0
Component: I2C
Base address: 0x40002000
I2CMaster/Slave Serial Controler
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4000 2000 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0004 |
0x4000 2004 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0004 |
0x4000 2004 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4000 2008 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4000 200C |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0010 |
0x4000 2010 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0014 |
0x4000 2014 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0018 |
0x4000 2018 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0800 |
0x4000 2800 |
|
|
RO |
32 |
0x0000 0020 |
0x0000 0804 |
0x4000 2804 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0804 |
0x4000 2804 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0808 |
0x4000 2808 |
|
|
RW |
32 |
0x0000 0001 |
0x0000 080C |
0x4000 280C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0810 |
0x4000 2810 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0814 |
0x4000 2814 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0818 |
0x4000 2818 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 081C |
0x4000 281C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0820 |
0x4000 2820 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x4000 2000 | Instance | 0x4000 2000 |
| Description | Slave Own Address This register consists of seven address bits that identify this I2C device on the I2C bus. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||
| 6:0 | OAR | I2C slave own address This field specifies bits a6 through a0 of the slave address. |
RW | 0b000 0000 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x4000 2004 | Instance | 0x4000 2004 |
| Description | Slave Status Note: This register shares address with SCTL, meaning that this register functions as a control register when written, and a status register when read. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | ||
| 2 | FBR | First byte received 0: The first byte has not been received. 1: The first byte following the slave's own address has been received. This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the SDR register. Note: This bit is not used for slave transmit operations. |
RO | 0 | ||
| 1 | TREQ | Transmit request 0: No outstanding transmit request. 1: The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the SDR register. |
RO | 0 | ||
| 0 | RREQ | Receive request 0: No outstanding receive data 1: The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until data has been read from the SDR register. |
RO | 0 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x4000 2004 | Instance | 0x4000 2004 |
| Description | Slave Control Note: This register shares address with SSTAT, meaning that this register functions as a control register when written, and a status register when read. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. | WO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | DA | Device active 0: Disables the I2C slave operation 1: Enables the I2C slave operation |
WO | 0 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0x4000 2008 | Instance | 0x4000 2008 |
| Description | Slave Data This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | DATA | Data for transfer This field contains the data for transfer during a slave receive or transmit operation. When written the register data is used as transmit data. When read, this register returns the last data received. Data is stored until next update, either by a system write for transmit or by an external master for receive. |
RW | 0x00 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0x4000 200C | Instance | 0x4000 200C |
| Description | Slave Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
| 2 | STOPIM | Stop condition interrupt mask 0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt controller. 1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt controller.
|
RW | 0 | |||||||||||
| 1 | STARTIM | Start condition interrupt mask 0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt controller. 1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt controller.
|
RW | 0 | |||||||||||
| 0 | DATAIM | Data interrupt mask 0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt controller. 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt controller. |
RW | 0 | |||||||||||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0x4000 2010 | Instance | 0x4000 2010 |
| Description | Slave Raw Interrupt Status This register shows the unmasked interrupt status. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | ||
| 2 | STOPRIS | Stop condition raw interrupt status 0: No interrupt 1: A Stop condition interrupt is pending. This bit is cleared by writing a 1 to SICR.STOPIC. |
RO | 0 | ||
| 1 | STARTRIS | Start condition raw interrupt status 0: No interrupt 1: A Start condition interrupt is pending. This bit is cleared by writing a 1 to SICR.STARTIC. |
RO | 0 | ||
| 0 | DATARIS | Data raw interrupt status 0: No interrupt 1: A data received or data requested interrupt is pending. This bit is cleared by writing a 1 to the SICR.DATAIC. |
RO | 0 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0x4000 2014 | Instance | 0x4000 2014 |
| Description | Slave Masked Interrupt Status This register show which interrupt is active (based on result from SRIS and SIMR). |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | ||
| 2 | STOPMIS | Stop condition masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked Stop condition interrupt is pending. This bit is cleared by writing a 1 to the SICR.STOPIC. |
RO | 0 | ||
| 1 | STARTMIS | Start condition masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked Start condition interrupt is pending. This bit is cleared by writing a 1 to the SICR.STARTIC. |
RO | 0 | ||
| 0 | DATAMIS | Data masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked data received or data requested interrupt is pending. This bit is cleared by writing a 1 to the SICR.DATAIC. |
RO | 0 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0x4000 2018 | Instance | 0x4000 2018 |
| Description | Slave Interrupt Clear This register clears the raw interrupt SRIS. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0b0 0000 0000 0000 0000 0000 0000 0000 | ||
| 2 | STOPIC | Stop condition interrupt clear Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. |
WO | 0 | ||
| 1 | STARTIC | Start condition interrupt clear Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. |
WO | 0 | ||
| 0 | DATAIC | Data interrupt clear Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. |
WO | 0 | ||
| Address Offset | 0x0000 0800 | ||
| Physical Address | 0x4000 2800 | Instance | 0x4000 2800 |
| Description | Master Salve Address This register contains seven address bits of the slave to be accessed by the master (a6-a0), and an RS bit determining if the next operation is a receive or transmit. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
| 7:1 | SA | I2C master slave address Defines which slave is addressed for the transaction in master mode |
RW | 0b000 0000 | |||||||||||
| 0 | RS | Receive or Send This bit-field specifies if the next operation is a receive (high) or a transmit/send (low) from the addressed slave SA.
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 0804 | ||
| Physical Address | 0x4000 2804 | Instance | 0x4000 2804 |
| Description | Master Status | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||
| 6 | BUSBSY | Bus busy 0: The I2C bus is idle. 1: The I2C bus is busy. The bit changes based on the MCTRL.START and MCTRL.STOP conditions. |
RO | 0 | ||
| 5 | IDLE | I2C idle 0: The I2C controller is not idle. 1: The I2C controller is idle. |
RO | 1 | ||
| 4 | ARBLST | Arbitration lost 0: The I2C controller won arbitration. 1: The I2C controller lost arbitration. |
RO | 0 | ||
| 3 | DATACK_N | Data Was Not Acknowledge 0: The transmitted data was acknowledged. 1: The transmitted data was not acknowledged. |
RO | 0 | ||
| 2 | ADRACK_N | Address Was Not Acknowledge 0: The transmitted address was acknowledged. 1: The transmitted address was not acknowledged. |
RO | 0 | ||
| 1 | ERR | Error 0: No error was detected on the last operation. 1: An error occurred on the last operation. |
RO | 0 | ||
| 0 | BUSY | I2C busy 0: The controller is idle. 1: The controller is busy. When this bit-field is set, the other status bits are not valid. Note: The I2C controller requires four SYSBUS clock cycles to assert the BUSY status after I2C master operation has been initiated through MCTRL register. Hence after programming MCTRL register, application is requested to wait for four SYSBUS clock cycles before issuing a controller status inquiry through MSTAT register. Any prior inquiry would result in wrong status being reported. |
RO | 0 | ||
| Address Offset | 0x0000 0804 | ||
| Physical Address | 0x4000 2804 | Instance | 0x4000 2804 |
| Description | Master Control This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller as stated in MSTAT. When written, the control register configures the I2C controller operation. To generate a single transmit cycle, the I2C Master Slave Address (MSA) register is written with the desired address, the MSA.RS bit is cleared, and this register is written with * ACK=X (0 or 1), * STOP=1, * START=1, * RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the MDR register. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0x000 0000 | |||||||||||
| 3 | ACK | Data acknowledge enable 0: The received data byte is not acknowledged automatically by the master. 1: The received data byte is acknowledged automatically by the master. This bit-field must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter.
|
WO | 0 | |||||||||||
| 2 | STOP | This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. 0: The controller does not generate the Stop condition. 1: The controller generates the Stop condition.
|
WO | 0 | |||||||||||
| 1 | START | This bit-field generates the Start or Repeated Start condition. 0: The controller does not generate the Start condition. 1: The controller generates the Start condition.
|
WO | 0 | |||||||||||
| 0 | RUN | I2C master enable 0: The master is disabled. 1: The master is enabled to transmit or receive data.
|
WO | 0 | |||||||||||
| Address Offset | 0x0000 0808 | ||
| Physical Address | 0x4000 2808 | Instance | 0x4000 2808 |
| Description | Master Data This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | DATA | When Read: Last RX Data is returned When Written: Data is transferred during TX transaction |
RW | 0x00 | ||
| Address Offset | 0x0000 080C | ||
| Physical Address | 0x4000 280C | Instance | 0x4000 280C |
| Description | I2C Master Timer Period This register specifies the period of the SCL clock. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7 | TPR_7 | Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. | RW | 0 | ||
| 6:0 | TPR | SCL clock period This field specifies the period of the SCL clock. SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the timer period register value (range of 1 to 127) SCL_LP is the SCL low period (fixed at 6). SCL_HP is the SCL high period (fixed at 4). CLK_PRD is the system clock period in ns. |
RW | 0b000 0001 | ||
| Address Offset | 0x0000 0810 | ||
| Physical Address | 0x4000 2810 | Instance | 0x4000 2810 |
| Description | Master Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
| 0 | IM | Interrupt mask 0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt controller. 1: The master interrupt is sent to the interrupt controller when the MRIS.RIS is set.
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 0814 | ||
| Physical Address | 0x4000 2814 | Instance | 0x4000 2814 |
| Description | Master Raw Interrupt Status This register show the unmasked interrupt status. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | RIS | Raw interrupt status 0: No interrupt 1: A master interrupt is pending. This bit is cleared by writing 1 to the MICR.IC bit . |
RO | 0 | ||
| Address Offset | 0x0000 0818 | ||
| Physical Address | 0x4000 2818 | Instance | 0x4000 2818 |
| Description | Master Masked Interrupt Status This register show which interrupt is active (based on result from MRIS and MIMR). |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | MIS | Masked interrupt status 0: An interrupt has not occurred or is masked. 1: A master interrupt is pending. This bit is cleared by writing 1 to the MICR.IC bit . |
RO | 0 | ||
| Address Offset | 0x0000 081C | ||
| Physical Address | 0x4000 281C | Instance | 0x4000 281C |
| Description | Master Interrupt Clear This register clears the raw and masked interrupt. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | IC | Interrupt clear Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . Reading this register returns no meaningful data. |
WO | 0 | ||
| Address Offset | 0x0000 0820 | ||
| Physical Address | 0x4000 2820 | Instance | 0x4000 2820 |
| Description | Master Configuration This register configures the mode (Master or Slave) and sets the interface for test mode loopback. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
| 5 | SFE | I2C slave function enable
|
RW | 0 | |||||||||||
| 4 | MFE | I2C master function enable
|
RW | 0 | |||||||||||
| 3:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
| 0 | LPBK | I2C loopback 0: Normal operation 1: Loopback operation (test mode)
|
RW | 0 | |||||||||||
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