CPU_TIPROP

Instance: CPU_TIPROP
Component: CPU_TIPROP
Base address: 0xE00FE000


Cortex-M's TI proprietary registers

TOP:CPU_TIPROP Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

TRACECLKMUX

RW

32

0x0000 0000

0x0000 0FF8

0xE00F EFF8

DYN_CG

RW

32

0x0000 0000

0x0000 0FFC

0xE00F EFFC

TOP:CPU_TIPROP Register Descriptions

TOP:CPU_TIPROP:TRACECLKMUX

Address Offset 0x0000 0FF8
Physical Address 0xE00F EFF8 Instance 0xE00F EFF8
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED Internal. Only to be used through TI provided API. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 TRACECLK_N_SWV Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 SWV Internal. Only to be used through TI provided API.
0x1 TRACECLK Internal. Only to be used through TI provided API.
RW 0

TOP:CPU_TIPROP:DYN_CG

Address Offset 0x0000 0FFC
Physical Address 0xE00F EFFC Instance 0xE00F EFFC
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED Internal. Only to be used through TI provided API. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 DYN_CG Internal. Only to be used through TI provided API. RW 0b00


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