AUX_DDI0

AUX_DDI0_OSC

Instance: AUX_DDI0_OSC
Component: DDI
Base address: 0x400CA000

Digital to Digital Interface
This is a generic module for handling register information between digital core and and digital subchips within the analog domain.
To see the actual contents connected on the analog side, please see:
DDI0: DDI_0_OSC:DDI_0_OSC

TOP:AUX_DDI0_OSC Register Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset	Physical Address
DIR03	RW	32	0x0000 0000	0x0000 0000	0x400C A000
DIR47	RW	32	0x0000 0000	0x0000 0004	0x400C A004
DIR811	RW	32	0x0000 0000	0x0000 0008	0x400C A008
DIR1215	RW	32	0x0000 0000	0x0000 000C	0x400C A00C
DIR1619	RW	32	0x0000 0000	0x0000 0010	0x400C A010
DIR2023	RW	32	0x0000 0000	0x0000 0014	0x400C A014
DIR2427	RW	32	0x0000 0000	0x0000 0018	0x400C A018
DIR2831	RW	32	0x0000 0000	0x0000 001C	0x400C A01C
DIR3235	RW	32	0x0000 0000	0x0000 0020	0x400C A020
DIR3639	RW	32	0x0000 0000	0x0000 0024	0x400C A024
DIR4043	RW	32	0x0000 0000	0x0000 0028	0x400C A028
DIR4447	RW	32	0x0000 0000	0x0000 002C	0x400C A02C
DIR4851	RW	32	0x0000 0000	0x0000 0030	0x400C A030
DIR5255	RW	32	0x0000 0000	0x0000 0034	0x400C A034
DIR5659	RW	32	0x0000 0000	0x0000 0038	0x400C A038
DIR6063	RW	32	0x0000 0000	0x0000 003C	0x400C A03C
SET03	WO	32	0x0000 0000	0x0000 0040	0x400C A040
SET47	WO	32	0x0000 0000	0x0000 0044	0x400C A044
SET811	WO	32	0x0000 0000	0x0000 0048	0x400C A048
SET1215	WO	32	0x0000 0000	0x0000 004C	0x400C A04C
SET1619	WO	32	0x0000 0000	0x0000 0050	0x400C A050
SET2023	WO	32	0x0000 0000	0x0000 0054	0x400C A054
SET2427	WO	32	0x0000 0000	0x0000 0058	0x400C A058
SET2831	WO	32	0x0000 0000	0x0000 005C	0x400C A05C
SET3235	WO	32	0x0000 0000	0x0000 0060	0x400C A060
SET3639	WO	32	0x0000 0000	0x0000 0064	0x400C A064
SET4043	WO	32	0x0000 0000	0x0000 0068	0x400C A068
SET4447	WO	32	0x0000 0000	0x0000 006C	0x400C A06C
SET4851	WO	32	0x0000 0000	0x0000 0070	0x400C A070
SET5255	WO	32	0x0000 0000	0x0000 0074	0x400C A074
SET5659	WO	32	0x0000 0000	0x0000 0078	0x400C A078
SET6063	WO	32	0x0000 0000	0x0000 007C	0x400C A07C
CLR03	WO	32	0x0000 0000	0x0000 0080	0x400C A080
CLR47	WO	32	0x0000 0000	0x0000 0084	0x400C A084
CLR811	WO	32	0x0000 0000	0x0000 0088	0x400C A088
CLR1215	WO	32	0x0000 0000	0x0000 008C	0x400C A08C
CLR1619	WO	32	0x0000 0000	0x0000 0090	0x400C A090
CLR2023	WO	32	0x0000 0000	0x0000 0094	0x400C A094
CLR2427	WO	32	0x0000 0000	0x0000 0098	0x400C A098
CLR2831	WO	32	0x0000 0000	0x0000 009C	0x400C A09C
CLR3235	WO	32	0x0000 0000	0x0000 00A0	0x400C A0A0
CLR3639	WO	32	0x0000 0000	0x0000 00A4	0x400C A0A4
CLR4043	WO	32	0x0000 0000	0x0000 00A8	0x400C A0A8
CLR4447	WO	32	0x0000 0000	0x0000 00AC	0x400C A0AC
CLR4851	WO	32	0x0000 0000	0x0000 00B0	0x400C A0B0
CLR5255	WO	32	0x0000 0000	0x0000 00B4	0x400C A0B4
CLR5659	WO	32	0x0000 0000	0x0000 00B8	0x400C A0B8
CLR6063	WO	32	0x0000 0000	0x0000 00BC	0x400C A0BC
SYNC	RW	32	0x0000 0000	0x0000 00C0	0x400C A0C0
CFG	RW	32	0x0000 0004	0x0000 00C8	0x400C A0C8
MASK4B01	WO	32	0x0000 0000	0x0000 0100	0x400C A100
MASK4B23	WO	32	0x0000 0000	0x0000 0104	0x400C A104
MASK4B45	WO	32	0x0000 0000	0x0000 0108	0x400C A108
MASK4B67	WO	32	0x0000 0000	0x0000 010C	0x400C A10C
MASK4B89	WO	32	0x0000 0000	0x0000 0110	0x400C A110
MASK4B1011	WO	32	0x0000 0000	0x0000 0114	0x400C A114
MASK4B1213	WO	32	0x0000 0000	0x0000 0118	0x400C A118
MASK4B1415	WO	32	0x0000 0000	0x0000 011C	0x400C A11C
MASK4B1617	WO	32	0x0000 0000	0x0000 0120	0x400C A120
MASK4B1819	WO	32	0x0000 0000	0x0000 0124	0x400C A124
MASK4B2021	WO	32	0x0000 0000	0x0000 0128	0x400C A128
MASK4B2223	WO	32	0x0000 0000	0x0000 012C	0x400C A12C
MASK4B2425	WO	32	0x0000 0000	0x0000 0130	0x400C A130
MASK4B2627	WO	32	0x0000 0000	0x0000 0134	0x400C A134
MASK4B2829	WO	32	0x0000 0000	0x0000 0138	0x400C A138
MASK4B3031	WO	32	0x0000 0000	0x0000 013C	0x400C A13C
MASK4B3233	WO	32	0x0000 0000	0x0000 0140	0x400C A140
MASK4B3435	WO	32	0x0000 0000	0x0000 0144	0x400C A144
MASK4B3637	WO	32	0x0000 0000	0x0000 0148	0x400C A148
MASK4B3839	WO	32	0x0000 0000	0x0000 014C	0x400C A14C
MASK4B4041	WO	32	0x0000 0000	0x0000 0150	0x400C A150
MASK4B4243	WO	32	0x0000 0000	0x0000 0154	0x400C A154
MASK4B4445	WO	32	0x0000 0000	0x0000 0158	0x400C A158
MASK4B4647	WO	32	0x0000 0000	0x0000 015C	0x400C A15C
MASK4B4849	WO	32	0x0000 0000	0x0000 0160	0x400C A160
MASK4B5051	WO	32	0x0000 0000	0x0000 0164	0x400C A164
MASK4B5253	WO	32	0x0000 0000	0x0000 0168	0x400C A168
MASK4B5455	WO	32	0x0000 0000	0x0000 016C	0x400C A16C
MASK4B5657	WO	32	0x0000 0000	0x0000 0170	0x400C A170
MASK4B5859	WO	32	0x0000 0000	0x0000 0174	0x400C A174
MASK4B6061	WO	32	0x0000 0000	0x0000 0178	0x400C A178
MASK4B6263	WO	32	0x0000 0000	0x0000 017C	0x400C A17C
MASK8B01	WO	32	0x0000 0000	0x0000 0180	0x400C A180
MASK8B23	WO	32	0x0000 0000	0x0000 0184	0x400C A184
MASK8B45	WO	32	0x0000 0000	0x0000 0188	0x400C A188
MASK8B67	WO	32	0x0000 0000	0x0000 018C	0x400C A18C
MASK8B89	WO	32	0x0000 0000	0x0000 0190	0x400C A190
MASK8B1011	WO	32	0x0000 0000	0x0000 0194	0x400C A194
MASK8B1213	WO	32	0x0000 0000	0x0000 0198	0x400C A198
MASK8B1415	WO	32	0x0000 0000	0x0000 019C	0x400C A19C
MASK8B1617	WO	32	0x0000 0000	0x0000 01A0	0x400C A1A0
MASK8B1819	WO	32	0x0000 0000	0x0000 01A4	0x400C A1A4
MASK8B2021	WO	32	0x0000 0000	0x0000 01A8	0x400C A1A8
MASK8B2223	WO	32	0x0000 0000	0x0000 01AC	0x400C A1AC
MASK8B2425	WO	32	0x0000 0000	0x0000 01B0	0x400C A1B0
MASK8B2627	WO	32	0x0000 0000	0x0000 01B4	0x400C A1B4
MASK8B2829	WO	32	0x0000 0000	0x0000 01B8	0x400C A1B8
MASK8B3031	WO	32	0x0000 0000	0x0000 01BC	0x400C A1BC
MASK8B3233	WO	32	0x0000 0000	0x0000 01C0	0x400C A1C0
MASK8B3435	WO	32	0x0000 0000	0x0000 01C4	0x400C A1C4
MASK8B3637	WO	32	0x0000 0000	0x0000 01C8	0x400C A1C8
MASK8B3839	WO	32	0x0000 0000	0x0000 01CC	0x400C A1CC
MASK8B4041	WO	32	0x0000 0000	0x0000 01D0	0x400C A1D0
MASK8B4243	WO	32	0x0000 0000	0x0000 01D4	0x400C A1D4
MASK8B4445	WO	32	0x0000 0000	0x0000 01D8	0x400C A1D8
MASK8B4647	WO	32	0x0000 0000	0x0000 01DC	0x400C A1DC
MASK8B4849	WO	32	0x0000 0000	0x0000 01E0	0x400C A1E0
MASK8B5051	WO	32	0x0000 0000	0x0000 01E4	0x400C A1E4
MASK8B5253	WO	32	0x0000 0000	0x0000 01E8	0x400C A1E8
MASK8B5455	WO	32	0x0000 0000	0x0000 01EC	0x400C A1EC
MASK8B5657	WO	32	0x0000 0000	0x0000 01F0	0x400C A1F0
MASK8B5859	WO	32	0x0000 0000	0x0000 01F4	0x400C A1F4
MASK8B6061	WO	32	0x0000 0000	0x0000 01F8	0x400C A1F8
MASK8B6263	WO	32	0x0000 0000	0x0000 01FC	0x400C A1FC
MASK16B01	WO	32	0x0000 0000	0x0000 0200	0x400C A200
MASK16B23	WO	32	0x0000 0000	0x0000 0204	0x400C A204
MASK16B45	WO	32	0x0000 0000	0x0000 0208	0x400C A208
MASK16B67	WO	32	0x0000 0000	0x0000 020C	0x400C A20C
MASK16B89	WO	32	0x0000 0000	0x0000 0210	0x400C A210
MASK16B1011	WO	32	0x0000 0000	0x0000 0214	0x400C A214
MASK16B1213	WO	32	0x0000 0000	0x0000 0218	0x400C A218
MASK16B1415	WO	32	0x0000 0000	0x0000 021C	0x400C A21C
MASK16B1617	WO	32	0x0000 0000	0x0000 0220	0x400C A220
MASK16B1819	WO	32	0x0000 0000	0x0000 0224	0x400C A224
MASK16B2021	WO	32	0x0000 0000	0x0000 0228	0x400C A228
MASK16B2223	WO	32	0x0000 0000	0x0000 022C	0x400C A22C
MASK16B2425	WO	32	0x0000 0000	0x0000 0230	0x400C A230
MASK16B2627	WO	32	0x0000 0000	0x0000 0234	0x400C A234
MASK16B2829	WO	32	0x0000 0000	0x0000 0238	0x400C A238
MASK16B3031	WO	32	0x0000 0000	0x0000 023C	0x400C A23C
MASK16B3233	WO	32	0x0000 0000	0x0000 0240	0x400C A240
MASK16B3435	WO	32	0x0000 0000	0x0000 0244	0x400C A244
MASK16B3637	WO	32	0x0000 0000	0x0000 0248	0x400C A248
MASK16B3839	WO	32	0x0000 0000	0x0000 024C	0x400C A24C
MASK16B4041	WO	32	0x0000 0000	0x0000 0250	0x400C A250
MASK16B4243	WO	32	0x0000 0000	0x0000 0254	0x400C A254
MASK16B4445	WO	32	0x0000 0000	0x0000 0258	0x400C A258
MASK16B4647	WO	32	0x0000 0000	0x0000 025C	0x400C A25C
MASK16B4849	WO	32	0x0000 0000	0x0000 0260	0x400C A260
MASK16B5051	WO	32	0x0000 0000	0x0000 0264	0x400C A264
MASK16B5253	WO	32	0x0000 0000	0x0000 0268	0x400C A268
MASK16B5455	WO	32	0x0000 0000	0x0000 026C	0x400C A26C
MASK16B5657	WO	32	0x0000 0000	0x0000 0270	0x400C A270
MASK16B5859	WO	32	0x0000 0000	0x0000 0274	0x400C A274
MASK16B6061	WO	32	0x0000 0000	0x0000 0278	0x400C A278
MASK16B6263	WO	32	0x0000 0000	0x0000 027C	0x400C A27C

TOP:AUX_DDI0_OSC Register Descriptions

TOP:AUX_DDI0_OSC:DIR03

Address Offset	0x0000 0000
Physical Address	0x400C A000	Instance	0x400C A000
Description	Direct Access for DDI Byte Offsets 0 to 3
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 3	RW	0x00
23:16	B2	Direct access to DDI register 2	RW	0x00
15:8	B1	Direct access to DDI register 1	RW	0x00
7:0	B0	Direct access to DDI register 0	RW	0x00

TOP:AUX_DDI0_OSC:DIR47

Address Offset	0x0000 0004
Physical Address	0x400C A004	Instance	0x400C A004
Description	Direct Access for DDI Byte Offsets 4 to 7
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 7	RW	0x00
23:16	B2	Direct access to DDI register 6	RW	0x00
15:8	B1	Direct access to DDI register 5	RW	0x00
7:0	B0	Direct access to DDI register 4	RW	0x00

TOP:AUX_DDI0_OSC:DIR811

Address Offset	0x0000 0008
Physical Address	0x400C A008	Instance	0x400C A008
Description	Direct Access for DDI Byte Offsets 8 to 11
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 11	RW	0x00
23:16	B2	Direct access to DDI register 10	RW	0x00
15:8	B1	Direct access to DDI register 9	RW	0x00
7:0	B0	Direct access to DDI register 8	RW	0x00

TOP:AUX_DDI0_OSC:DIR1215

Address Offset	0x0000 000C
Physical Address	0x400C A00C	Instance	0x400C A00C
Description	Direct Access for DDI Byte Offsets 12 to 15
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 15	RW	0x00
23:16	B2	Direct access to DDI register 14	RW	0x00
15:8	B1	Direct access to DDI register 13	RW	0x00
7:0	B0	Direct access to DDI register 12	RW	0x00

TOP:AUX_DDI0_OSC:DIR1619

Address Offset	0x0000 0010
Physical Address	0x400C A010	Instance	0x400C A010
Description	Direct Access for DDI Byte Offsets 16 to 19
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 19	RW	0x00
23:16	B2	Direct access to DDI register 18	RW	0x00
15:8	B1	Direct access to DDI register 17	RW	0x00
7:0	B0	Direct access to DDI register 16	RW	0x00

TOP:AUX_DDI0_OSC:DIR2023

Address Offset	0x0000 0014
Physical Address	0x400C A014	Instance	0x400C A014
Description	Direct Access for DDI Byte Offsets 20 to 23
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 23	RW	0x00
23:16	B2	Direct access to DDI register 22	RW	0x00
15:8	B1	Direct access to DDI register 21	RW	0x00
7:0	B0	Direct access to DDI register 20	RW	0x00

TOP:AUX_DDI0_OSC:DIR2427

Address Offset	0x0000 0018
Physical Address	0x400C A018	Instance	0x400C A018
Description	Direct Access for DDI Byte Offsets 24 to 27
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 27	RW	0x00
23:16	B2	Direct access to DDI register 26	RW	0x00
15:8	B1	Direct access to DDI register 25	RW	0x00
7:0	B0	Direct access to DDI register 24	RW	0x00

TOP:AUX_DDI0_OSC:DIR2831

Address Offset	0x0000 001C
Physical Address	0x400C A01C	Instance	0x400C A01C
Description	Direct Access for DDI Byte Offsets 28 to 31
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 31	RW	0x00
23:16	B2	Direct access to DDI register 30	RW	0x00
15:8	B1	Direct access to DDI register 29	RW	0x00
7:0	B0	Direct access to DDI register 28	RW	0x00

TOP:AUX_DDI0_OSC:DIR3235

Address Offset	0x0000 0020
Physical Address	0x400C A020	Instance	0x400C A020
Description	Direct Access for DDI Byte Offsets 32 to 35
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 35	RW	0x00
23:16	B2	Direct access to DDI register 34	RW	0x00
15:8	B1	Direct access to DDI register 33	RW	0x00
7:0	B0	Direct access to DDI register 32	RW	0x00

TOP:AUX_DDI0_OSC:DIR3639

Address Offset	0x0000 0024
Physical Address	0x400C A024	Instance	0x400C A024
Description	Direct Access for DDI Byte Offsets 36 to 39
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 39	RW	0x00
23:16	B2	Direct access to DDI register 38	RW	0x00
15:8	B1	Direct access to DDI register 37	RW	0x00
7:0	B0	Direct access to DDI register 36	RW	0x00

TOP:AUX_DDI0_OSC:DIR4043

Address Offset	0x0000 0028
Physical Address	0x400C A028	Instance	0x400C A028
Description	Direct Access for DDI Byte Offsets 40 to 43
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 43	RW	0x00
23:16	B2	Direct access to DDI register 42	RW	0x00
15:8	B1	Direct access to DDI register 41	RW	0x00
7:0	B0	Direct access to DDI register 40	RW	0x00

TOP:AUX_DDI0_OSC:DIR4447

Address Offset	0x0000 002C
Physical Address	0x400C A02C	Instance	0x400C A02C
Description	Direct Access for DDI Byte Offsets 44 to 47
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 47	RW	0x00
23:16	B2	Direct access to DDI register 46	RW	0x00
15:8	B1	Direct access to DDI register 45	RW	0x00
7:0	B0	Direct access to DDI register 44	RW	0x00

TOP:AUX_DDI0_OSC:DIR4851

Address Offset	0x0000 0030
Physical Address	0x400C A030	Instance	0x400C A030
Description	Direct Access for DDI Byte Offsets 48 to 51
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 51	RW	0x00
23:16	B2	Direct access to DDI register 50	RW	0x00
15:8	B1	Direct access to DDI register 49	RW	0x00
7:0	B0	Direct access to DDI register 48	RW	0x00

TOP:AUX_DDI0_OSC:DIR5255

Address Offset	0x0000 0034
Physical Address	0x400C A034	Instance	0x400C A034
Description	Direct Access for DDI Byte Offsets 52 to 55
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 55	RW	0x00
23:16	B2	Direct access to DDI register 54	RW	0x00
15:8	B1	Direct access to DDI register 53	RW	0x00
7:0	B0	Direct access to DDI register 52	RW	0x00

TOP:AUX_DDI0_OSC:DIR5659

Address Offset	0x0000 0038
Physical Address	0x400C A038	Instance	0x400C A038
Description	Direct Access for DDI Byte Offsets 56 to 59
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 59	RW	0x00
23:16	B2	Direct access to DDI register 58	RW	0x00
15:8	B1	Direct access to DDI register 57	RW	0x00
7:0	B0	Direct access to DDI register 56	RW	0x00

TOP:AUX_DDI0_OSC:DIR6063

Address Offset	0x0000 003C
Physical Address	0x400C A03C	Instance	0x400C A03C
Description	Direct Access for DDI Byte Offsets 60 to 63
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	B3	Direct access to DDI register 63	RW	0x00
23:16	B2	Direct access to DDI register 62	RW	0x00
15:8	B1	Direct access to DDI register 61	RW	0x00
7:0	B0	Direct access to DDI register 60	RW	0x00

TOP:AUX_DDI0_OSC:SET03

Address Offset	0x0000 0040
Physical Address	0x400C A040	Instance	0x400C A040
Description	Set for DDI Byte Offsets 0 to 3
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 3. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 2. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 1. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 0. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET47

Address Offset	0x0000 0044
Physical Address	0x400C A044	Instance	0x400C A044
Description	Set for DDI Byte Offsets 4 to 7
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 7. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 6. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 5. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 4. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET811

Address Offset	0x0000 0048
Physical Address	0x400C A048	Instance	0x400C A048
Description	Set for DDI Byte Offsets 8 to 11
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 11. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 10. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 9. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 8. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET1215

Address Offset	0x0000 004C
Physical Address	0x400C A04C	Instance	0x400C A04C
Description	Set for DDI Byte Offsets 12 to 15
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 15. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 14. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 13. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 12. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET1619

Address Offset	0x0000 0050
Physical Address	0x400C A050	Instance	0x400C A050
Description	Set for DDI Byte Offsets 16 to 19
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 19. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 18. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 17. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 16. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET2023

Address Offset	0x0000 0054
Physical Address	0x400C A054	Instance	0x400C A054
Description	Set for DDI Byte Offsets 20 to 23
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 23. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 22. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 21. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 20. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET2427

Address Offset	0x0000 0058
Physical Address	0x400C A058	Instance	0x400C A058
Description	Set for DDI Byte Offsets 24 to 27
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 27. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 26. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 25. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 24. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET2831

Address Offset	0x0000 005C
Physical Address	0x400C A05C	Instance	0x400C A05C
Description	Set for DDI Byte Offsets 28 to 31
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 31. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 30. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 29. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 28. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET3235

Address Offset	0x0000 0060
Physical Address	0x400C A060	Instance	0x400C A060
Description	Set for DDI Byte Offsets 32 to 35
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 35. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 34. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 33. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 32. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET3639

Address Offset	0x0000 0064
Physical Address	0x400C A064	Instance	0x400C A064
Description	Set for DDI Byte Offsets 36 to 39
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 39. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 38. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 37. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 36. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET4043

Address Offset	0x0000 0068
Physical Address	0x400C A068	Instance	0x400C A068
Description	Set for DDI Byte Offsets 40 to 43
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 43. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 42. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 41. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 40. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET4447

Address Offset	0x0000 006C
Physical Address	0x400C A06C	Instance	0x400C A06C
Description	Set for DDI Byte Offsets 44 to 47
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 47. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 46. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 45. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 44. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET4851

Address Offset	0x0000 0070
Physical Address	0x400C A070	Instance	0x400C A070
Description	Set for DDI Byte Offsets 48 to 51
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 51. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 50. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 49. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 48. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET5255

Address Offset	0x0000 0074
Physical Address	0x400C A074	Instance	0x400C A074
Description	Set for DDI Byte Offsets 52 to 55
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 55. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 54. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 53. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 52. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET5659

Address Offset	0x0000 0078
Physical Address	0x400C A078	Instance	0x400C A078
Description	Set for DDI Byte Offsets 56 to 59
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 59. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 58. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 57. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 56. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:SET6063

Address Offset	0x0000 007C
Physical Address	0x400C A07C	Instance	0x400C A07C
Description	Set for DDI Byte Offsets 60 to 63
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will set the corresponding bit in DDI register 63. Read returns 0.	WO	0x00
23:16	S2	A high bit value will set the corresponding bit in DDI register 62. Read returns 0.	WO	0x00
15:8	S1	A high bit value will set the corresponding bit in DDI register 61. Read returns 0.	WO	0x00
7:0	S0	A high bit value will set the corresponding bit in DDI register 60. Read returns 0.	WO	0x00

TOP:AUX_DDI0_OSC:CLR03

Address Offset	0x0000 0080
Physical Address	0x400C A080	Instance	0x400C A080
Description	Clear for DDI Byte Offsets 0 to 3
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 3	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 2	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 1	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 0	WO	0x00

TOP:AUX_DDI0_OSC:CLR47

Address Offset	0x0000 0084
Physical Address	0x400C A084	Instance	0x400C A084
Description	Clear for DDI Byte Offsets 4 to 7
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 7	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 6	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 5	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 4	WO	0x00

TOP:AUX_DDI0_OSC:CLR811

Address Offset	0x0000 0088
Physical Address	0x400C A088	Instance	0x400C A088
Description	Clear for DDI Byte Offsets 8 to 11
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 11	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 10	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 9	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 8	WO	0x00

TOP:AUX_DDI0_OSC:CLR1215

Address Offset	0x0000 008C
Physical Address	0x400C A08C	Instance	0x400C A08C
Description	Clear for DDI Byte Offsets 12 to 15
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 15	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 14	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 13	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 12	WO	0x00

TOP:AUX_DDI0_OSC:CLR1619

Address Offset	0x0000 0090
Physical Address	0x400C A090	Instance	0x400C A090
Description	Clear for DDI Byte Offsets 16 to 19
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 19	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 18	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 17	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 16	WO	0x00

TOP:AUX_DDI0_OSC:CLR2023

Address Offset	0x0000 0094
Physical Address	0x400C A094	Instance	0x400C A094
Description	Clear for DDI Byte Offsets 20 to 23
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 23	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 22	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 21	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 20	WO	0x00

TOP:AUX_DDI0_OSC:CLR2427

Address Offset	0x0000 0098
Physical Address	0x400C A098	Instance	0x400C A098
Description	Clear for DDI Byte Offsets 24 to 27
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 27	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 26	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 25	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 24	WO	0x00

TOP:AUX_DDI0_OSC:CLR2831

Address Offset	0x0000 009C
Physical Address	0x400C A09C	Instance	0x400C A09C
Description	Clear for DDI Byte Offsets 28 to 31
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 31	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 30	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 29	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 28	WO	0x00

TOP:AUX_DDI0_OSC:CLR3235

Address Offset	0x0000 00A0
Physical Address	0x400C A0A0	Instance	0x400C A0A0
Description	Clear for DDI Byte Offsets 32 to 35
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 35	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 34	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 33	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 32	WO	0x00

TOP:AUX_DDI0_OSC:CLR3639

Address Offset	0x0000 00A4
Physical Address	0x400C A0A4	Instance	0x400C A0A4
Description	Clear for DDI Byte Offsets 36 to 39
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 39	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 38	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 37	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 36	WO	0x00

TOP:AUX_DDI0_OSC:CLR4043

Address Offset	0x0000 00A8
Physical Address	0x400C A0A8	Instance	0x400C A0A8
Description	Clear for DDI Byte Offsets 40 to 43
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 43	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 42	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 41	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 40	WO	0x00

TOP:AUX_DDI0_OSC:CLR4447

Address Offset	0x0000 00AC
Physical Address	0x400C A0AC	Instance	0x400C A0AC
Description	Clear for DDI Byte Offsets 44 to 47
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 47	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 46	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 45	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 44	WO	0x00

TOP:AUX_DDI0_OSC:CLR4851

Address Offset	0x0000 00B0
Physical Address	0x400C A0B0	Instance	0x400C A0B0
Description	Clear for DDI Byte Offsets 48 to 51
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 51	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 50	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 49	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 48	WO	0x00

TOP:AUX_DDI0_OSC:CLR5255

Address Offset	0x0000 00B4
Physical Address	0x400C A0B4	Instance	0x400C A0B4
Description	Clear for DDI Byte Offsets 52 to 55
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 55	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 54	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 53	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 52	WO	0x00

TOP:AUX_DDI0_OSC:CLR5659

Address Offset	0x0000 00B8
Physical Address	0x400C A0B8	Instance	0x400C A0B8
Description	Clear for DDI Byte Offsets 56 to 59
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 59	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 58	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 57	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 56	WO	0x00

TOP:AUX_DDI0_OSC:CLR6063

Address Offset	0x0000 00BC
Physical Address	0x400C A0BC	Instance	0x400C A0BC
Description	Clear for DDI Byte Offsets 60 to 63
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	S3	A high bit value will clear the corresponding bit in DDI register 63	WO	0x00
23:16	S2	A high bit value will clear the corresponding bit in DDI register 62	WO	0x00
15:8	S1	A high bit value will clear the corresponding bit in DDI register 61	WO	0x00
7:0	S0	A high bit value will clear the corresponding bit in DDI register 60	WO	0x00

TOP:AUX_DDI0_OSC:SYNC

Address Offset	0x0000 00C0
Physical Address	0x400C A0C0	Instance	0x400C A0C0
Description	Internal. Only to be used through TI provided API.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	RESERVED	Internal. Only to be used through TI provided API.	RO	0b00 0000 0000 0000 0000 0000 0000 0000
1	REQ	Internal. Only to be used through TI provided API.	RW	0
0	ACK	Internal. Only to be used through TI provided API.	RO	0

TOP:AUX_DDI0_OSC:CFG

Address Offset	0x0000 00C8
Physical Address	0x400C A0C8	Instance	0x400C A0C8
Description	Internal. Only to be used through TI provided API.
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	Internal. Only to be used through TI provided API.	RO	0x00 0000
7	LOCK	Internal. Only to be used through TI provided API.	RW	0
6:3	RESERVED2	Internal. Only to be used through TI provided API.	RO	0x0
2	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RW	1
1:0	CLK_DIV	Internal. Only to be used through TI provided API.	RW	0b00

TOP:AUX_DDI0_OSC:MASK4B01

Address Offset	0x0000 0100
Physical Address	0x400C A100	Instance	0x400C A100
Description	Masked Access (4m/4d), Byte Offsets 0 and 1
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 1	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 1, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 1	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 1, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 0	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 0, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 0	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 0, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B23

Address Offset	0x0000 0104
Physical Address	0x400C A104	Instance	0x400C A104
Description	Masked Access (4m/4d), Byte Offsets 2 and 3
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 3	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 3, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 3	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 3, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 2	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 2, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 2	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 2, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B45

Address Offset	0x0000 0108
Physical Address	0x400C A108	Instance	0x400C A108
Description	Masked Access (4m/4d), Byte Offsets 4 and 5
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 5	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 5, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 5	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 5, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 4	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 4, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 4	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 4, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B67

Address Offset	0x0000 010C
Physical Address	0x400C A10C	Instance	0x400C A10C
Description	Masked Access (4m/4d), Byte Offsets 6 and 7
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 7	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 7, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 7	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 7, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 6	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 6, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 6	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 6, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B89

Address Offset	0x0000 0110
Physical Address	0x400C A110	Instance	0x400C A110
Description	Masked Access (4m/4d), Byte Offsets 8 and 9
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 9	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 9, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 9	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 9, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 8	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 8, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 8	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 8, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B1011

Address Offset	0x0000 0114
Physical Address	0x400C A114	Instance	0x400C A114
Description	Masked Access (4m/4d), Byte Offsets 10 and 11
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 11	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 11, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 11	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 11, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 10	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 10, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 10	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 10, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B1213

Address Offset	0x0000 0118
Physical Address	0x400C A118	Instance	0x400C A118
Description	Masked Access (4m/4d), Byte Offsets 12 and 13
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 13	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 13, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 13	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 13, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 12	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 12, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 12	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 12, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B1415

Address Offset	0x0000 011C
Physical Address	0x400C A11C	Instance	0x400C A11C
Description	Masked Access (4m/4d), Byte Offsets 14 and 15
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 15	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 15, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 15	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 15, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 14	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 14, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 14	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 14, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B1617

Address Offset	0x0000 0120
Physical Address	0x400C A120	Instance	0x400C A120
Description	Masked Access (4m/4d), Byte Offsets 16 and 17
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 17	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 17, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 17	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 17, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 16	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 16, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 16	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 16, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B1819

Address Offset	0x0000 0124
Physical Address	0x400C A124	Instance	0x400C A124
Description	Masked Access (4m/4d), Byte Offsets 18 and 19
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 19	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 19, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 19	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 19, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 18	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 18, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 18	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 18, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B2021

Address Offset	0x0000 0128
Physical Address	0x400C A128	Instance	0x400C A128
Description	Masked Access (4m/4d), Byte Offsets 20 and 21
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 21	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 21, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 21	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 21, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 20	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 20, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 20	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 20, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B2223

Address Offset	0x0000 012C
Physical Address	0x400C A12C	Instance	0x400C A12C
Description	Masked Access (4m/4d), Byte Offsets 22 and 23
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 23	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 23, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 23	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 23, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 22	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 22, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 22	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 22, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B2425

Address Offset	0x0000 0130
Physical Address	0x400C A130	Instance	0x400C A130
Description	Masked Access (4m/4d), Byte Offsets 24 and 25
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 25	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 25, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 25	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 25, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 24	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 24, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 24	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 24, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B2627

Address Offset	0x0000 0134
Physical Address	0x400C A134	Instance	0x400C A134
Description	Masked Access (4m/4d), Byte Offsets 26 and 27
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 27	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 27, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 27	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 27, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 26	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 26, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 26	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 26, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B2829

Address Offset	0x0000 0138
Physical Address	0x400C A138	Instance	0x400C A138
Description	Masked Access (4m/4d), Byte Offsets 28 and 29
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 29	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 29, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 29	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 29, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 28	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 28, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 28	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 28, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B3031

Address Offset	0x0000 013C
Physical Address	0x400C A13C	Instance	0x400C A13C
Description	Masked Access (4m/4d), Byte Offsets 30 and 31
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 31	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 31, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 31	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 31, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 30	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 30, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 30	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 30, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B3233

Address Offset	0x0000 0140
Physical Address	0x400C A140	Instance	0x400C A140
Description	Masked Access (4m/4d), Byte Offsets 32 and 33
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 33	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 33, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 33	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 33, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 32	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 32, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 32	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 32, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B3435

Address Offset	0x0000 0144
Physical Address	0x400C A144	Instance	0x400C A144
Description	Masked Access (4m/4d), Byte Offsets 34 and 35
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 35	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 35, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 35	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 35, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 34	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 34, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 34	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 34, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B3637

Address Offset	0x0000 0148
Physical Address	0x400C A148	Instance	0x400C A148
Description	Masked Access (4m/4d), Byte Offsets 36 and 37
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 37	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 37, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 37	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 37, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 36	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 36, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 36	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 36, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B3839

Address Offset	0x0000 014C
Physical Address	0x400C A14C	Instance	0x400C A14C
Description	Masked Access (4m/4d), Byte Offsets 38 and 39
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 39	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 39, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 39	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 39, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 38	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 38, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 38	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 38, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B4041

Address Offset	0x0000 0150
Physical Address	0x400C A150	Instance	0x400C A150
Description	Masked Access (4m/4d), Byte Offsets 40 and 41
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 41	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 41, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 41	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 41, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 40	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 40, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 40	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 40, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B4243

Address Offset	0x0000 0154
Physical Address	0x400C A154	Instance	0x400C A154
Description	Masked Access (4m/4d), Byte Offsets 42 and 43
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 43	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 43, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 43	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 43, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 42	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 42, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 42	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 42, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B4445

Address Offset	0x0000 0158
Physical Address	0x400C A158	Instance	0x400C A158
Description	Masked Access (4m/4d), Byte Offsets 44 and 45
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 45	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 45, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 45	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 45, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 44	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 44, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 44	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 44, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B4647

Address Offset	0x0000 015C
Physical Address	0x400C A15C	Instance	0x400C A15C
Description	Masked Access (4m/4d), Byte Offsets 46 and 47
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 47	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 47, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 47	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 47, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 46	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 46, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 46	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 46, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B4849

Address Offset	0x0000 0160
Physical Address	0x400C A160	Instance	0x400C A160
Description	Masked Access (4m/4d), Byte Offsets 48 and 49
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 49	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 49, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 49	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 49, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 48	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 48, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 48	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 48, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B5051

Address Offset	0x0000 0164
Physical Address	0x400C A164	Instance	0x400C A164
Description	Masked Access (4m/4d), Byte Offsets 50 and 51
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 51	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 51, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 51	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 51, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 50	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 50, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 50	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 50, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B5253

Address Offset	0x0000 0168
Physical Address	0x400C A168	Instance	0x400C A168
Description	Masked Access (4m/4d), Byte Offsets 52 and 53
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 53	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 53, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 53	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 53, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 52	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 52, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 52	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 52, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B5455

Address Offset	0x0000 016C
Physical Address	0x400C A16C	Instance	0x400C A16C
Description	Masked Access (4m/4d), Byte Offsets 54 and 55
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 55	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 55, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 55	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 55, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 54	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 54, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 54	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 54, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B5657

Address Offset	0x0000 0170
Physical Address	0x400C A170	Instance	0x400C A170
Description	Masked Access (4m/4d), Byte Offsets 56 and 57
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 57	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 57, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 57	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 57, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 56	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 56, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 56	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 56, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B5859

Address Offset	0x0000 0174
Physical Address	0x400C A174	Instance	0x400C A174
Description	Masked Access (4m/4d), Byte Offsets 58 and 59
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 59	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 59, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 59	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 59, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 58	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 58, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 58	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 58, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B6061

Address Offset	0x0000 0178
Physical Address	0x400C A178	Instance	0x400C A178
Description	Masked Access (4m/4d), Byte Offsets 60 and 61
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 61	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 61, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 61	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 61, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 60	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 60, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 60	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 60, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK4B6263

Address Offset	0x0000 017C
Physical Address	0x400C A17C	Instance	0x400C A17C
Description	Masked Access (4m/4d), Byte Offsets 62 and 63
Type	WO

Bits	Field Name	Description	Type	Reset
31:28	M1H	Mask for bits [7:4] in DDI register 63	WO	0x0
27:24	D1H	Data for bits [7:4] in DDI register 63, only bits selected by mask M1H will be affected by access	WO	0x0
23:20	M1L	Mask for bits [3:0] in DDI register 63	WO	0x0
19:16	D1L	Data for bits [3:0] in DDI register 63, only bits selected by mask M1L will be affected by access	WO	0x0
15:12	M0H	Mask for bits [7:4] in DDI register 62	WO	0x0
11:8	D0H	Data for bits [7:4] in DDI register 62, only bits selected by mask M0H will be affected by access	WO	0x0
7:4	M0L	Mask for bits [3:0] in DDI register 62	WO	0x0
3:0	D0L	Data for bits [3:0] in DDI register 62, only bits selected by mask M0L will be affected by access	WO	0x0

TOP:AUX_DDI0_OSC:MASK8B01

Address Offset	0x0000 0180
Physical Address	0x400C A180	Instance	0x400C A180
Description	Masked Access (8m/8d), Byte Offsets 0 and 1
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 1	WO	0x00
23:16	D1	Data for DDI register 1, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 0	WO	0x00
7:0	D0	Data for DDI register 0, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B23

Address Offset	0x0000 0184
Physical Address	0x400C A184	Instance	0x400C A184
Description	Masked Access (8m/8d), Byte Offsets 2 and 3
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 3	WO	0x00
23:16	D1	Data for DDI register 3, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 2	WO	0x00
7:0	D0	Data for DDI register 2, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B45

Address Offset	0x0000 0188
Physical Address	0x400C A188	Instance	0x400C A188
Description	Masked Access (8m/8d), Byte Offsets 4 and 5
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 5	WO	0x00
23:16	D1	Data for DDI register 5, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 4	WO	0x00
7:0	D0	Data for DDI register 4, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B67

Address Offset	0x0000 018C
Physical Address	0x400C A18C	Instance	0x400C A18C
Description	Masked Access (8m/8d), Byte Offsets 6 and 7
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 7	WO	0x00
23:16	D1	Data for DDI register 7, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 6	WO	0x00
7:0	D0	Data for DDI register 6, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B89

Address Offset	0x0000 0190
Physical Address	0x400C A190	Instance	0x400C A190
Description	Masked Access (8m/8d), Byte Offsets 8 and 9
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 9	WO	0x00
23:16	D1	Data for DDI register 9, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 8	WO	0x00
7:0	D0	Data for DDI register 8, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B1011

Address Offset	0x0000 0194
Physical Address	0x400C A194	Instance	0x400C A194
Description	Masked Access (8m/8d), Byte Offsets 10 and 11
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 11	WO	0x00
23:16	D1	Data for DDI register 11, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 10	WO	0x00
7:0	D0	Data for DDI register 10, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B1213

Address Offset	0x0000 0198
Physical Address	0x400C A198	Instance	0x400C A198
Description	Masked Access (8m/8d), Byte Offsets 12 and 13
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 13	WO	0x00
23:16	D1	Data for DDI register 13, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 12	WO	0x00
7:0	D0	Data for DDI register 12, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B1415

Address Offset	0x0000 019C
Physical Address	0x400C A19C	Instance	0x400C A19C
Description	Masked Access (8m/8d), Byte Offsets 14 and 15
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 15	WO	0x00
23:16	D1	Data for DDI register 15, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 14	WO	0x00
7:0	D0	Data for DDI register 14, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B1617

Address Offset	0x0000 01A0
Physical Address	0x400C A1A0	Instance	0x400C A1A0
Description	Masked Access (8m/8d), Byte Offsets 16 and 17
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 17	WO	0x00
23:16	D1	Data for DDI register 17, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 16	WO	0x00
7:0	D0	Data for DDI register 16, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B1819

Address Offset	0x0000 01A4
Physical Address	0x400C A1A4	Instance	0x400C A1A4
Description	Masked Access (8m/8d), Byte Offsets 18 and 19
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 19	WO	0x00
23:16	D1	Data for DDI register 19, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 18	WO	0x00
7:0	D0	Data for DDI register 18, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B2021

Address Offset	0x0000 01A8
Physical Address	0x400C A1A8	Instance	0x400C A1A8
Description	Masked Access (8m/8d), Byte Offsets 20 and 21
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 21	WO	0x00
23:16	D1	Data for DDI register 21, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 20	WO	0x00
7:0	D0	Data for DDI register 20, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B2223

Address Offset	0x0000 01AC
Physical Address	0x400C A1AC	Instance	0x400C A1AC
Description	Masked Access (8m/8d), Byte Offsets 22 and 23
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 23	WO	0x00
23:16	D1	Data for DDI register 23, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 22	WO	0x00
7:0	D0	Data for DDI register 22, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B2425

Address Offset	0x0000 01B0
Physical Address	0x400C A1B0	Instance	0x400C A1B0
Description	Masked Access (8m/8d), Byte Offsets 24 and 25
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 25	WO	0x00
23:16	D1	Data for DDI register 25, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 24	WO	0x00
7:0	D0	Data for DDI register 24, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B2627

Address Offset	0x0000 01B4
Physical Address	0x400C A1B4	Instance	0x400C A1B4
Description	Masked Access (8m/8d), Byte Offsets 26 and 27
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 27	WO	0x00
23:16	D1	Data for DDI register 27, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 26	WO	0x00
7:0	D0	Data for DDI register 26, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B2829

Address Offset	0x0000 01B8
Physical Address	0x400C A1B8	Instance	0x400C A1B8
Description	Masked Access (8m/8d), Byte Offsets 28 and 29
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 29	WO	0x00
23:16	D1	Data for DDI register 29, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 28	WO	0x00
7:0	D0	Data for DDI register 28, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B3031

Address Offset	0x0000 01BC
Physical Address	0x400C A1BC	Instance	0x400C A1BC
Description	Masked Access (8m/8d), Byte Offsets 30 and 31
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 31	WO	0x00
23:16	D1	Data for DDI register 31, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 30	WO	0x00
7:0	D0	Data for DDI register 30, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B3233

Address Offset	0x0000 01C0
Physical Address	0x400C A1C0	Instance	0x400C A1C0
Description	Masked Access (8m/8d), Byte Offsets 32 and 33
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 33	WO	0x00
23:16	D1	Data for DDI register 33, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 32	WO	0x00
7:0	D0	Data for DDI register 32, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B3435

Address Offset	0x0000 01C4
Physical Address	0x400C A1C4	Instance	0x400C A1C4
Description	Masked Access (8m/8d), Byte Offsets 34 and 35
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 35	WO	0x00
23:16	D1	Data for DDI register 35, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 34	WO	0x00
7:0	D0	Data for DDI register 34, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B3637

Address Offset	0x0000 01C8
Physical Address	0x400C A1C8	Instance	0x400C A1C8
Description	Masked Access (8m/8d), Byte Offsets 36 and 37
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 37	WO	0x00
23:16	D1	Data for DDI register 37, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 36	WO	0x00
7:0	D0	Data for DDI register 36, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B3839

Address Offset	0x0000 01CC
Physical Address	0x400C A1CC	Instance	0x400C A1CC
Description	Masked Access (8m/8d), Byte Offsets 38 and 39
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 39	WO	0x00
23:16	D1	Data for DDI register 39, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 38	WO	0x00
7:0	D0	Data for DDI register 38, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B4041

Address Offset	0x0000 01D0
Physical Address	0x400C A1D0	Instance	0x400C A1D0
Description	Masked Access (8m/8d), Byte Offsets 40 and 41
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 41	WO	0x00
23:16	D1	Data for DDI register 41, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 40	WO	0x00
7:0	D0	Data for DDI register 40, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B4243

Address Offset	0x0000 01D4
Physical Address	0x400C A1D4	Instance	0x400C A1D4
Description	Masked Access (8m/8d), Byte Offsets 42 and 43
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 43	WO	0x00
23:16	D1	Data for DDI register 43, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 42	WO	0x00
7:0	D0	Data for DDI register 42, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B4445

Address Offset	0x0000 01D8
Physical Address	0x400C A1D8	Instance	0x400C A1D8
Description	Masked Access (8m/8d), Byte Offsets 44 and 45
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 45	WO	0x00
23:16	D1	Data for DDI register 45, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 44	WO	0x00
7:0	D0	Data for DDI register 44, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B4647

Address Offset	0x0000 01DC
Physical Address	0x400C A1DC	Instance	0x400C A1DC
Description	Masked Access (8m/8d), Byte Offsets 46 and 47
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 47	WO	0x00
23:16	D1	Data for DDI register 47, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 46	WO	0x00
7:0	D0	Data for DDI register 46, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B4849

Address Offset	0x0000 01E0
Physical Address	0x400C A1E0	Instance	0x400C A1E0
Description	Masked Access (8m/8d), Byte Offsets 48 and 49
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 49	WO	0x00
23:16	D1	Data for DDI register 49, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 48	WO	0x00
7:0	D0	Data for DDI register 48, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B5051

Address Offset	0x0000 01E4
Physical Address	0x400C A1E4	Instance	0x400C A1E4
Description	Masked Access (8m/8d), Byte Offsets 50 and 51
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 51	WO	0x00
23:16	D1	Data for DDI register 51, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 50	WO	0x00
7:0	D0	Data for DDI register 50, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B5253

Address Offset	0x0000 01E8
Physical Address	0x400C A1E8	Instance	0x400C A1E8
Description	Masked Access (8m/8d), Byte Offsets 52 and 53
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 53	WO	0x00
23:16	D1	Data for DDI register 53, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 52	WO	0x00
7:0	D0	Data for DDI register 52, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B5455

Address Offset	0x0000 01EC
Physical Address	0x400C A1EC	Instance	0x400C A1EC
Description	Masked Access (8m/8d), Byte Offsets 54 and 55
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 55	WO	0x00
23:16	D1	Data for DDI register 55, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 54	WO	0x00
7:0	D0	Data for DDI register 54, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B5657

Address Offset	0x0000 01F0
Physical Address	0x400C A1F0	Instance	0x400C A1F0
Description	Masked Access (8m/8d), Byte Offsets 56 and 57
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 57	WO	0x00
23:16	D1	Data for DDI register 57, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 56	WO	0x00
7:0	D0	Data for DDI register 56, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B5859

Address Offset	0x0000 01F4
Physical Address	0x400C A1F4	Instance	0x400C A1F4
Description	Masked Access (8m/8d), Byte Offsets 58 and 59
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 59	WO	0x00
23:16	D1	Data for DDI register 59, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 58	WO	0x00
7:0	D0	Data for DDI register 58, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B6061

Address Offset	0x0000 01F8
Physical Address	0x400C A1F8	Instance	0x400C A1F8
Description	Masked Access (8m/8d), Byte Offsets 60 and 61
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 61	WO	0x00
23:16	D1	Data for DDI register 61, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 60	WO	0x00
7:0	D0	Data for DDI register 60, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK8B6263

Address Offset	0x0000 01FC
Physical Address	0x400C A1FC	Instance	0x400C A1FC
Description	Masked Access (8m/8d), Byte Offsets 62 and 63
Type	WO

Bits	Field Name	Description	Type	Reset
31:24	M1	Mask for DDI register 63	WO	0x00
23:16	D1	Data for DDI register 63, only bits selected by mask M1 will be affected by access	WO	0x00
15:8	M0	Mask for DDI register 62	WO	0x00
7:0	D0	Data for DDI register 62, only bits selected by mask M0 will be affected by access	WO	0x00

TOP:AUX_DDI0_OSC:MASK16B01

Address Offset	0x0000 0200
Physical Address	0x400C A200	Instance	0x400C A200
Description	Masked Access (16m/16d), Byte Offsets 0 and 1
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 0 and 1	WO	0x0000
15:0	D	Data for DDI register at offsets 0 and 1, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B23

Address Offset	0x0000 0204
Physical Address	0x400C A204	Instance	0x400C A204
Description	Masked Access (16m/16d), Byte Offsets 2 and 3
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 2 and 3	WO	0x0000
15:0	D	Data for DDI register at offsets 2 and 3, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B45

Address Offset	0x0000 0208
Physical Address	0x400C A208	Instance	0x400C A208
Description	Masked Access (16m/16d), Byte Offsets 4 and 5
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 4 and 5	WO	0x0000
15:0	D	Data for DDI register at offsets 4 and 5, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B67

Address Offset	0x0000 020C
Physical Address	0x400C A20C	Instance	0x400C A20C
Description	Masked Access (16m/16d), Byte Offsets 6 and 7
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 6 and 7	WO	0x0000
15:0	D	Data for DDI register at offsets 6 and 7, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B89

Address Offset	0x0000 0210
Physical Address	0x400C A210	Instance	0x400C A210
Description	Masked Access (16m/16d), Byte Offsets 8 and 9
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 8 and 9	WO	0x0000
15:0	D	Data for DDI register at offsets 8 and 9, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B1011

Address Offset	0x0000 0214
Physical Address	0x400C A214	Instance	0x400C A214
Description	Masked Access (16m/16d), Byte Offsets 10 and 11
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 10 and 11	WO	0x0000
15:0	D	Data for DDI register at offsets 10 and 11, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B1213

Address Offset	0x0000 0218
Physical Address	0x400C A218	Instance	0x400C A218
Description	Masked Access (16m/16d), Byte Offsets 12 and 13
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 12 and 13	WO	0x0000
15:0	D	Data for DDI register at offsets 12 and 13, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B1415

Address Offset	0x0000 021C
Physical Address	0x400C A21C	Instance	0x400C A21C
Description	Masked Access (16m/16d), Byte Offsets 14 and 15
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 14 and 15	WO	0x0000
15:0	D	Data for DDI register at offsets 14 and 15, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B1617

Address Offset	0x0000 0220
Physical Address	0x400C A220	Instance	0x400C A220
Description	Masked Access (16m/16d), Byte Offsets 16 and 17
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 16 and 17	WO	0x0000
15:0	D	Data for DDI register at offsets 16 and 17, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B1819

Address Offset	0x0000 0224
Physical Address	0x400C A224	Instance	0x400C A224
Description	Masked Access (16m/16d), Byte Offsets 18 and 19
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 18 and 19	WO	0x0000
15:0	D	Data for DDI register at offsets 18 and 19, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B2021

Address Offset	0x0000 0228
Physical Address	0x400C A228	Instance	0x400C A228
Description	Masked Access (16m/16d), Byte Offsets 20 and 21
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 20 and 21	WO	0x0000
15:0	D	Data for DDI register at offsets 20 and 21, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B2223

Address Offset	0x0000 022C
Physical Address	0x400C A22C	Instance	0x400C A22C
Description	Masked Access (16m/16d), Byte Offsets 22 and 23
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 22 and 23	WO	0x0000
15:0	D	Data for DDI register at offsets 22 and 23, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B2425

Address Offset	0x0000 0230
Physical Address	0x400C A230	Instance	0x400C A230
Description	Masked Access (16m/16d), Byte Offsets 24 and 25
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 24 and 25	WO	0x0000
15:0	D	Data for DDI register at offsets 24 and 25, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B2627

Address Offset	0x0000 0234
Physical Address	0x400C A234	Instance	0x400C A234
Description	Masked Access (16m/16d), Byte Offsets 26 and 27
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 26 and 27	WO	0x0000
15:0	D	Data for DDI register at offsets 26 and 27, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B2829

Address Offset	0x0000 0238
Physical Address	0x400C A238	Instance	0x400C A238
Description	Masked Access (16m/16d), Byte Offsets 28 and 29
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 28 and 29	WO	0x0000
15:0	D	Data for DDI register at offsets 28 and 29, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B3031

Address Offset	0x0000 023C
Physical Address	0x400C A23C	Instance	0x400C A23C
Description	Masked Access (16m/16d), Byte Offsets 30 and 31
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 30 and 31	WO	0x0000
15:0	D	Data for DDI register at offsets 30 and 31, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B3233

Address Offset	0x0000 0240
Physical Address	0x400C A240	Instance	0x400C A240
Description	Masked Access (16m/16d), Byte Offsets 32 and 33
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 32 and 33	WO	0x0000
15:0	D	Data for DDI register at offsets 32 and 33, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B3435

Address Offset	0x0000 0244
Physical Address	0x400C A244	Instance	0x400C A244
Description	Masked Access (16m/16d), Byte Offsets 34 and 35
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 34 and 35	WO	0x0000
15:0	D	Data for DDI register at offsets 34 and 35, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B3637

Address Offset	0x0000 0248
Physical Address	0x400C A248	Instance	0x400C A248
Description	Masked Access (16m/16d), Byte Offsets 36 and 37
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 36 and 37	WO	0x0000
15:0	D	Data for DDI register at offsets 36 and 37, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B3839

Address Offset	0x0000 024C
Physical Address	0x400C A24C	Instance	0x400C A24C
Description	Masked Access (16m/16d), Byte Offsets 38 and 39
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 38 and 39	WO	0x0000
15:0	D	Data for DDI register at offsets 38 and 39, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B4041

Address Offset	0x0000 0250
Physical Address	0x400C A250	Instance	0x400C A250
Description	Masked Access (16m/16d), Byte Offsets 40 and 41
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 40 and 41	WO	0x0000
15:0	D	Data for DDI register at offsets 40 and 41, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B4243

Address Offset	0x0000 0254
Physical Address	0x400C A254	Instance	0x400C A254
Description	Masked Access (16m/16d), Byte Offsets 42 and 43
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 42 and 43	WO	0x0000
15:0	D	Data for DDI register at offsets 42 and 43, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B4445

Address Offset	0x0000 0258
Physical Address	0x400C A258	Instance	0x400C A258
Description	Masked Access (16m/16d), Byte Offsets 44 and 45
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 44 and 45	WO	0x0000
15:0	D	Data for DDI register at offsets 44 and 45, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B4647

Address Offset	0x0000 025C
Physical Address	0x400C A25C	Instance	0x400C A25C
Description	Masked Access (16m/16d), Byte Offsets 46 and 47
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 46 and 47	WO	0x0000
15:0	D	Data for DDI register at offsets 46 and 47, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B4849

Address Offset	0x0000 0260
Physical Address	0x400C A260	Instance	0x400C A260
Description	Masked Access (16m/16d), Byte Offsets 48 and 49
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 48 and 49	WO	0x0000
15:0	D	Data for DDI register at offsets 48 and 49, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B5051

Address Offset	0x0000 0264
Physical Address	0x400C A264	Instance	0x400C A264
Description	Masked Access (16m/16d), Byte Offsets 50 and 51
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 50 and 51	WO	0x0000
15:0	D	Data for DDI register at offsets 50 and 51, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B5253

Address Offset	0x0000 0268
Physical Address	0x400C A268	Instance	0x400C A268
Description	Masked Access (16m/16d), Byte Offsets 52 and 53
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 52 and 53	WO	0x0000
15:0	D	Data for DDI register at offsets 52 and 53, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B5455

Address Offset	0x0000 026C
Physical Address	0x400C A26C	Instance	0x400C A26C
Description	Masked Access (16m/16d), Byte Offsets 54 and 55
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 54 and 55	WO	0x0000
15:0	D	Data for DDI register at offsets 54 and 55, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B5657

Address Offset	0x0000 0270
Physical Address	0x400C A270	Instance	0x400C A270
Description	Masked Access (16m/16d), Byte Offsets 56 and 57
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 56 and 57	WO	0x0000
15:0	D	Data for DDI register at offsets 56 and 57, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B5859

Address Offset	0x0000 0274
Physical Address	0x400C A274	Instance	0x400C A274
Description	Masked Access (16m/16d), Byte Offsets 58 and 59
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 58 and 59	WO	0x0000
15:0	D	Data for DDI register at offsets 58 and 59, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B6061

Address Offset	0x0000 0278
Physical Address	0x400C A278	Instance	0x400C A278
Description	Masked Access (16m/16d), Byte Offsets 60 and 61
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 60 and 61	WO	0x0000
15:0	D	Data for DDI register at offsets 60 and 61, only bits selected by mask M will be affected by access	WO	0x0000

TOP:AUX_DDI0_OSC:MASK16B6263

Address Offset	0x0000 027C
Physical Address	0x400C A27C	Instance	0x400C A27C
Description	Masked Access (16m/16d), Byte Offsets 62 and 63
Type	WO

Bits	Field Name	Description	Type	Reset
31:16	M	Mask for DDI register 62 and 63	WO	0x0000
15:0	D	Data for DDI register at offsets 62 and 63, only bits selected by mask M will be affected by access	WO	0x0000