rl_monitoring.h
1 /****************************************************************************************
2  * FileName : rl_monitoring.h
3  *
4  * Description : This file defines the functions required for Monitoring.
5  *
6  ****************************************************************************************
7  * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com
8  *---------------------------------------------------------------------------------------
9  *
10  * Redistribution and use in source and binary forms, with or without modification,
11  * are permitted provided that the following conditions are met:
12  *
13  * Redistributions of source code must retain the above copyright notice,
14  * this list of conditions and the following disclaimer.
15  *
16  * Redistributions in binary form must reproduce the above copyright notice,
17  * this list of conditions and the following disclaimer in the documentation
18  * and/or other materials provided with the distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of its
21  * contributors may be used to endorse or promote products derived from this
22  * software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  * POSSIBILITY OF SUCH DAMAGE.
35  */
36 
37 /****************************************************************************************
38  * FILE INCLUSION PROTECTION
39  ****************************************************************************************
40  */
41 #ifndef RL_MONITORING_H
42 #define RL_MONITORING_H
43 
44 /******************************************************************************
45  * INCLUDE FILES
46  ******************************************************************************
47  */
48 
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 
56 #define RL_MON_RF_FREQ_CNT (3U)
57 
61 #define RL_NUM_MON_SLICES_MAX (127U)
62 
63 
64 /******************************************************************************
65  * GLOBAL VARIABLES/DATA-TYPES DEFINITIONS
66  ******************************************************************************
67  */
68 
72 typedef struct rlMonDigEnables
73 {
104  rlUInt32_t enMask;
105 #ifndef MMWL_BIG_ENDIAN
106 
112  rlUInt8_t testMode;
116  rlUInt8_t reserved0;
117 #else
118 
121  rlUInt8_t reserved0;
131  rlUInt8_t testMode;
132 #endif
133 
136  rlUInt16_t reserved1;
140  rlUInt32_t reserved2;
142 
146 typedef struct rlDigMonPeriodicConf
147 {
148 #ifndef MMWL_BIG_ENDIAN
149 
155  rlUInt8_t reportMode;
159  rlUInt8_t reserved0;
160 #else
161 
164  rlUInt8_t reserved0;
171  rlUInt8_t reportMode;
172 #endif
173 
176  rlUInt16_t reserved1;
185  rlUInt32_t periodicEnableMask;
189  rlUInt32_t reserved2;
191 
195 typedef struct rlMonAnaEnables
196 {
230  rlUInt32_t enMask;
246  rlUInt32_t ldoVmonScEn;
248 
252 typedef struct rlTempMonConf
253 {
254 #ifndef MMWL_BIG_ENDIAN
255 
261  rlUInt8_t reportMode;
265  rlUInt8_t reserved0;
266 #else
267 
270  rlUInt8_t reserved0;
277  rlUInt8_t reportMode;
278 #endif
279 
287  rlInt16_t anaTempThreshMin;
296  rlInt16_t anaTempThreshMax;
306  rlInt16_t digTempThreshMin;
316  rlInt16_t digTempThreshMax;
327  rlUInt16_t tempDiffThresh;
331  rlUInt32_t reserved1;
335  rlUInt32_t reserved2;
337 
341 typedef struct rlRxGainPhaseMonConf
342 {
343 #ifndef MMWL_BIG_ENDIAN
344 
347  rlUInt8_t profileIndx;
373  rlUInt8_t rfFreqBitMask;
383  rlUInt8_t reportMode;
389  rlUInt8_t txSel;
390 #else
391 
416  rlUInt8_t rfFreqBitMask;
420  rlUInt8_t profileIndx;
426  rlUInt8_t txSel;
436  rlUInt8_t reportMode;
437 #endif
438 
448  rlUInt16_t rxGainAbsThresh;
499  rlInt16_t rxGainMismatchOffsetVal[RL_RX_CNT][RL_MON_RF_FREQ_CNT];
513  rlUInt16_t rxGainPhaseMismatchOffsetVal[RL_RX_CNT][RL_MON_RF_FREQ_CNT];
541  rlUInt16_t reserved0;
543 
547 typedef struct rlRxNoiseMonConf
548 {
549 #ifndef MMWL_BIG_ENDIAN
550 
553  rlUInt8_t profileIndx;
569  rlUInt8_t rfFreqBitMask;
570 #else
571 
586  rlUInt8_t rfFreqBitMask;
590  rlUInt8_t profileIndx;
591 #endif
592 
595  rlUInt16_t reserved0;
596 #ifndef MMWL_BIG_ENDIAN
597 
603  rlUInt8_t reportMode;
607  rlUInt8_t reserved1;
608 #else
609 
612  rlUInt8_t reserved1;
619  rlUInt8_t reportMode;
620 #endif
621 
629  rlUInt16_t noiseThresh;
633  rlUInt32_t reserved2;
635 
639 typedef struct rlRxIfStageMonConf
640 {
641 #ifndef MMWL_BIG_ENDIAN
642 
645  rlUInt8_t profileIndx;
652  rlUInt8_t reportMode;
653 #else
654 
660  rlUInt8_t reportMode;
664  rlUInt8_t profileIndx;
665 #endif
666 
669  rlUInt16_t reserved0;
673  rlUInt16_t reserved1;
682  rlUInt16_t hpfCutoffErrThresh;
683 #ifndef MMWL_BIG_ENDIAN
684 
705 #else
706 
716  rlUInt8_t lpfCutoffStopBandAttenThresh;
726  rlUInt8_t lpfCutoffBandEdgeDroopThresh;
727 #endif
728 
737  rlUInt16_t ifaGainErrThresh;
741  rlUInt32_t reserved2;
743 
747 typedef struct rlTxPowMonConf
748 {
749 #ifndef MMWL_BIG_ENDIAN
750 
753  rlUInt8_t profileIndx;
770  rlUInt8_t rfFreqBitMask;
771 #else
772 
788  rlUInt8_t rfFreqBitMask;
792  rlUInt8_t profileIndx;
793 #endif
794 
797  rlUInt16_t reserved0;
798 #ifndef MMWL_BIG_ENDIAN
799 
804  rlUInt8_t reportMode;
808  rlUInt8_t reserved1;
809 #else
810 
813  rlUInt8_t reserved1;
819  rlUInt8_t reportMode;
820 #endif
821 
829  rlUInt16_t txPowAbsErrThresh;
844  rlUInt16_t reserved2;
845 #ifndef MMWL_BIG_ENDIAN
846 
870  rlUInt8_t reserved3;
871 #else
872 
878  rlInt8_t txPowOffsetValRF2;
885  rlInt8_t txPowOffsetValRF1;
889  rlUInt8_t reserved3;
896  rlInt8_t txPowOffsetValRF3;
897 #endif
899 
900 
904 typedef struct rlAllTxPowMonConf
905 {
919 
923 typedef struct rlTxBallbreakMonConf
924 {
925 #ifndef MMWL_BIG_ENDIAN
926 
932  rlUInt8_t reportMode;
936  rlUInt8_t reserved0;
937 #else
938 
941  rlUInt8_t reserved0;
948  rlUInt8_t reportMode;
949 #endif
950 
957  rlInt16_t txReflCoeffMagThresh;
965  rlUInt32_t monStartFreqConst;
966 #ifndef MMWL_BIG_ENDIAN
967 
973  rlUInt8_t txPowBackOff;
977  rlUInt8_t reserved1;
978 #else
979 
982  rlUInt8_t reserved1;
989  rlUInt8_t txPowBackOff;
990 #endif
991 
994  rlUInt16_t reserved2;
996 
1000 typedef struct rlAllTxBallBreakMonCfg
1001 {
1015 
1019 typedef struct rlTxGainPhaseMismatchMonConf
1020 {
1021 #ifndef MMWL_BIG_ENDIAN
1022 
1028  rlUInt8_t profileIndx;
1045  rlUInt8_t rfFreqBitMask;
1055  rlUInt8_t txEn;
1066  rlUInt8_t rxEn;
1073  rlUInt8_t reportMode;
1096  rlInt8_t monChirpSlope;
1097 #else
1098 
1114  rlUInt8_t rfFreqBitMask;
1121  rlUInt8_t profileIndx;
1132  rlUInt8_t rxEn;
1142  rlUInt8_t txEn;
1165  rlInt8_t monChirpSlope;
1172  rlUInt8_t reportMode;
1173 #endif
1174 
1208  rlUInt16_t txGainMismatchOffsetVal[RL_MON_RF_FREQ_CNT][RL_TX_CNT];
1222  rlUInt16_t txPhaseMismatchOffsetVal[RL_MON_RF_FREQ_CNT][RL_TX_CNT];
1226  rlUInt16_t reserved1;
1230  rlUInt32_t reserved2;
1232 
1236 typedef struct rlSynthFreqMonConf
1237 {
1238 #ifndef MMWL_BIG_ENDIAN
1239 
1242  rlUInt8_t profileIndx;
1249  rlUInt8_t reportMode;
1250 #else
1251 
1257  rlUInt8_t reportMode;
1261  rlUInt8_t profileIndx;
1262 #endif
1263 
1272  rlUInt16_t freqErrThresh;
1273 #ifndef MMWL_BIG_ENDIAN
1274 
1281  rlInt8_t monStartTime;
1298  rlUInt8_t monitorMode;
1308  rlUInt8_t vcoMonEn;
1312  rlUInt8_t reserved1;
1313 #else
1314 
1330  rlUInt8_t monitorMode;
1338  rlInt8_t monStartTime;
1342  rlUInt8_t reserved1;
1352  rlUInt8_t vcoMonEn;
1353 #endif
1354 
1357  rlUInt32_t reserved2;
1359 
1363 typedef struct rlExtAnaSignalsMonConf
1364 {
1365 #ifndef MMWL_BIG_ENDIAN
1366 
1372  rlUInt8_t reportMode;
1376  rlUInt8_t reserved0;
1391  rlUInt8_t signalInpEnables;
1426  rlUInt8_t signalSettlingTime[6U];
1448  rlUInt8_t signalThresh[12U];
1449 #else
1450 
1453  rlUInt8_t reserved0;
1460  rlUInt8_t reportMode;
1475  rlUInt8_t signalBuffEnables;
1490  rlUInt8_t signalInpEnables;
1510  rlUInt8_t signalSettlingTime[6U];
1532  rlUInt8_t signalThresh[12U];
1533 #endif
1534 
1537  rlUInt16_t reserved1;
1541  rlUInt32_t reserved2;
1545  rlUInt32_t reserved3;
1547 
1551 typedef struct rlTxIntAnaSignalsMonConf
1552 {
1553 #ifndef MMWL_BIG_ENDIAN
1554 
1559  rlUInt8_t profileIndx;
1566  rlUInt8_t reportMode;
1567 #else
1568 
1574  rlUInt8_t reportMode;
1580  rlUInt8_t profileIndx;
1581 #endif
1582 
1592  rlUInt32_t reserved1;
1594 
1595 
1599 typedef struct rlAllTxIntAnaSignalsMonConf
1600 {
1614 
1615 typedef struct rlRxIntAnaSignalsMonConf
1616 {
1617 #ifndef MMWL_BIG_ENDIAN
1618 
1623  rlUInt8_t profileIndx;
1630  rlUInt8_t reportMode;
1631 #else
1632 
1638  rlUInt8_t reportMode;
1644  rlUInt8_t profileIndx;
1645 #endif
1646 
1649  rlUInt16_t reserved0;
1653  rlUInt32_t reserved1;
1654 } rlRxIntAnaSignalsMonConf_t;
1655 
1659 typedef struct rlPmClkLoIntAnaSignalsMonConf
1660 {
1661 #ifndef MMWL_BIG_ENDIAN
1662 
1672  rlUInt8_t profileIndx;
1679  rlUInt8_t reportMode;
1680 
1694  rlUInt8_t sync20GSigSel;
1695 
1702 
1709 
1713  rlUInt8_t reserved0;
1714 #else
1715 
1721  rlUInt8_t reportMode;
1732  rlUInt8_t profileIndx;
1733 
1739  rlInt8_t sync20GMinThresh;
1740 
1754  rlUInt8_t sync20GSigSel;
1755 
1759  rlUInt8_t reserved0;
1760 
1766  rlInt8_t sync20GMaxThresh;
1767 #endif
1768 
1771  rlUInt16_t reserved1;
1773 
1777 typedef struct rlGpadcIntAnaSignalsMonConf
1778 {
1779 #ifndef MMWL_BIG_ENDIAN
1780 
1786  rlUInt8_t reportMode;
1790  rlUInt8_t reserved0;
1791 #else
1792 
1795  rlUInt8_t reserved0;
1802  rlUInt8_t reportMode;
1803 #endif
1804 
1807  rlUInt16_t reserved1;
1811  rlUInt32_t reserved2;
1813 
1817 typedef struct rlPllContrlVoltMonConf
1818 {
1819 #ifndef MMWL_BIG_ENDIAN
1820 
1826  rlUInt8_t reportMode;
1830  rlUInt8_t reserved0;
1831 #else
1832 
1835  rlUInt8_t reserved0;
1842  rlUInt8_t reportMode;
1843 #endif
1844 
1874  rlUInt16_t signalEnables;
1878  rlUInt32_t reserved1;
1880 
1884 typedef struct rlDualClkCompMonConf
1885 {
1886 #ifndef MMWL_BIG_ENDIAN
1887 
1893  rlUInt8_t reportMode;
1897  rlUInt8_t reserved0;
1898 #else
1899 
1902  rlUInt8_t reserved0;
1909  rlUInt8_t reportMode;
1910 #endif
1911 
1926  rlUInt16_t dccPairEnables;
1930  rlUInt32_t reserved1;
1932 
1936 typedef struct rlRxSatMonConf
1937 {
1938 #ifndef MMWL_BIG_ENDIAN
1939 
1942  rlUInt8_t profileIndx;
1947  rlUInt8_t satMonSel;
1948 #else
1949 
1953  rlUInt8_t satMonSel;
1957  rlUInt8_t profileIndx;
1958 #endif
1959 
1962  rlUInt16_t reserved0;
1995  rlUInt16_t numSlices;
1996 #ifndef MMWL_BIG_ENDIAN
1997 
2006  rlUInt8_t rxChannelMask;
2010  rlUInt8_t reserved1;
2011 #else
2012 
2015  rlUInt8_t reserved1;
2025  rlUInt8_t rxChannelMask;
2026 #endif
2027 
2030  rlUInt16_t reserved2;
2034  rlUInt32_t reserved3;
2038  rlUInt32_t reserved4;
2040 
2044 typedef struct rlSigImgMonConf
2045 {
2046 #ifndef MMWL_BIG_ENDIAN
2047 
2050  rlUInt8_t profileIndx;
2054  rlUInt8_t numSlices;
2055 #else
2056 
2059  rlUInt8_t numSlices;
2063  rlUInt8_t profileIndx;
2064 #endif
2065 
2085  rlUInt32_t reserved0;
2089  rlUInt32_t reserved1;
2091 
2095 typedef struct rlRxMixInPwrMonConf
2096 {
2097 #ifndef MMWL_BIG_ENDIAN
2098 
2103  rlUInt8_t profileIndx;
2111  rlUInt8_t reportMode;
2122  rlUInt8_t txEnable;
2126  rlUInt8_t reserved0;
2127 #else
2128 
2135  rlUInt8_t reportMode;
2141  rlUInt8_t profileIndx;
2145  rlUInt8_t reserved0;
2156  rlUInt8_t txEnable;
2157 #endif
2158 
2170  rlUInt16_t thresholds;
2174  rlUInt16_t reserved1;
2178  rlUInt32_t reserved2;
2180 
2184 typedef struct rlRfSigImgPowerCqData
2185 {
2189  rlUInt16_t numSlices;
2215  rlUInt16_t sigImgPowerCqVal[RL_NUM_MON_SLICES_MAX];
2217 
2221 typedef struct rlRfRxSaturationCqData
2222 {
2226  rlUInt8_t numSlices;
2254  rlUInt8_t satCqVal[RL_NUM_MON_SLICES_MAX];
2256 
2257 typedef struct rlAnaFaultInj
2258 {
2259 #ifndef MMWL_BIG_ENDIAN
2260 
2263  rlUInt8_t reserved0;
2278  rlUInt8_t rxGainDrop;
2292  rlUInt8_t rxPhInv;
2307  rlUInt8_t rxHighNoise;
2325  rlUInt8_t rxIfStagesFault;
2338  rlUInt8_t rxLoAmpFault;
2352  rlUInt8_t txLoAmpFault;
2366  rlUInt8_t txGainDrop;
2387  rlUInt8_t txPhInv;
2406  rlUInt8_t synthFault;
2420  rlUInt8_t supplyLdoFault;
2431  rlUInt8_t miscFault;
2445  rlUInt8_t miscThreshFault;
2449  rlUInt8_t reserved1;
2450 #else
2451 
2465  rlUInt8_t rxGainDrop;
2469  rlUInt8_t reserved0;
2484  rlUInt8_t rxHighNoise;
2498  rlUInt8_t rxPhInv;
2510  rlUInt8_t rxLoAmpFault;
2528  rlUInt8_t rxIfStagesFault;
2542  rlUInt8_t txGainDrop;
2555  rlUInt8_t txLoAmpFault;
2574  rlUInt8_t synthFault;
2595  rlUInt8_t txPhInv;
2606  rlUInt8_t miscFault;
2620  rlUInt8_t supplyLdoFault;
2624  rlUInt8_t reserved1;
2638  rlUInt8_t miscThreshFault;
2639 #endif
2640 
2643  rlUInt16_t reserved2;
2647  rlUInt16_t reserved3;
2651  rlUInt16_t reserved4;
2652 } rlAnaFaultInj_t;
2653 
2657 typedef struct rlTxPhShiftMonConf
2658 {
2659 #ifndef MMWL_BIG_ENDIAN
2660 
2663  rlUInt8_t profileIndx;
2670  rlUInt8_t reportMode;
2671 #else
2672 
2678  rlUInt8_t reportMode;
2682  rlUInt8_t profileIndx;
2683 #endif
2684 
2687  rlUInt16_t reserved0;
2688 #ifndef MMWL_BIG_ENDIAN
2689 
2699  rlUInt8_t phShifterMonCfg;
2711  rlUInt8_t rxEn;
2734  rlInt8_t monChirpSlope;
2738  rlUInt8_t reserved1;
2749  rlUInt8_t phShifterIncVal1;
2760  rlUInt8_t phShifterIncVal2;
2771  rlUInt8_t phShifterIncVal3;
2782  rlUInt8_t phShifterIncVal4;
2790  rlUInt8_t phShifterMon1;
2798  rlUInt8_t phShifterMon2;
2806  rlUInt8_t phShifterMon3;
2814  rlUInt8_t phShifterMon4;
2815 #else
2816 
2827  rlUInt8_t rxEn;
2838  rlUInt8_t phShifterMonCfg;
2842  rlUInt8_t reserved1;
2865  rlInt8_t monChirpSlope;
2876  rlUInt8_t phShifterIncVal2;
2887  rlUInt8_t phShifterIncVal1;
2898  rlUInt8_t phShifterIncVal4;
2909  rlUInt8_t phShifterIncVal3;
2917  rlUInt8_t phShifterMon2;
2925  rlUInt8_t phShifterMon1;
2933  rlUInt8_t phShifterMon4;
2941  rlUInt8_t phShifterMon3;
2942 #endif
2943 
2962  rlUInt16_t txAmplErrorThresh;
2966  rlUInt32_t reserved2;
2970  rlUInt32_t reserved3;
2972 
2976 typedef struct rlAllTxPhShiftMonConf
2977 {
2991 
3115 /******************************************************************************
3116  * FUNCTION DECLARATIONS
3117  ******************************************************************************
3118  */
3119 
3120 /* Digital Monitoring Configuration */
3121 MMWL_EXPORT rlReturnVal_t rlRfDigMonEnableConfig(rlUInt8_t deviceMap,
3122  rlMonDigEnables_t* data);
3123 
3124 /* Digital Monitoring Periodic Configuration */
3125 MMWL_EXPORT rlReturnVal_t rlRfDigMonPeriodicConfig(rlUInt8_t deviceMap,
3126  rlDigMonPeriodicConf_t* data);
3127 /* Analog Monitoring Configuration */
3128 MMWL_EXPORT rlReturnVal_t rlRfAnaMonConfig(rlUInt8_t deviceMap,
3129  rlMonAnaEnables_t* data);
3130 /* TemperatureSsensor Monitoring Configuration */
3131 MMWL_EXPORT rlReturnVal_t rlRfTempMonConfig(rlUInt8_t deviceMap, rlTempMonConf_t* data);
3132 /* RX Gain and Phase Monitoring Configuration */
3133 MMWL_EXPORT rlReturnVal_t rlRfRxGainPhMonConfig(rlUInt8_t deviceMap,
3134  rlRxGainPhaseMonConf_t* data);
3135 /* RX Noise Monitoring Configuration */
3136 MMWL_EXPORT rlReturnVal_t rlRfRxNoiseMonConfig(rlUInt8_t deviceMap,
3137  rlRxNoiseMonConf_t* data);
3138 /* RX IF Stage Monitoring Configuration */
3139 MMWL_EXPORT rlReturnVal_t rlRfRxIfStageMonConfig(rlUInt8_t deviceMap,
3140  rlRxIfStageMonConf_t* data);
3141 /* TX Power Monitoring Configuration */
3142 MMWL_EXPORT rlReturnVal_t rlRfTxPowrMonConfig(rlUInt8_t deviceMap,
3143  rlAllTxPowMonConf_t *data);
3144 /* TX Ballbreak Monitoring Configuration */
3145 MMWL_EXPORT rlReturnVal_t rlRfTxBallbreakMonConfig(rlUInt8_t deviceMap,
3146  rlAllTxBallBreakMonCfg_t* data);
3147 /* TX Gain Phase Mismatch Monitoring Configuration */
3148 MMWL_EXPORT rlReturnVal_t rlRfTxGainPhaseMismatchMonConfig(rlUInt8_t deviceMap,
3150 /* Synth Freq Monitoring Configuration */
3151 MMWL_EXPORT rlReturnVal_t rlRfSynthFreqMonConfig(rlUInt8_t deviceMap,
3152  rlSynthFreqMonConf_t* data);
3153 /* External Analog Signals Monitoring Configuration */
3154 MMWL_EXPORT rlReturnVal_t rlRfExtAnaSignalsMonConfig(rlUInt8_t deviceMap,
3155  rlExtAnaSignalsMonConf_t* data);
3156 /* TX Internal Analog Signals Monitoring Configuration */
3157 MMWL_EXPORT rlReturnVal_t rlRfTxIntAnaSignalsMonConfig(rlUInt8_t deviceMap,
3159 /* RX Internal Analog Signals Monitoring Configuration */
3160 MMWL_EXPORT rlReturnVal_t rlRfRxIntAnaSignalsMonConfig(rlUInt8_t deviceMap,
3161  rlRxIntAnaSignalsMonConf_t* data);
3162 /* PM, CLK, LO Internal Analog Signals Monitoring Configuration */
3163 MMWL_EXPORT rlReturnVal_t rlRfPmClkLoIntAnaSignalsMonConfig(rlUInt8_t deviceMap,
3165 /* GPADC Internal Analog Signals Monitoring Configuration */
3166 MMWL_EXPORT rlReturnVal_t rlRfGpadcIntAnaSignalsMonConfig(rlUInt8_t deviceMap,
3168 /* PLL Control Voltage Monitoring Configuration */
3169 MMWL_EXPORT rlReturnVal_t rlRfPllContrlVoltMonConfig(rlUInt8_t deviceMap,
3170  rlPllContrVoltMonConf_t* data);
3171 /* Dual Clock Comparator Monitoring Configuration */
3172 MMWL_EXPORT rlReturnVal_t rlRfDualClkCompMonConfig(rlUInt8_t deviceMap,
3173  rlDualClkCompMonConf_t* data);
3174 /* RX Saturation Monitoring Configuration */
3175 MMWL_EXPORT rlReturnVal_t rlRfRxIfSatMonConfig(rlUInt8_t deviceMap,
3176  rlRxSatMonConf_t* data);
3177 /* RX Signal Image band Monitoring Configuration */
3178 MMWL_EXPORT rlReturnVal_t rlRfRxSigImgMonConfig(rlUInt8_t deviceMap,
3179  rlSigImgMonConf_t* data);
3180 /* RX mixer input power monitoring.Configuration */
3181 MMWL_EXPORT rlReturnVal_t rlRfRxMixerInPwrConfig(rlUInt8_t deviceMap,
3182  rlRxMixInPwrMonConf_t* data);
3183 /* Analog fault injection Configuration */
3184 MMWL_EXPORT rlReturnVal_t rlRfAnaFaultInjConfig(rlUInt8_t deviceMap,
3185  rlAnaFaultInj_t* data);
3186 /* TX Phase shifter monitoring Configuration */
3187 MMWL_EXPORT rlReturnVal_t rlRfTxPhShiftMonConfig(rlUInt8_t deviceMap,
3188  rlAllTxPhShiftMonConf_t* data);
3189 
3195 #ifdef __cplusplus
3196 }
3197 #endif
3198 
3199 #endif
3200 /*
3201  * END OF RL_MONITORING_H FILE
3202  */
rlUInt32_t reserved2
Reserved for Future use.
rlInt8_t sync20GMinThresh
Minimum threshold for 20GHz monitoring 1 LSB = 1 dBm Valid Range: -63 to +63 dBm.
rlUInt16_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t reserved0
Reserved for Future use.
rlUInt8_t reserved1
Reserved for Future use.
rlUInt16_t reserved1
Reserved for Future use.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt8_t phShifterIncVal1
Phase shifter monitoring increment value for phase1, the monitoring phase will be incremented by this...
rlUInt8_t testMode
Value Definition 0 Production mode. Latent faults are tested and any failures are reported 1 Char...
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t reserved0
Reserved for Future use.
TX power monitoring configuration.
Internal signals for DCC based clock monitoring configuration.
rlUInt16_t timeSliceNumSamples
This field specifies the number of samples constituting each time slice. The minimum allowed value ...
rlUInt16_t numSlices
Number of (primary + secondary) slices to monitor Valid range: 1 to 127.
Signal and image band energy monitoring configuration.
rlUInt8_t reserved0
Reserved for Future use.
External analog signals monitoring configuration.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt16_t signalEnables
This field indicates the sets of signals which are to be monitored. When each bit in this field is ...
rlUInt16_t primarySliceDuration
It specifies the duration of each (primary) time slice. 1 LSB = 0.16us. Valid range: 4 to floor(A...
rlInt16_t txGainMismatchThresh
The magnitude of difference between measured TX powers across the enabled channels at each enabled ...
RX saturation monitoring configuration.
rlUInt8_t reportMode
Indicates the desired reporting verbosity and threshold usage. Value = 0 Report is sent every monit...
MMWL_EXPORT rlReturnVal_t rlRfTxBallbreakMonConfig(rlUInt8_t deviceMap, rlAllTxBallBreakMonCfg_t *data)
Sets information related to TX ball break detection.
MMWL_EXPORT rlReturnVal_t rlRfAnaMonConfig(rlUInt8_t deviceMap, rlMonAnaEnables_t *data)
This function contains the consolidated configuration of all analog monitoring. The enabled monitorin...
rlUInt32_t enMask
Bit Analog monitoring control 0 TEMPERATURE_MONITOR_EN 1 RX_GAIN_PHASE_MONITOR_EN 2 RX_NOISE_MO...
rlUInt32_t reserved1
Reserved for Future use.
rlUInt32_t reserved3
Reserved for Future use.
rlTxPhShiftMonConf_t * tx2PhShiftMonCfg
Tx-2 Phase shifter monitoring config.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt32_t ldoVmonScEn
LDO short circuit monitoring enable. There are no reports for these monitors. If there is any fault...
rlUInt16_t reserved1
Reserved for Future use.
rlUInt8_t numSlices
Number of (primary + secondary) slices to monitor Valid range: 1 to 127.
rlInt8_t monStartTime
This field determines when the monitoring starts in each chirp relative to the start of the ramp....
rlUInt16_t noiseThresh
The measured RX input referred noise figure at the enabled RF frequencies, for all channels,...
rlUInt8_t reserved1
Reserved for Future use.
rlUInt8_t reserved1
Reserved for Future use.
Digital monitoring latent fault reporting configuration.
rlUInt8_t numSlices
Number of (primary + secondary) slices to monitor Valid range: 1 to 127.
rlUInt8_t profileIndx
This field indicates the profile index for which this configuration applies.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period 1 Report is sent only on a failure 2 ...
MMWL_EXPORT rlReturnVal_t rlRfRxGainPhMonConfig(rlUInt8_t deviceMap, rlRxGainPhaseMonConf_t *data)
This API is to set RX gain and phase monitoring config to device.
rlUInt8_t reserved1
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfRxSigImgMonConfig(rlUInt8_t deviceMap, rlSigImgMonConf_t *data)
Sets information related to signal and image band energy.
rlTxBallbreakMonConf_t * tx0BallBrkMonCfg
Tx ballbreak monitoring config for Tx0.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure (after checking for thresholds) ...
rlUInt8_t phShifterMon4
TXn Phase shifter phase4 monitor value. Bits Phase shift definition b1:0 Reserved (set it to 0b00...
rlInt8_t monChirpSlope
Frequency slope for each monitoring chirp is encoded in 1 bytes (8 bit signed number)....
Internal signals for PLL control voltage monitoring configuration.
rlUInt16_t reserved0
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfRxIfStageMonConfig(rlUInt8_t deviceMap, rlRxIfStageMonConf_t *data)
Sets information related to RX IF filter attenuation monitoring.
rlUInt8_t rfFreqBitMask
This field indicates the exact RF frequencies inside the profile's RF band at which to measure the ...
rlUInt8_t profileIndx
This field indicates the Profile Index for which this configuration applies.
MMWL_EXPORT rlReturnVal_t rlRfTxPhShiftMonConfig(rlUInt8_t deviceMap, rlAllTxPhShiftMonConf_t *data)
Sets information related to TX Phase shifter monitoring.
rlUInt16_t reserved1
Reserved for Future use.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt8_t profileIndx
This field indicates the Profile Index for which this monitoring configuration applies....
rlUInt8_t rxEn
This field indicates the RX channels that should be enabled for TX to RX loopback measurement....
rlTxBallbreakMonConf_t * tx1BallBrkMonCfg
Tx ballbreak monitoring config for Tx1.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t rxGainMismatchErrThresh
The magnitude of difference between measured RX gains across the enabled channels at each enabled R...
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
rlUInt32_t monStartFreqConst
For AWR2243 devices : This field is reserved. Set to 0x0. For xWR6x43 devices : Start frequency of ...
MMWL_EXPORT rlReturnVal_t rlRfSynthFreqMonConfig(rlUInt8_t deviceMap, rlSynthFreqMonConf_t *data)
Sets information related to synthesizer frequency.
rlUInt8_t phShifterIncVal2
Phase shifter monitoring increment value for phase2, the monitoring phase will be incremented by this...
MMWL_EXPORT rlReturnVal_t rlRfDigMonEnableConfig(rlUInt8_t deviceMap, rlMonDigEnables_t *data)
Sets the consolidated configuration of all digital monitoring.
Definition: rl_monitoring.c:93
rlUInt32_t reserved3
Reserved for Future use.
rlUInt8_t txEnable
This field indicates if and which TX channels should be enabled while measuring RX mixer input powe...
rlUInt16_t reserved1
Reserved for Future use.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure(after checking for thresholds) ...
rlUInt32_t reserved2
Reserved for Future use.
rlUInt8_t profileIndx
The RF analog settings corresponding to this profile are used for monitoring the enabled signals,...
rlUInt16_t txPowFlatnessErrThresh
The magnitude of measured TX power flatness error, for each enabled channel, is compared against th...
rlUInt16_t rxGainFlatnessErrThresh
The magnitude of measured RX gain flatness error, for each enabled channel, is compared against thi...
rlUInt8_t rxChannelMask
This field is applicable only for SAT_MON_MODE = 0 Masks RX channels used for monitoring....
rlUInt8_t profileIndx
This field indicates the Profile Index for which this configuration applies.
MMWL_EXPORT rlReturnVal_t rlRfAnaFaultInjConfig(rlUInt8_t deviceMap, rlAnaFaultInj_t *data)
Sets information related to RF fault injection.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt8_t reserved0
Reserved for Future use.
TX Phase shifter monitoring configuration.
rlUInt8_t reserved0
Reserved for Future use.
TX power monitoring configuration.
rlInt32_t rf1rf2FreqDitherLimits
Minimum and maximum offset frequency dither limits for RF1 and RF2, when dither limit selection bit b...
RX noise monitoring configuration.
RX IF stage monitoring configuration.
rlUInt16_t reserved2
Reserved for Future use.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlTxIntAnaSignalsMonConf_t * tx2IntAnaSgnlMonCfg
Internal signals in the Tx-2 path monitoring config.
TX ballbreak monitoring configuration.
rlUInt8_t reserved1
Reserved for Future use.
rlInt8_t sync20GMaxThresh
Maximum threshold for 20GHz monitoring 1 LSB = 1 dBm Valid Range: -63 to +63 dBm.
MMWL_EXPORT rlReturnVal_t rlRfPllContrlVoltMonConfig(rlUInt8_t deviceMap, rlPllContrVoltMonConf_t *data)
Sets information related to APLL and Synthesizer's control voltage signals monitoring.
rlUInt8_t txEn
This field indicates the TX channels that should be compared for gain and phase balance....
Internal signals in the TX path monitoring configuration.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
rlUInt16_t reserved0
Reserved for Future use.
rlUInt8_t lpfCutoffBandEdgeDroopThresh
The LPF band edge droop of RX channels are compared against the corresponding thresholds given in t...
rlUInt8_t monitorMode
This field configures whether this monitor should be done for functional active chirps (mode 0) or ...
rlUInt8_t txPowBackOff
For AWR2243 devices : This field is reserved. Set to 0x0. For xWR6x43 devices : TX Power Backoff se...
rlUInt16_t numSlices
Number of (primary + secondary) time slices to monitor. Valid range: 1 to 127 .
MMWL_EXPORT rlReturnVal_t rlRfRxIfSatMonConfig(rlUInt8_t deviceMap, rlRxSatMonConf_t *data)
Sets information related to RX saturation detector monitoring.
RX ADC and IF saturation information.
rlInt16_t rf3FreqDitherLimits
Minimum and maximum offset frequency dither limits for RF3, when dither limit selection bit b3 of RF_...
rlTxPowMonConf_t * tx1PowrMonCfg
Power Monitoring Configuration for Tx1.
MMWL_EXPORT rlReturnVal_t rlRfTempMonConfig(rlUInt8_t deviceMap, rlTempMonConf_t *data)
This API configure the on chip temperature monitors and report the soft results from the monitor....
TX gain and phase mismatch monitoring configuration.
rlUInt32_t reserved4
Reserved for Future use.
rlTxPhShiftMonConf_t * tx1PhShiftMonCfg
Tx-1 Phase shifter monitoring config.
rlUInt8_t vcoMonEn
This bit mask can be used to enable/disable the monitoring of non-live VCO profiles,...
rlUInt16_t reserved2
Reserved for Future use.
rlUInt16_t freqErrThresh
During the chirp, the error of the measured instantaneous chirp frequency w.r.t. the desired value ...
rlUInt8_t profileIndx
The RF analog settings corresponding to this profile are used for monitoring RX mixer input power u...
rlUInt8_t txSel
Value Definition 0 TX0 is used for generating loopback signal for RX gain measurement 1 TX1 is us...
MMWL_EXPORT rlReturnVal_t rlRfGpadcIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlGpadcIntAnaSignalsMonConf_t *data)
Sets information related to GPADC Internal Analog Signals monitoring.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t reserved1
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfDigMonPeriodicConfig(rlUInt8_t deviceMap, rlDigMonPeriodicConf_t *data)
Sets the consolidated configuration.
TX ballbreak monitoring configuration.
MMWL_EXPORT rlReturnVal_t rlRfExtAnaSignalsMonConfig(rlUInt8_t deviceMap, rlExtAnaSignalsMonConf_t *data)
Sets information related to external DC signals monitoring.
rlUInt16_t txPhaseMismatchThresh
The magnitude of measured TX phase mismatch across the enabled channels at each enabled RF frequenc...
Synthesizer frequency monitoring configuration.
rlUInt8_t phShifterMonCfg
Enable at least two phase settings to measure phase error and to apply threshold in reporting mode 1 ...
Digital monitoring configuration.
Definition: rl_monitoring.h:72
rlUInt16_t hpfCutoffErrThresh
The absolute values of RX IF HPF cutoff percentage frequency errors are compared against the corres...
rlTxIntAnaSignalsMonConf_t * tx1IntAnaSgnlMonCfg
Internal signals in the Tx-1 path monitoring config.
rlUInt8_t rfFreqBitMask
This field indicates the exact RF frequencies inside the profile's RF band at which to measure the ...
rlUInt16_t ifaGainErrThresh
The absolute deviation of RX IFA Gain from the expected gain for each enabled RX channel is compare...
MMWL_EXPORT rlReturnVal_t rlRfPmClkLoIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlPmClkLoIntAnaSignalsMonConf_t *data)
Sets information related to Power Management, Clock generation and LO distribution.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
Internal signals for GPADC monitoring configuration.
TX Phase shifter monitoring configuration.
rlUInt16_t txPhShiftDacMonThresh
The TX phase shifter DAC monitor delta threshold when TX_PS_DAC_MON is Enabled 1 LSB = 1....
rlInt16_t anaTempThreshMax
The temperatures read from near the sensors near the RF analog modules are compared against a maximum...
rlInt8_t txPowOffsetValRF3
For AWR2243 devices : This field is reserved. Set it to 0x0. For xWR6243 devices : The offset value...
rlUInt16_t reserved1
Reserved for Future use.
rlUInt8_t profileIndx
The RF analog settings corresponding to this profile are used for monitoring the enabled signals,...
rlTxIntAnaSignalsMonConf_t * tx0IntAnaSgnlMonCfg
Internal signals in the Tx-0 path monitoring config.
RX mixer input power monitoring configuration.
rlUInt32_t reserved1
Reserved for Future use.
rlUInt8_t satMonSel
01 => Enable only the ADC saturation monitor 11 => Enable both the ADC and IFA1 saturation monitors
rlUInt16_t rxGainAbsThresh
The magnitude of difference between the programmed and measured RX gain for each enabled channel at...
rlUInt32_t reserved3
Reserved for Future use.
rlUInt16_t tempDiffThresh
The maximum difference across temperatures read from all the enabled sensors is compared against this...
MMWL_EXPORT rlReturnVal_t rlRfTxIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlAllTxIntAnaSignalsMonConf_t *data)
Sets information related to TX Internal Analog Signals monitoring.
rlUInt16_t dccPairEnables
This field indicates which pairs of clocks to monitor. When a bit in the field is set to 1,...
MMWL_EXPORT rlReturnVal_t rlRfRxNoiseMonConfig(rlUInt8_t deviceMap, rlRxNoiseMonConf_t *data)
Sets information related to RX noise monitoring.
rlUInt8_t phShifterIncVal3
Phase shifter monitoring increment value for phase3, the monitoring phase will be incremented by this...
rlUInt8_t phShifterMon3
TXn Phase shifter phase3 monitor value. Bits Phase shift definition b1:0 Reserved (set it to 0b00...
rlUInt8_t rfFreqBitMask
This field indicates the exact RF frequencies inside the profile's RF band at which to measure the ...
rlUInt16_t txPowAbsErrThresh
The magnitude of difference between the programmed and measured TX power for each enabled channel a...
rlUInt16_t reserved0
Reserved for Future use.
rlTxBallbreakMonConf_t * tx2BallBrkMonCfg
Tx ballbreak monitoring config for Tx2.
Analog monitoring configuration.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
rlUInt8_t signalBuffEnables
This field indicates the sets of externally fed DC signals which are to be buffered before being fe...
rlInt8_t monChirpSlope
Frequency slope for each monitoring chirp is encoded in 1 bytes (8 bit signed number) For 77GHz Dev...
rlUInt32_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlTxPowMonConf_t * tx2PowrMonCfg
Power Monitoring Configuration for Tx2.
rlUInt8_t rxEn
This field indicates the RX channels that should be enabled for TX to RX loopback measurement....
RX signal and image band energy statistics.
MMWL_EXPORT rlReturnVal_t rlRfRxIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlRxIntAnaSignalsMonConf_t *data)
Sets information related to RX Internal Analog Signals monitoring.
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure(after checking for thresholds) ...
rlInt8_t txPowOffsetValRF2
For AWR2243 devices : This field is reserved. Set it to 0x0. For xWR6243 devices : The offset value...
rlUInt8_t signalInpEnables
This field indicates the sets of externally fed DC signals which are to be monitored using GPADC....
rlUInt32_t periodicEnableMask
Bit Monitoring 0 PERIODIC_CONFG_REGISTER_READ_EN 1 RESERVED 2 DFE_STC_EN 3 FRAME_TIMING_MONIT...
rlInt16_t anaTempThreshMin
The temperatures read from near the sensors near the RF analog modules are compared against a minimum...
Temperature sensor monitoring configuration.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt8_t phShifterMon2
TXn Phase shifter phase2 monitor value. Bits Phase shift definition b1:0 Reserved (set it to 0b00...
rlUInt8_t lpfCutoffStopBandAttenThresh
The LPF stop band attenuation at 2x analog LPF’s band edge with respect to the analog LPF’s band ed...
rlInt16_t digTempThreshMax
The temperatures read from near the sensor near the digital module are compared against a maximum thr...
Internal signals in the TX path monitoring configuration.
rlUInt16_t rxGainPhaseMismatchErrThresh
The magnitude of measured RX phase mismatch across the enabled channels at each enabled RF frequenc...
Internal signals for PM, CLK and LO monitoring configuration.
rlUInt8_t sync20GSigSel
Value Definition 0 20GHz SYNC monitoring disabled 1 FMCW_SYNC_IN monitoring enabled 2 FMCW_SYNC...
MMWL_EXPORT rlReturnVal_t rlRfDualClkCompMonConfig(rlUInt8_t deviceMap, rlDualClkCompMonConf_t *data)
Sets information related to the DCC based clock frequency monitoring.
rlTxPowMonConf_t * tx0PowrMonCfg
Power Monitoring Configuration for Tx0.
rlTxPhShiftMonConf_t * tx0PhShiftMonCfg
Tx-0 Phase shifter monitoring config.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
rlInt8_t txPowOffsetValRF1
For AWR2243 devices : This field is reserved. Set it to 0x0. For xWR6243 devices : The offset value...
rlUInt16_t txPhaseErrorThresh
The threshold for deviation of the TX output phase difference between the measured phase values and c...
rlUInt8_t reserved1
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfTxGainPhaseMismatchMonConfig(rlUInt8_t deviceMap, rlTxGainPhaseMismatchMonConf_t *data)
Sets information related to TX gain and phase mismatch monitoring.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure (after checking for thresholds) ...
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t thresholds
The measured RX mixer input voltage swings during this monitoring is compared against the minimum a...
RX gain and phase monitoring configuration.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure (after checking for thresholds) ...
rlUInt16_t reserved1
Reserved for Future use.
rlInt16_t digTempThreshMin
The temperatures read from near the sensor near the digital module are compared against a minimum thr...
rlUInt8_t phShifterMon1
TXn Phase shifter phase1 monitor value. Bits Phase shift definition b1:0 Reserved (set it to 0b00...
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt16_t reserved2
Reserved for Future use.
rlUInt16_t reserved1
Reserved for Future use.
rlUInt32_t reserved1
Reserved for Future use.
rlUInt8_t reserved3
Reserved for Future use.
rlUInt8_t phShifterIncVal4
Phase shifter monitoring increment value for phase4, the monitoring phase will be incremented by this...
rlUInt8_t rfFreqBitMask
This field indicates the RF frequencies inside the profile's RF band at which to measure the required...
rlUInt32_t reserved1
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfTxPowrMonConfig(rlUInt8_t deviceMap, rlAllTxPowMonConf_t *data)
Sets information related to TX power monitoring.
rlUInt16_t txAmplErrorThresh
The threshold for deviation of the TX output amplitude difference between all enabled phase settings....
rlUInt32_t enMask
Bit: Dig Monitoring 0 Reserved 1 CR4 and VIM lockstep test of diagnostic 2 Reserved 3 VIM tes...
rlUInt32_t reserved1
Reserved for Future use.

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