PRU ICSS EtherCAT Release Notes

Updated : November 2018

Overview

The PRU-ICSS EtherCAT package provides the foundation that facilitate application software development for EtherCAT Slave on TI Sitara Embedded Processors with PRU-ICSS HW IP


Licensing

Please refer to the software manifest, which outlines the licensing status for all packages included in this release. The manifest can be found on the SDK download page or in the installed directory as indicated below.


Standard Compliance

Compliant to ETG.1000 V1.0.2 Spec

Documentation

  • Software Developer Guide: Provides information on features, functions, delivery package and, compile tools for the release. This also provides detailed information regarding software elements and software infrastructure to allow developers to start creating applications.
  • Getting Started Guide: provides information on getting the software and running basic examples/demonstrations bundled in the package.
  • User Guide: Provides basic information on the applications
  • Software Manifest: Provides license information on software included in the package. This document is in the release at the root directory of the package
  • EVM Quick Start Guide: Provides information on hardware setup and running the demonstration application that is loaded on flash. This document is provided as part of the EVM kit.

Release 01.00.07

Released November 2018

System Requirements

System Requirements

What’s New

  • PRU-ICSS EtherCAT Slave Software (100M MII) support for AM654x SoC
  • CiA402 Drive Profile support for Single chip drive application
  • Bug Fixes

Features Supported

  • EtherCAT Slave Controller
    • All EtherCAT Commands (NOP, APRD, APWR, APRW, FPRD, FPWR, FPRW, BRD, BWR, BRW, LRD, LWR, LRW, ARMW and FRMW)
    • 8 FMMU support
    • 8 SM support
    • 8KB (AM335x, AMIC11x) / 28KB (AM437x, AMIC12x, AM57xx) / 60KB (K2G, AM654x) of Process Data RAM
    • Distributed clocks
      • 64-bit DC
      • SYNC0 out generation single shot and cyclic mode support
      • SYNC1 out generation - SYNC1 cycle time multiple of SYNC0 cycle time
      • Latch0 and Latch1 inputs
      • System Time PDI control
    • DL Loop Control
      • Using MII_RX_LINK (fast - depending on PHY link loss detection latency) – mandatory for cable redundancy support
      • Using PRU-ICSS MDIO state machine – not recommended for cable redundancy support
    • Interrupts – AL/ECAT events
      • SYNC0, SYNC1 and PDI interrupt events on external SOC pins
    • Watchdog – PDI and SM
    • Error Counters
      • RX Invalid Frame Counter Port 0/1
      • RX ERR Counter Port 0/1
      • Forwarded Error Counter Port 0/1
      • ECAT Processing Unit Error Counter
    • LED – Run, Error and Port0/1 activity based on firmware feedback
      • Controlled via GPIO from Host CPU or PHY directly
    • EEPROM Emulation
      • QSPI flash non-volatile storage support
    • Management Interface for PHY over EtherCAT
    • PHY address configuration and host side PRU-ICSS MDIO API for PHY programming
    • Cable redundancy support
    • Beckhoff EtherCAT Slave Stack Code (SSC) Version 5.12 based evaluation library and example
    • PRU-ICSS EtherCAT TI-ESC SPI Slave mode on AMIC11x and AMIC12x SoC with on chip memory execution support(without DDR)

What is not supported

  • In general, peripherals or features not mentioned as part of “Features Supported” section are not supported in this release.
  • EtherCAT Slave Controller
    • ECAT side register protection when using LRD command
    • APRW/FPRW/BRW for SM mapped area

PRU-ICSS Firmware Revision

Platform Build Firmware Header location
AM335x, AMIC11x 1.4.238 protocols\ethercat_slave\firmware\v1.0
AM437x 2.4.238 protocols\ethercat_slave\firmware\v2.0
AM57xx 3.4.238 protocols\ethercat_slave\firmware\v2.1
K2G 4.4.238 protocols\ethercat_slave\firmware\v2.2
AM654x 5.4.238 protocols\ethercat_slave\firmware\g_v1.0

Fixed Issues

Record ID Platform Details
PINDSW-2735 Sitara, K2G bsp_get_local_sys_time() function ocassionally returns incorrect time when the lower 32-bit wrap around
PINDSW-2963 AMIC11x DDR-less application build fail with PRSDK v5.1
PINDSW-3013 AMIC11x EtherCAT SPI Slave mode application doesnt go to OP state with SYSBIOS v6.73.0.12

Known Issues

This section contains the list of Known Issues at the time of making the release.

Record ID Platform Details Workaround
PINDSW-47 Sitara, K2G Multiple FMMU access in a single datagram to a slave for process data using LRD/LWR commands Use LRW instead of LRD/LWR
PINDSW-72 Sitara, K2G PDI/PD watchdog counter incremented by 1 whenever PDI/PD watchdog is disabled None
PINDSW-74 Sitara, K2G LRD access on unused registers increment WKC - no register protection while using LRD None
PINDSW-141 Sitara, K2G LRW access to non-interleaved input and output process data of multiple slaves does not work. SOEM accesses slaves in LRW mode this way Use LRD/LWR for process data access or use more optimal interleaved access for process data access from Master (TwinCAT way)
PINDSW-1005 AM335x ESC test tool - Errors: some registers which are “Mandatory” read-only are actually writable None
PINDSW-2204 Sitara, K2G Frames with no SFD not counted as errors if received on reverse path None
PINDSW-2360 Sitara, K2G System time of next Sync0 pulse register (0x990:0x993) is not instantaneous, resulting in read of incorrect value if read immediately after sync pulse None
PRSDK-1879 K2G EtherCAT slave application hangs on K2G ICE Board after multiple resets Giving a power cycle to the board resolves the issue. The issue is caused because of I2C bus hanging.

EtherCAT errata for AM57x, AM437x and K2G is the same as AM335x. Please find the details here