diff --git a/examples/ethercat_slave/linker_r5.lds b/examples/ethercat_slave/linker_r5.lds index 63f2834..c04b312 100644 --- a/examples/ethercat_slave/linker_r5.lds +++ b/examples/ethercat_slave/linker_r5.lds @@ -36,63 +36,35 @@ */ /* Linker Settings */ /* Standard linker options */ ---retain="*(.intvecs)" ---retain="*(.intc_text)" ---retain="*(.rstvectors)" ---retain="*(.irqStack)" ---retain="*(.fiqStack)" ---retain="*(.abortStack)" ---retain="*(.undStack)" ---retain="*(.svcStack)" ---fill_value=0 ---stack_size=0x2000 ---heap_size=0x1000 -/*--entry_point=_resetvectors*/ /* Default C RTS boot.asm */ - --stack 0x2000 /* SOFTWARE STACK SIZE */ --heap 0x2000 /* HEAP AREA SIZE */ - -/* Stack Sizes for various modes */ -__IRQ_STACK_SIZE = 0x1000; -__FIQ_STACK_SIZE = 0x1000; -__ABORT_STACK_SIZE = 0x1000; -__UND_STACK_SIZE = 0x1000; -__SVC_STACK_SIZE = 0x1000; +-e __VECS_ENTRY_POINT +--retain="*(.utilsCopyVecsToAtcm)" /*----------------------------------------------------------------------------*/ /* Memory Map */ MEMORY { - VECTORS (X) : origin=0x41C7F000 length=0x1000 - /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */ - RESET_VECTORS (X) : origin=0x41C00000 length=0x100 - /* MCU0_R5F_0 local view */ - MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100 - MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100 - MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000 + /* Refer the user guide for details on persistence of these sections */ + /* Also, when these memories can be used by apps */ + MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100 + MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100 + MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000 - /* MCU0_R5F_1 SoC view */ - MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000 - MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000 + /* Used by SBL, can be used after APPs is started */ + MCU_MSRAM_RSVD_UNUSED (R) : origin=0x41C00000 length=0x200 + MCU_MSRAM_RSVD_SBL (RWIX) : origin=0x41C00200 length=0x3DE00 - /* Fully avaialble for apps. Used by SBL to load SYSFW */ - OCMRAM_LOW (RWIX) : origin=0x41C00100 length=0x40600 - 0x100 /* ~257KB */ + VECTORS (RWIX) : origin=0x41C3E000 length=0x100 + RESET_VECTORS (RWIX) : origin=0x41C3E100 length=0x1000 + OCMRAM (RWIX) : origin=0x41C3F100 length=0x40F00 - /* MCU0 memory used for SBL. Avaiable after boot for app starts for dynamic use */ - SBL_RESERVED (RWIX) : origin=0x41C40600 length=0x60000 - 0x40600 /* ~126KB */ + /* COMPUTE_CLUSTER0_MSMC_SRAM */ + MSMC3 (RWIX) : origin=0x70000000 length=0x100000 /* 1MB */ + MSMC3_HIGH (RWIX) : origin=0x70100000 length=0xEFC00 /* 1MB - 0x10400*/ - /* MCU0 share locations */ - OCMRAM (RWIX) : origin=0x41C60000 length=0x20000 - 0x1000 /* ~124KB */ - - /* AM65XX M4 locations */ - MSMC3 (RWIX) : origin=0x70000000 length=0xF0000 /* 1MB - 64K */ - /* Reserved for DMSC */ - MSMC3_DMSC (RWIX) : origin=0x700F0000 length=0x10000 /* 64K */ - MSMC3_H (RWIX) : origin=0x70100000 length=0xF2000 /* 1MB -56K */ - MSMC3_NOCACHE (RWIX) : origin=0x701F2000 length=0xE000 /* 56K */ - DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */ - -/* Additional memory settings */ + /* The origin and length is determined by board cfg, */ + /* refer user guide for details */ + MSMC3_RSVD_DMSC (RWIX) : origin=0x701F0000 length=0x1000 + DDR0 (RWIX) : origin=0x80000000 length=0x7FFFFFE4 } /* end of MEMORY */ @@ -101,49 +73,36 @@ MEMORY SECTIONS { -/* 'intvecs' and 'intc_text' sections shall be placed within */ -/* a range of +\- 16 MB */ - .intvecs : {} palign(8) > VECTORS - .intc_text : {} palign(8) > VECTORS - .rstvectors : {} palign(8) > RESET_VECTORS - .bootCode : {} palign(8) > MSMC3 - .startupCode : {} palign(8) > MSMC3 - .startupData : {} palign(8) > MSMC3, type = NOINIT - .text : {} palign(8) > MSMC3 - .const : {} palign(8) > MSMC3 - .cinit : {} palign(8) > MSMC3 - .pinit : {} palign(8) > MSMC3 - .bss : {} align(4) > DDR0 /*MSMC3*/ - .far : {} align(4) > DDR0 - .data : {} palign(128) > MSMC3 - .boardcfg_data : {} palign(128) > MSMC3 - .sysmem : {} > MSMC3 - - /* USB ram disk dev-msc example */ - .bss:extMemCache:ramdisk : {} align (32) > DDR0 - - /* UXB host xhci */ - .bss:extMemNonCache:usbXhci : {} align (32) > MSMC3_NOCACHE - - /* USB or any other LLD buffer for benchmarking */ - .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0 - - .stack : {} align(4) > MSMC3 (HIGH) - .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > MSMC3 (HIGH) - RUN_START(__IRQ_STACK_START) - RUN_END(__IRQ_STACK_END) - .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > MSMC3 (HIGH) - RUN_START(__FIQ_STACK_START) - RUN_END(__FIQ_STACK_END) - .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > MSMC3 (HIGH) - RUN_START(__ABORT_STACK_START) - RUN_END(__ABORT_STACK_END) - .undStack : {. = . + __UND_STACK_SIZE;} align(4) > MSMC3 (HIGH) - RUN_START(__UND_STACK_START) - RUN_END(__UND_STACK_END) - .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > MSMC3 (HIGH) - RUN_START(__SVC_STACK_START) - RUN_END(__SVC_STACK_END) + /* Place sysbios entry point - starts */ + .vecs : { *(.vecs) } palign(8) > VECTORS + .vecs : { __VECS_ENTRY_POINT = .; } > VECTORS + + xdc.meta (COPY) : { *(xdc.meta) } > OCMRAM + .init_text : { + boot.*(.text) + *(.text:ti_sysbios_family_arm_MPU_*) + *(.text:ti_sysbios_family_arm_v7r_Cache_*) + } palign(8) > OCMRAM + + .text:xdc_runtime_Startup_reset__I: {} palign(8) > OCMRAM + + .bootCode : {} palign(8) > OCMRAM + .startupCode : {} palign(8) > OCMRAM + .startupData : {} palign(8) > OCMRAM, type = NOINIT + + /* Place sysbios entry point - ends */ + .utilsCopyVecsToAtcm : {} palign(8) > MSMC3_HIGH + + .text_fast : > OCMRAM + { + *ecatappl.obj (.text) + } + .text : {} palign(8) > MSMC3_HIGH + .const : {} palign(8) > MSMC3_HIGH + .cinit : {} palign(8) > MSMC3_HIGH + .bss : {} align(4) > OCMRAM /*MSMC3*/ + .data : {} palign(128) > MSMC3_HIGH + .stack : {} align(4) > MCU0_R5F_TCMB0 /* Additional sections settings */ diff --git a/examples/ethercat_slave/tiescutils.c b/examples/ethercat_slave/tiescutils.c index 592d757..5203e89 100644 --- a/examples/ethercat_slave/tiescutils.c +++ b/examples/ethercat_slave/tiescutils.c @@ -65,8 +65,9 @@ #include #include +#if defined(SOC_AM437x) #include - +#endif #include #include #include diff --git a/protocols/ethercat_slave/ecat_appl/am65xx_app_r5f.cfg b/protocols/ethercat_slave/ecat_appl/am65xx_app_r5f.cfg index f8d4130..c0a594b 100644 --- a/protocols/ethercat_slave/ecat_appl/am65xx_app_r5f.cfg +++ b/protocols/ethercat_slave/ecat_appl/am65xx_app_r5f.cfg @@ -58,23 +58,32 @@ Load.swiEnabled = true; Load.hwiEnabled = true; Load.taskEnabled = true; -var Uart = xdc.loadPackage('ti.drv.uart'); -var I2c = xdc.loadPackage('ti.drv.i2c'); -var Pruss = xdc.loadPackage('ti.drv.pruss'); -var Gpio = xdc.loadPackage('ti.drv.gpio'); -/*var Udma = xdc.loadPackage('ti.drv.udma'); -var Sciclient = xdc.loadPackage('ti.drv.sciclient');*/ +var socType = "am65xx"; -var socType = "am65xx"; -var Csl = xdc.loadPackage('ti.csl'); -Csl.Settings.deviceType = socType; +/* Load the UART package */ +var Uart = xdc.loadPackage('ti.drv.uart'); +Uart.Settings.socType = socType; + +/* Load the I2C package */ +var I2c = xdc.loadPackage('ti.drv.i2c'); +I2c.Settings.socType = socType; + +/* Load the PRUSS package */ +var Pruss = xdc.loadPackage('ti.drv.pruss'); +Pruss.Settings.socType = socType; + +var Gpio = xdc.loadPackage('ti.drv.gpio'); +Gpio.Settings.socType = socType; + +/* Load the CSL package */ +var Csl = xdc.loadPackage('ti.csl'); +Csl.Settings.deviceType = socType; /* Load the board package */ var Board = xdc.loadPackage('ti.board'); Board.Settings.boardName = "am65xx_idk"; /* Load the spi package */ -var socType = "am65xx"; var Spi = xdc.loadPackage('ti.drv.spi'); Spi.Settings.socType = socType; @@ -82,11 +91,11 @@ Spi.Settings.socType = socType; var osType = "tirtos" var Osal = xdc.useModule('ti.osal.Settings'); Osal.osType = osType; +Osal.socType = socType; -/* SCICLIENT */ -var socType = "am65xx"; -var SciClient = xdc.loadPackage('ti.drv.sciclient'); -SciClient.Settings.socType = socType; +/* Load the SCICLIENT package */ +var Sciclient = xdc.loadPackage('ti.drv.sciclient'); +Sciclient.Settings.socType = socType; /* Enable cache */ var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache'); @@ -124,7 +133,7 @@ Defaults.common$.namedModule = false; /* Create default heap and hook it into Memory */ var heapMemParams = new HeapMem.Params; -heapMemParams.size = 2*1048576; +heapMemParams.size = 32768; var heap0 = HeapMem.create(heapMemParams); Memory.defaultHeapInstance = heap0; @@ -162,7 +171,7 @@ SysMin.flushAtExit = false; */ /* System stack size (used by ISRs and Swis) */ -Program.stack = 0x80000; +Program.stack = 32768; Task.defaultStackSize = 8192; /* @@ -202,4 +211,15 @@ LoggingSetup.eventUploadMode = LoggingSetup.UploadMode_JTAGSTOPMODE; BIOS.kernelHeapSize = 32768; Task.idleTaskStackSize = 8192; -BIOS.customCCOpts = "--float_support=vfpv3d16 --endian=little -mv7R5 --abi=eabi -q -ms --opt_for_speed=5 --program_level_compile -o3"; +BIOS.customCCOpts = "--float_support=vfpv3d16 --endian=little -mv7R5 --abi=eabi -q -ms --opt_for_speed=0 --code_state=16 --program_level_compile -o3"; + +/* WORKAROUND: Disable Timer frequency check, workaround for issue when loading with SBL */ +var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer'); +Timer.checkFrequency = false; + +var Reset = xdc.useModule("xdc.runtime.Reset"); +Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm"; + +/* Place vector table in separate section - by default this goes to 0x0 which + * is reserved by SBL */ +Program.sectMap[".vecs"] = "VECTORS"; \ No newline at end of file diff --git a/protocols/ethercat_slave/ecat_appl/idkAM65xx/tiesc_soc.c b/protocols/ethercat_slave/ecat_appl/idkAM65xx/tiesc_soc.c index 6459fd6..4846a47 100644 --- a/protocols/ethercat_slave/ecat_appl/idkAM65xx/tiesc_soc.c +++ b/protocols/ethercat_slave/ecat_appl/idkAM65xx/tiesc_soc.c @@ -34,8 +34,6 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. **/ -#include - #include #include @@ -71,6 +69,7 @@ #include #include #include +#include #endif #if defined (__aarch64__) @@ -78,13 +77,9 @@ #define ARM_INTERRUPT_OFFSET_ICSS0 (286-20) #define ARM_INTERRUPT_OFFSET_ICSS1 (294-20) #define ARM_INTERRUPT_OFFSET_ICSS2 (302-20) -#else -/* R5F */ -#define ARM_INTERRUPT_OFFSET_ICSS0 (160-20) -#define ARM_INTERRUPT_OFFSET_ICSS1 (168-20) -#define ARM_INTERRUPT_OFFSET_ICSS2 (176-20) #endif + #define CSL_SEMAPHORE_REG_OFFSET(n) (0x100 + ((n) * 0x04)) SPI_Handle handle; /* SPI handle */ @@ -95,11 +90,15 @@ extern PRUICSS_Config pruss_config[2 + 1]; /* Board specific definitions */ #define MCSPI_INSTANCE (0U) -#define BOARD_IDKAM571x 1 -#define BOARD_IDKAM572x 2 +#define NUM_ICSS_INTERRUPTS (8) +#define INTERRUPT_ROUTE_ERROR (-1) +#define ICSSG_INTERRUPT_SRC_INDEX (294) +#define I2C0_INTERRUPT_SRC_INDEX (0) void tiesc_mii_pinmuxConfig (void); +int16_t icssInterruptOffset = 0; +uint32_t i2cInterruptOffset = 0; uint8_t isEtherCATDevice(void) { @@ -124,6 +123,7 @@ uint8_t isEtherCATDevice(void) int16_t getARMInterruptOffset() { +#if defined (__aarch64__) #if (PRUICSS_INSTANCE == PRUICSS_INSTANCE_ONE) return ARM_INTERRUPT_OFFSET_ICSS0; #elif (PRUICSS_INSTANCE == PRUICSS_INSTANCE_TWO) @@ -131,6 +131,10 @@ int16_t getARMInterruptOffset() #else return ARM_INTERRUPT_OFFSET_ICSS2; #endif +#else + return (icssInterruptOffset - 20); +#endif + } void initSpinlock() @@ -160,6 +164,160 @@ void bsp_soft_reset() return; } +#if !defined (__aarch64__) +int32_t route_icss_interrupts_to_r5f(uint32_t icss_instance) +{ + /* Route ICSS Interrupts to R5F. */ + int32_t retVal = CSL_PASS; + struct tisci_msg_rm_get_resource_range_resp resp; + struct tisci_msg_rm_get_resource_range_req req; + struct tisci_msg_rm_irq_set_req rmIrqReq; + struct tisci_msg_rm_irq_set_resp rmIrqResp; + uint16_t intStartNum; + uint16_t intNum, dstInput, baseOffset; + uint32_t i; + + if ( (icss_instance != PRUICSS_INSTANCE_ONE) && (icss_instance != PRUICSS_INSTANCE_ONE) && (icss_instance != PRUICSS_INSTANCE_ONE)) + { + retVal = INTERRUPT_ROUTE_ERROR; + } + + if(CSL_PASS == retVal) + { + req.type = TISCI_DEV_MAIN2MCU_LVL_INTRTR0; + req.subtype = TISCI_RESASG_SUBTYPE_IR_OUTPUT; + req.secondary_host = (uint8_t)TISCI_HOST_ID_R5_0; + + /* Get interrupt number range */ + retVal = Sciclient_rmGetResourceRange(&req, &resp, SCICLIENT_SERVICE_WAIT_FOREVER); + + if(CSL_PASS == retVal) + { + intStartNum = resp.range_start; + + rmIrqReq.dst_id = TISCI_DEV_MCU_ARMSS0_CPU0; + rmIrqReq.secondary_host = TISCI_HOST_ID_R5_0; + + for(i = 0; NUM_ICSS_INTERRUPTS != i; i++) + { + intNum = intStartNum + i; + + retVal = Sciclient_rmIrqTranslateIrOutput(TISCI_DEV_MAIN2MCU_LVL_INTRTR0, intNum, TISCI_DEV_MCU_ARMSS0_CPU0, &dstInput); + + if(i == 0) + baseOffset = dstInput; + + if (CSL_PASS == retVal) + { + rmIrqReq.ia_id = 0U; + rmIrqReq.vint = 0U; + rmIrqReq.global_event = 0U; + rmIrqReq.vint_status_bit_index = 0U; + + rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID + | TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID + | TISCI_MSG_VALUE_RM_SECONDARY_HOST_VALID; + if (icss_instance == PRUICSS_INSTANCE_ONE) + { + rmIrqReq.src_id = TISCI_DEV_PRU_ICSSG0; + } + else if (icss_instance == PRUICSS_INSTANCE_ONE) + { + rmIrqReq.src_id = TISCI_DEV_PRU_ICSSG1; + } + else if (icss_instance == PRUICSS_INSTANCE_ONE) + { + rmIrqReq.src_id = TISCI_DEV_PRU_ICSSG2; + } + + rmIrqReq.src_index = ICSSG_INTERRUPT_SRC_INDEX + i; + rmIrqReq.dst_host_irq = dstInput; + + /* Config event */ + retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER); + if ( CSL_PASS != retVal ) + { + break; + } + } + } + } + } + + if(CSL_PASS == retVal) + { + retVal = baseOffset; + } + else + { + retVal = INTERRUPT_ROUTE_ERROR; + UART_printf("Error in mapping ICSS interrupts to R5F\n"); + } + + return retVal; +} + + +int32_t route_i2c_interrupts_to_r5f() +{ + /* Route I2C Interrupts to R5F. */ + int32_t retVal; + struct tisci_msg_rm_get_resource_range_resp resp; + struct tisci_msg_rm_get_resource_range_req req; + struct tisci_msg_rm_irq_set_req rmIrqReq; + struct tisci_msg_rm_irq_set_resp rmIrqResp; + uint16_t intStartNum; + uint16_t dstInput; + + req.type = TISCI_DEV_MAIN2MCU_LVL_INTRTR0; + req.subtype = TISCI_RESASG_SUBTYPE_IR_OUTPUT; + req.secondary_host = (uint8_t)TISCI_HOST_ID_R5_0; + + /* Get interrupt number range */ + retVal = Sciclient_rmGetResourceRange(&req, &resp, SCICLIENT_SERVICE_WAIT_FOREVER); + + if(CSL_PASS == retVal) + { + /*ASSUMPTION: First few interrupt lines are used for mapping ICSS events*/ + intStartNum = resp.range_start + NUM_ICSS_INTERRUPTS; + + rmIrqReq.dst_id = TISCI_DEV_MCU_ARMSS0_CPU0; + rmIrqReq.secondary_host = TISCI_HOST_ID_R5_0; + + retVal = Sciclient_rmIrqTranslateIrOutput(TISCI_DEV_MAIN2MCU_LVL_INTRTR0, intStartNum, TISCI_DEV_MCU_ARMSS0_CPU0, &dstInput); + + if (CSL_PASS == retVal) + { + rmIrqReq.ia_id = 0U; + rmIrqReq.vint = 0U; + rmIrqReq.global_event = 0U; + rmIrqReq.vint_status_bit_index = 0U; + + rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID + | TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID + | TISCI_MSG_VALUE_RM_SECONDARY_HOST_VALID; + rmIrqReq.src_id = TISCI_DEV_I2C0; + rmIrqReq.src_index = I2C0_INTERRUPT_SRC_INDEX; + rmIrqReq.dst_host_irq = dstInput; + } + + /* Config event */ + retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER); + } + + if(CSL_PASS == retVal) + { + retVal = dstInput; + } + else + { + retVal = INTERRUPT_ROUTE_ERROR; + UART_printf("Error in mapping I2C interrupt to R5F\n"); + } + + return retVal; +} +#endif void bsp_soc_evm_init() { @@ -217,61 +375,18 @@ void bsp_soc_evm_init() //Disable PRUs - This is to ensure PRUs are not running when application is not initialized PRUICSS_pruDisable(pruIcss1Handle, 0); PRUICSS_pruDisable(pruIcss1Handle, 1); - #if !defined (__aarch64__) - /* Route I2C0 interrupts to R5F */ - /* Main Domain I2C0 events are mapped to MAIN2MCU_INTRTR_LVL_IN_100 */ - /* Since 176 is used as I2C interrupt number, MAIN2MCU_INTRTR_LVL_IN_100 should be written to 0xA10044. */ - /* If 177 is used as I2C interrupt number, MAIN2MCU_INTRTR_LVL_IN_100 should be written to 0xA10048. */ - HW_WR_REG8_RAW(0xA10044, 100); - - /* Route ICSS Interrupts to R5F. */ - /* ICSSG0 events are mapped to MAIN2MCU_INTRTR_LVL_IN[32:39]*/ - /* ICSSG1 events are mapped to MAIN2MCU_INTRTR_LVL_IN[40:47]*/ - /* ICSSG2 events are mapped to MAIN2MCU_INTRTR_LVL_IN[48:55]*/ - /* MAIN2MCU_RTR_LVL_MX_INTR[63:0] is mapped to MCU_R5_CORE0_INT_IN[223:160] */ - HW_WR_REG8_RAW(0xA10004, - 32); //MAIN2MCU_RTR_LVL_MX_INTR0 mapped to MAIN2MCU_RTR_LVL_MX_INTR32 - HW_WR_REG8_RAW(0xA10008, - 33); //MAIN2MCU_RTR_LVL_MX_INTR1 mapped to MAIN2MCU_RTR_LVL_MX_INTR33 - HW_WR_REG8_RAW(0xA1000C, - 34); //MAIN2MCU_RTR_LVL_MX_INTR2 mapped to MAIN2MCU_RTR_LVL_MX_INTR34 - HW_WR_REG8_RAW(0xA10010, - 35); //MAIN2MCU_RTR_LVL_MX_INTR3 mapped to MAIN2MCU_RTR_LVL_MX_INTR35 - HW_WR_REG8_RAW(0xA10014, - 36); //MAIN2MCU_RTR_LVL_MX_INTR4 mapped to MAIN2MCU_RTR_LVL_MX_INTR36 - HW_WR_REG8_RAW(0xA10018, - 37); //MAIN2MCU_RTR_LVL_MX_INTR5 mapped to MAIN2MCU_RTR_LVL_MX_INTR37 - HW_WR_REG8_RAW(0xA1001C, - 38); //MAIN2MCU_RTR_LVL_MX_INTR6 mapped to MAIN2MCU_RTR_LVL_MX_INTR38 - HW_WR_REG8_RAW(0xA10020, - 39); //MAIN2MCU_RTR_LVL_MX_INTR7 mapped to MAIN2MCU_RTR_LVL_MX_INTR39 - - HW_WR_REG8_RAW(0xA10024, - 40); //MAIN2MCU_RTR_LVL_MX_INTR8 mapped to MAIN2MCU_RTR_LVL_MX_INTR40 - HW_WR_REG8_RAW(0xA10028, - 43); //MAIN2MCU_RTR_LVL_MX_INTR9 mapped to MAIN2MCU_RTR_LVL_MX_INTR41 - HW_WR_REG8_RAW(0xA1002C, - 44); //MAIN2MCU_RTR_LVL_MX_INTR10 mapped to MAIN2MCU_RTR_LVL_MX_INTR42 - HW_WR_REG8_RAW(0xA10030, - 45); //MAIN2MCU_RTR_LVL_MX_INTR11 mapped to MAIN2MCU_RTR_LVL_MX_INTR43 - HW_WR_REG8_RAW(0xA10034, - 46); //MAIN2MCU_RTR_LVL_MX_INTR12 mapped to MAIN2MCU_RTR_LVL_MX_INTR44 - HW_WR_REG8_RAW(0xA10038, - 47); //MAIN2MCU_RTR_LVL_MX_INTR13 mapped to MAIN2MCU_RTR_LVL_MX_INTR45 - HW_WR_REG8_RAW(0xA1003C, - 48); //MAIN2MCU_RTR_LVL_MX_INTR14 mapped to MAIN2MCU_RTR_LVL_MX_INTR46 - HW_WR_REG8_RAW(0xA10040, - 49); //MAIN2MCU_RTR_LVL_MX_INTR15 mapped to MAIN2MCU_RTR_LVL_MX_INTR47 + /* Route Interrupts to R5F. */ + icssInterruptOffset = (int16_t)route_icss_interrupts_to_r5f(PRUICSS_INSTANCE); + i2cInterruptOffset = route_i2c_interrupts_to_r5f(); /* LED's and Rotary Switch are connected to Main Domain I2C0. Reconfigure I2C to use I2C0 of main domain. */ /* Get the default I2C init configurations */ I2C_socGetInitCfg(BOARD_I2C_IOEXP_INSTANCE, &i2c_cfg); i2c_cfg.baseAddr = CSL_I2C0_CFG_BASE; - /*Use MCU_R5_CORE0_INT_IN_176, MAIN2MCU_LVL_INTRTR0 host interrupt 16.*/ - i2c_cfg.intNum = CSL_MCU0_INTR_MAIN2MCU_LVL_INTR0_OUTL_16; + i2c_cfg.intNum = i2cInterruptOffset; I2C_socSetInitCfg(BOARD_I2C_IOEXP_INSTANCE, &i2c_cfg); #endif diff --git a/protocols/ethercat_slave/projects/ccsproject_args/AM65xx/ethercat_slave_demo_AM65xx_r5f.txt b/protocols/ethercat_slave/projects/ccsproject_args/AM65xx/ethercat_slave_demo_AM65xx_r5f.txt index 03d2aa3..4db933d 100644 --- a/protocols/ethercat_slave/projects/ccsproject_args/AM65xx/ethercat_slave_demo_AM65xx_r5f.txt +++ b/protocols/ethercat_slave/projects/ccsproject_args/AM65xx/ethercat_slave_demo_AM65xx_r5f.txt @@ -23,6 +23,7 @@ -ccs.linkFile "IA_SDK_HOME/protocols/ethercat_slave/ecat_appl/am65xx_app_r5f.cfg" @configurations AM65xx_debug AM65xx_release -ccs.linkFile "IA_SDK_HOME/examples/osal" @configurations AM65xx_debug AM65xx_release -ccs.linkFile "IA_SDK_HOME/examples/ethercat_slave/linker_r5.lds" @configurations AM65xx_debug AM65xx_release +-ccs.linkFile "PDK_INSTALL_PATH/ti/utils/copyVecs2Atcm/utilsCopyVecs2ATcm.asm" -ccs.setCompilerOptions "-DSOC_AM65XX" @configurations AM65xx_debug AM65xx_release -ccs.setCompilerOptions "-DECAT_MII" @configurations AM65xx_debug AM65xx_release diff --git a/protocols/ethercat_slave/projects/ccsproject_args/AM65xx/ethercat_slave_full_AM65xx_r5f.txt b/protocols/ethercat_slave/projects/ccsproject_args/AM65xx/ethercat_slave_full_AM65xx_r5f.txt index 2562175..cf91b2d 100644 --- a/protocols/ethercat_slave/projects/ccsproject_args/AM65xx/ethercat_slave_full_AM65xx_r5f.txt +++ b/protocols/ethercat_slave/projects/ccsproject_args/AM65xx/ethercat_slave_full_AM65xx_r5f.txt @@ -18,6 +18,7 @@ -ccs.linkFile "IA_SDK_HOME/protocols/ethercat_slave/ecat_appl/EcatStack" @configurations AM65xx_debug AM65xx_release -ccs.linkFile "IA_SDK_HOME/examples/osal" @configurations AM65xx_debug AM65xx_release -ccs.linkFile "IA_SDK_HOME/examples/ethercat_slave/linker_r5.lds" @configurations AM65xx_debug AM65xx_release +-ccs.linkFile "PDK_INSTALL_PATH/ti/utils/copyVecs2Atcm/utilsCopyVecs2ATcm.asm" -ccs.setCompilerOptions "-DSOC_AM65XX" @configurations AM65xx_debug AM65xx_release -ccs.setCompilerOptions "-DECAT_MII" @configurations AM65xx_debug AM65xx_release diff --git a/protocols/ethercat_slave/projects/projectCreate.bat b/protocols/ethercat_slave/projects/projectCreate.bat index fa256f9..6aecd2c 100644 --- a/protocols/ethercat_slave/projects/projectCreate.bat +++ b/protocols/ethercat_slave/projects/projectCreate.bat @@ -55,7 +55,7 @@ set "AM57xx_PDK_INSTALL_PATH=C:\ti\pdk_am57xx_1_0_17\packages" set "K2G_PDK_INSTALL_PATH=C:\ti\pdk_k2g_1_0_12\packages" ::Set PDK Installation directory path(Mandatory for AM65xx projects) -set "AM65xx_PDK_INSTALL_PATH=C:\ti\pdk_am65xx_1_0_7\packages" +set "AM65xx_PDK_INSTALL_PATH=C:\ti\pdk_am65xx_07_01_00_55\packages" :: Set the folder path where the projects will be created using command line project create method(Mandatory) set "PROJECT_CREATE_DIR=%IA_SDK_HOME%\protocols\ethercat_slave\projects" @@ -91,16 +91,16 @@ set "AM57xx_PDK_VERSION=1.0.17" set "K2G_PDK_VERSION=1.0.17" ::Set AM65xx PDK Version -set "AM65xx_PDK_VERSION=1.0.7" +set "AM65xx_PDK_VERSION=7.1.0.55" :: Set SYSBIOS Version which is to be used while creating the project -set "SYS_BIOS_VERSION=6.76.03.01" +set "SYS_BIOS_VERSION=6.83.00.18" :: Set NDK Version which is to be used while creating the project set "NDK_VERSION=3.61.01.01" :: Set XDC Tools Version which is to be used while creating the project -set "XDC_TOOLS_VERSION=3.55.02.22" +set "XDC_TOOLS_VERSION=3.61.03.29_core" :: Set EDMA3 Version which is to be used while creating the project set "EDMA_VERSION=2.12.05.30" @@ -361,10 +361,10 @@ IF "%SOC%"=="AM335x" ( ::Set RTSC Platform for AM65xx A53 ARM core set "RTSC_PLATFORM=ti.platforms.cortexA:AM65X" ::Set Processor variable which is passed to pdkAppImageCreate.bat inside Processor SDK - set PROCESSOR_FOR_POST_BUILD="mpu" + set PROCESSOR_FOR_POSTBUILD="mpu" ) ELSE IF "%PROCESSOR%"=="r5f" ( ::Set version of CG-Tools for AM65xx R5F ARM core - set "CGT_VERSION="18.12.5.LTS"" + set "CGT_VERSION="20.2.0.LTS"" ::Set Device type for AM65xx R5F ARM core set "CCS_DEVICE="Cortex R.AM6548"" ::set RTSC Target for AM65xx R5F ARM core @@ -372,10 +372,10 @@ IF "%SOC%"=="AM335x" ( ::Set RTSC Platform for AM65xx R5F ARM core set "RTSC_PLATFORM=ti.platforms.cortexR:AM65X" ::Set Processor variable which is passed to pdkAppImageCreate.bat inside Processor SDK - set PROCESSOR_FOR_POST_BUILD="mcu" + set PROCESSOR_FOR_POSTBUILD="mcu" ) ::Set SOC variable which is passed to pdkAppImageCreate.bat inside Processor SDK - set SOC_FOR_POST_BUILD="am65xx" + set SOC_FOR_POSTBUILD="am65xx" ::Set PDK Installation directory path set "PDK_INSTALL_PATH=%AM65xx_PDK_INSTALL_PATH%" ::Set AM65xx PDK Eclipse ID diff --git a/protocols/ethercat_slave/projects/projectCreate.sh b/protocols/ethercat_slave/projects/projectCreate.sh index 592b411..88ef552 100644 --- a/protocols/ethercat_slave/projects/projectCreate.sh +++ b/protocols/ethercat_slave/projects/projectCreate.sh @@ -51,7 +51,7 @@ AM57xx_PDK_INSTALL_PATH=/home/gtbldadm/ti/pdk_am57xx_1_0_17/packages K2G_PDK_INSTALL_PATH=/home/gtbldadm/ti/pdk_k2g_1_0_16/packages #Set PDK Installation directory path(Mandatory for AM65xx projects) -AM65xx_PDK_INSTALL_PATH=/home/gtbldadm/ti/pdk_am65xx_1_0_7/packages +AM65xx_PDK_INSTALL_PATH=/home/gtbldadm/ti/pdk_am65xx_07_01_00_55/packages #Set the folder path where the projects will be created using command line project create method(Mandatory) PROJECT_CREATE_DIR=$IA_SDK_HOME/protocols/ethercat_slave/projects @@ -90,16 +90,16 @@ AM57xx_PDK_VERSION=1.0.17 K2G_PDK_VERSION=1.0.16 #Set AM65xx PDK Version -AM65xx_PDK_VERSION=1.0.7 +AM65xx_PDK_VERSION=7.1.0.55 #Set SYSBIOS Version which is to be used while creating the project -SYS_BIOS_VERSION=6.76.03.01 +SYS_BIOS_VERSION=6.83.00.18 #Set NDK Version which is to be used while creating the project NDK_VERSION=3.61.01.01 #Set XDC Tools Version which is to be used while creating the project -XDC_TOOLS_VERSION=3.55.02.22 +XDC_TOOLS_VERSION=3.61.03.29_core #Set EDMA3 Version which is to be used while creating the project EDMA_VERSION=2.12.05.30 @@ -353,7 +353,7 @@ then elif [ "$PROCESSOR" == "r5f" ] then # Set version of CG-Tools for AM65xx ARM - CGT_VERSION="18.12.5.LTS" + CGT_VERSION="20.2.0.LTS" # Set Device type for AM65xx R5F ARM core CCS_DEVICE="Cortex R.AM6548" # set RTSC Target for AM65xx R5F ARM core