MSPDS 3_07_000_012
Build date: 02242016
Release Information
Click on the links in the table below to download.The MSP debug stack (MSPDS) for all MSP430 devices consists of a dynamic link library as well as embedded firmware that runs on flash emulation tools (FETs) such as the MSP-FET, MSP-FET430UIF or eZ emulators. It is the bridging element between all PC software and all MSP430 microcontroller derivatives and handles tasks such as code download, stepping through code, break point handling and so forth. The MSP Debug Stack is used in IDEs such as Code Composer Studio (CCS), IAR's Embedded Workbench for MSP430 or other tools like Smart RF Studio or Elprotronic's FlashPro430.
Changes in this Release
- Added support for MSP430FR2311, MSP430FR2310
- Added support for MSP430FR5994 (including LEA debug)
- Added support for MSP432P401R
- Native 64-bit OS X 10.11.3 (El Capitan) support
- Native 64-bit Linux support
- MSP432P401R - support using the MSP-FET
- JTAG and SWD protocol
- Automatic protocol detection
- Integrated FLASH access
- Run Control
- Halt target
- Run or Free Run target
- CPU core register access
- Hardware breakpoints and data watchpoints
- JTAG/SWD lock - lock device via FLASH mailbox - unlock via factory reset
- EnergyTrace and EnergyTrace+
- MSP-FET BSL432 support - empty device with automatic BSL start support only
- Added LEA debug sync. mechanism for MSP430FR599x family
- Added new 32 bit clock control API for MSP430FR599x family
- Added new API to set MSP target architecture (MSP432 or MSP430)
- Enhanced MSPDS structs on API level to enable MSP432P401R support
Bug Fixes
- Fixed returned error message when Backchannel UART port is in use during firmware update
- Fixed incorrect module clock control defaults
- Fixed INFO memory lock for I20xx family
- Changed cycle counter to execute only delta cycle measurements
- Fixed async. close and callback messaging by adding mutex protection
Known Issues
- On devices with FLL, clock control does not allow to keep clocks running, while the device is halted and the clock is sourced by the FLL
- V1.3 of UIF does not work in SBW2 mode with 2.2nf cap on reset line
- eZ-FET UART might lose bytes with 115k baud (no handshake enabled) and DMA as data loopback on target device
- MSP-FET EEM access to F149 and L092 devices is only possible with JTAG speed slow
Older Releases
- 3_05_001_001
- 3_05_001_000
- 3_05_000_001
- 3_04_003_004
- 3_04_002_007
- 3_04_001_000
- 3_04_000_020
- 3_04_000_020
- 3_03_001_004
- 3_03_001_003
- 3_03_000_006
- 3_02_005_004
- 3_02_004_005
- 3_02_003_015
- 3_02_001_009
- 2_04_009_001
- 2_04_009_001
- 2_04_008_002
- 2_04_007_001
MSPDS Product downloads
| Title | Description | Size | |
|---|---|---|---|
 |
MSP430 DLL 3.07.000.012 | 31296K | |
| MD5 Checksums | 4K | ||
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