 |
 |
Go to the documentation of this file.
2 #define AES256_ACTL0 (HWREG16(0x40003C00))
3 #define AES256_ACTL1 (HWREG16(0x40003C02))
4 #define AES256_ADIN (HWREG16(0x40003C08))
5 #define AES256_ADOUT (HWREG16(0x40003C0A))
6 #define AES256_AKEY (HWREG16(0x40003C06))
7 #define AES256_ASTAT (HWREG16(0x40003C04))
8 #define AES256_AXDIN (HWREG16(0x40003C0C))
9 #define AES256_AXIN (HWREG16(0x40003C0E))
10 #define COMP_E0_CTL0 (HWREG16(0x40003400))
11 #define COMP_E0_CTL1 (HWREG16(0x40003402))
12 #define COMP_E0_CTL2 (HWREG16(0x40003404))
13 #define COMP_E0_CTL3 (HWREG16(0x40003406))
14 #define COMP_E0_INT (HWREG16(0x4000340C))
15 #define COMP_E0_IV (HWREG16(0x4000340E))
16 #define CS_ACC (HWREG32(0x40010400))
17 #define CS_CLKEN (HWREG32(0x40010430))
18 #define CS_CLRIFG (HWREG32(0x40010450))
19 #define CS_CTL0 (HWREG32(0x40010404))
20 #define CS_CTL1 (HWREG32(0x40010408))
21 #define CS_CTL2 (HWREG32(0x4001040C))
22 #define CS_CTL3 (HWREG32(0x40010410))
23 #define CS_CTL4 (HWREG32(0x40010414))
24 #define CS_CTL5 (HWREG32(0x40010418))
25 #define CS_CTL6 (HWREG32(0x4001041C))
26 #define CS_CTL7 (HWREG32(0x40010420))
27 #define CS_DCOERCAL (HWREG32(0x40010460))
28 #define CS_IE (HWREG32(0x40010440))
29 #define CS_IFG (HWREG32(0x40010448))
30 #define CS_SETIFG (HWREG32(0x40010458))
31 #define CS_STAT (HWREG32(0x40010434))
167 #define PMAP_CTL (HWREG16(0x40005002))
168 #define PMAP_KEYID (HWREG16(0x40005000))
169 #define REF_A_CTL0 (HWREG16(0x40003000))
170 #define RTC_C_ADAY (HWREG8_H(RTCADOWDAY))
171 #define RTC_C_ADOW (HWREG8_L(RTCADOWDAY))
172 #define RTC_ADAY (HWREG8_H(RTCADOWDAY))
173 #define RTC_ADOW (HWREG8_L(RTCADOWDAY))
174 #define RTC_C_AHOUR (HWREG8_H(RTCAMINHR))
175 #define RTC_C_AMIN (HWREG8_L(RTCAMINHR))
177 #define RTC_AHOUR (HWREG8_H(RTCAMINHR))
178 #define RTC_AMIN (HWREG8_L(RTCAMINHR))
179 #define RTC_C_CTL0 (HWREG16(0x40004400))
180 #define RTC_C_CTL1 (HWREG8_L(RTCCTL13))
181 #define RTC_C_CTL3 (HWREG8_H(RTCCTL13))
183 #define RTC_MON (HWREG8_H(RTCDATE))
184 #define RTC_DAY (HWREG8_L(RTCDATE))
185 #define RTC_C_DAY (HWREG8_L(RTCDATE))
186 #define RTC_C_DOW (HWREG8_H(RTCTIM1))
187 #define RTC_C_HOUR (HWREG8_L(RTCTIM1))
188 #define RTC_C_IV (HWREG16(0x4000440E))
189 #define RTC_C_MIN (HWREG8_H(RTCTIM0))
190 #define RTC_C_MON (HWREG8_H(RTCDATE))
191 #define RTC_C_OCAL (HWREG16(0x40004404))
192 #define RTCPS (HWREG16(0x4000440C))
193 #define RTC_C_PS0CTL (HWREG16(0x40004408))
194 #define RTC_C_PS1CTL (HWREG16(0x4000440A))
195 #define RTCPS1 (HWREG8_H(RTCPS))
196 #define RTC_C_SEC (HWREG8_L(RTCTIM0))
197 #define RTC_C_TCMP (HWREG16(0x40004406))
199 #define RTC_MIN (HWREG8_H(RTCTIM0))
200 #define RTC_DOW (HWREG8_H(RTCTIM1))
201 #define RTC_HOUR (HWREG8_L(RTCTIM1))
202 #define RTC_C_YEAR (HWREG16(0x40004416))
203 #define TA0_CCR0 (HWREG16(0x40000012))
204 #define TA0_CCR1 (HWREG16(0x40000014))
205 #define TA0_CCR2 (HWREG16(0x40000016))
206 #define TA0_CCR3 (HWREG16(0x40000018))
207 #define TA0_CCR4 (HWREG16(0x4000001A))
208 #define TA0_CCR5 (HWREG16(0x4000001C))
209 #define TA0_CCR6 (HWREG16(0x4000001E))
210 #define TA0_CCTL0 (HWREG16(0x40000002))
211 #define TA0_CCTL1 (HWREG16(0x40000004))
212 #define TA0_CCTL2 (HWREG16(0x40000006))
213 #define TA0_CCTL3 (HWREG16(0x40000008))
214 #define TA0_CCTL4 (HWREG16(0x4000000A))
215 #define TA0_CCTL5 (HWREG16(0x4000000C))
216 #define TA0_CCTL6 (HWREG16(0x4000000E))
217 #define TA0_CTL (HWREG16(0x40000000))
218 #define TA0_EX0 (HWREG16(0x40000020))
219 #define TA0_IV (HWREG16(0x4000002E))
220 #define TA0_R (HWREG16(0x40000010))
221 #define TA1_CCR0 (HWREG16(0x40000412))
222 #define TA1_CCR1 (HWREG16(0x40000414))
223 #define TA1_CCR2 (HWREG16(0x40000416))
224 #define TA1_CCR3 (HWREG16(0x40000418))
225 #define TA1_CCR4 (HWREG16(0x4000041A))
226 #define TA1_CCR5 (HWREG16(0x4000041C))
227 #define TA1_CCR6 (HWREG16(0x4000041E))
228 #define TA1_CCTL0 (HWREG16(0x40000402))
229 #define TA1_CCTL1 (HWREG16(0x40000404))
230 #define TA1_CCTL2 (HWREG16(0x40000406))
231 #define TA1_CCTL3 (HWREG16(0x40000408))
232 #define TA1_CCTL4 (HWREG16(0x4000040A))
233 #define TA1_CCTL5 (HWREG16(0x4000040C))
234 #define TA1_CCTL6 (HWREG16(0x4000040E))
235 #define TA1_CTL (HWREG16(0x40000400))
236 #define TA1_EX0 (HWREG16(0x40000420))
237 #define TA1_IV (HWREG16(0x4000042E))
238 #define TA1_R (HWREG16(0x40000410))
239 #define TA2_CCR0 (HWREG16(0x40000812))
240 #define TA2_CCR1 (HWREG16(0x40000814))
241 #define TA2_CCR2 (HWREG16(0x40000816))
242 #define TA2_CCR3 (HWREG16(0x40000818))
243 #define TA2_CCR4 (HWREG16(0x4000081A))
244 #define TA2_CCR5 (HWREG16(0x4000081C))
245 #define TA2_CCR6 (HWREG16(0x4000081E))
246 #define TA2_CCTL0 (HWREG16(0x40000802))
247 #define TA2_CCTL1 (HWREG16(0x40000804))
248 #define TA2_CCTL2 (HWREG16(0x40000806))
249 #define TA2_CCTL3 (HWREG16(0x40000808))
250 #define TA2_CCTL4 (HWREG16(0x4000080A))
251 #define TA2_CCTL5 (HWREG16(0x4000080C))
252 #define TA2_CCTL6 (HWREG16(0x4000080E))
253 #define TA2_CTL (HWREG16(0x40000800))
254 #define TA2_EX0 (HWREG16(0x40000820))
255 #define TA2_IV (HWREG16(0x4000082E))
256 #define TA2_R (HWREG16(0x40000810))
257 #define TA3_CCR0 (HWREG16(0x40000C12))
258 #define TA3_CCR1 (HWREG16(0x40000C14))
259 #define TA3_CCR2 (HWREG16(0x40000C16))
260 #define TA3_CCR3 (HWREG16(0x40000C18))
261 #define TA3_CCR4 (HWREG16(0x40000C1A))
262 #define TA3_CCR5 (HWREG16(0x40000C1C))
263 #define TA3_CCR6 (HWREG16(0x40000C1E))
264 #define TA3_CCTL0 (HWREG16(0x40000C02))
265 #define TA3_CCTL1 (HWREG16(0x40000C04))
266 #define TA3_CCTL2 (HWREG16(0x40000C06))
267 #define TA3_CCTL3 (HWREG16(0x40000C08))
268 #define TA3_CCTL4 (HWREG16(0x40000C0A))
269 #define TA3_CCTL5 (HWREG16(0x40000C0C))
270 #define TA3_CCTL6 (HWREG16(0x40000C0E))
271 #define TA3_CTL (HWREG16(0x40000C00))
272 #define TA3_EX0 (HWREG16(0x40000C20))
273 #define TA3_IV (HWREG16(0x40000C2E))
274 #define TA3_R (HWREG16(0x40000C10))
275 #define EUSCI_A0_UART_ABCTL (HWREG16(0x40001010))
276 #define UCA0BRW_L (HWREG8_L(UCA0BRW))
277 #define UCA0BRW_H (HWREG8_H(UCA0BRW))
278 #define EUSCI_A0_SPI_BRW (HWREG16(0x40001006))
279 #define UCA0CTLW0_H (HWREG8_L(UCA0CTLW0))
280 #define UCA0CTLW0_L (HWREG8_H(UCA0CTLW0))
281 #define EUSCI_A0_SPI_CTLW0 (HWREG16(0x40001000))
282 #define EUSCI_A0_UART_CTLW1 (HWREG16(0x40001002))
283 #define EUSCI_A0_SPI_IE (HWREG16(0x4000101A))
284 #define EUSCI_A0_SPI_IFG (HWREG16(0x4000101C))
285 #define EUSCI_A0_UART_IRCTL (HWREG16(0x40001012))
286 #define UCA0IRCTL_H (HWREG8_H(UCA0IRCTL))
287 #define UCA0IRCTL_L (HWREG8_L(UCA0IRCTL))
288 #define EUSCI_A0_SPI_IV (HWREG16(0x4000101E))
289 #define EUSCI_A0_UART_MCTLW (HWREG16(0x40001008))
290 #define EUSCI_A0_SPI_RXBUF (HWREG16(0x4000100C))
291 #define EUSCI_A0_SPI_STATW (HWREG16(0x4000100A))
292 #define EUSCI_A0_SPI_TXBUF (HWREG16(0x4000100E))
293 #define EUSCI_A1_UART_ABCTL (HWREG16(0x40001410))
294 #define UCA1BRW_L (HWREG8_L(UCA1BRW))
295 #define UCA1BRW_H (HWREG8_H(UCA1BRW))
296 #define EUSCI_A1_SPI_BRW (HWREG16(0x40001406))
297 #define UCA1CTLW0_H (HWREG8_L(UCA1CTLW0))
298 #define UCA1CTLW0_L (HWREG8_H(UCA1CTLW0))
299 #define EUSCI_A1_SPI_CTLW0 (HWREG16(0x40001400))
300 #define EUSCI_A1_UART_CTLW1 (HWREG16(0x40001402))
301 #define EUSCI_A1_SPI_IE (HWREG16(0x4000141A))
302 #define EUSCI_A1_SPI_IFG (HWREG16(0x4000141C))
303 #define EUSCI_A1_UART_IRCTL (HWREG16(0x40001412))
304 #define UCA1IRCTL_H (HWREG8_H(UCA1IRCTL))
305 #define UCA1IRCTL_L (HWREG8_L(UCA1IRCTL))
306 #define EUSCI_A1_SPI_IV (HWREG16(0x4000141E))
307 #define EUSCI_A1_UART_MCTLW (HWREG16(0x40001408))
308 #define EUSCI_A1_SPI_RXBUF (HWREG16(0x4000140C))
309 #define EUSCI_A1_SPI_STATW (HWREG16(0x4000140A))
310 #define EUSCI_A1_SPI_TXBUF (HWREG16(0x4000140E))
311 #define EUSCI_A2_UART_ABCTL (HWREG16(0x40001810))
312 #define UCA2BRW_L (HWREG8_L(UCA2BRW))
313 #define UCA2BRW_H (HWREG8_H(UCA2BRW))
314 #define EUSCI_A2_SPI_BRW (HWREG16(0x40001806))
315 #define UCA2CTLW0_H (HWREG8_L(UCA2CTLW0))
316 #define UCA2CTLW0_L (HWREG8_H(UCA2CTLW0))
317 #define EUSCI_A2_SPI_CTLW0 (HWREG16(0x40001800))
318 #define EUSCI_A2_UART_CTLW1 (HWREG16(0x40001802))
319 #define EUSCI_A2_SPI_IE (HWREG16(0x4000181A))
320 #define EUSCI_A2_SPI_IFG (HWREG16(0x4000181C))
321 #define EUSCI_A2_UART_IRCTL (HWREG16(0x40001812))
322 #define UCA2IRCTL_H (HWREG8_H(UCA2IRCTL))
323 #define UCA2IRCTL_L (HWREG8_L(UCA2IRCTL))
324 #define EUSCI_A2_SPI_IV (HWREG16(0x4000181E))
325 #define EUSCI_A2_UART_MCTLW (HWREG16(0x40001808))
326 #define EUSCI_A2_SPI_RXBUF (HWREG16(0x4000180C))
327 #define EUSCI_A2_SPI_STATW (HWREG16(0x4000180A))
328 #define EUSCI_A2_SPI_TXBUF (HWREG16(0x4000180E))
329 #define EUSCI_A3_UART_ABCTL (HWREG16(0x40001C10))
330 #define UCA3BRW_L (HWREG8_L(UCA3BRW))
331 #define UCA3BRW_H (HWREG8_H(UCA3BRW))
332 #define EUSCI_A3_SPI_BRW (HWREG16(0x40001C06))
333 #define UCA3CTLW0_H (HWREG8_L(UCA3CTLW0))
334 #define UCA3CTLW0_L (HWREG8_H(UCA3CTLW0))
335 #define EUSCI_A3_SPI_CTLW0 (HWREG16(0x40001C00))
336 #define EUSCI_A3_UART_CTLW1 (HWREG16(0x40001C02))
337 #define EUSCI_A3_SPI_IE (HWREG16(0x40001C1A))
338 #define EUSCI_A3_SPI_IFG (HWREG16(0x40001C1C))
339 #define EUSCI_A3_UART_IRCTL (HWREG16(0x40001C12))
340 #define UCA3IRCTL_H (HWREG8_H(UCA3IRCTL))
341 #define UCA3IRCTL_L (HWREG8_L(UCA3IRCTL))
342 #define EUSCI_A3_SPI_IV (HWREG16(0x40001C1E))
343 #define EUSCI_A3_UART_MCTLW (HWREG16(0x40001C08))
344 #define EUSCI_A3_SPI_RXBUF (HWREG16(0x40001C0C))
345 #define EUSCI_A3_SPI_STATW (HWREG16(0x40001C0A))
346 #define EUSCI_A3_SPI_TXBUF (HWREG16(0x40001C0E))
347 #define EUSCI_B0_I2C_ADDMASK (HWREG16(0x4000201E))
348 #define EUSCI_B0_I2C_ADDRX (HWREG16(0x4000201C))
349 #define UCB0BRW_L (HWREG8_L(UCB0BRW))
350 #define UCB0BRW_H (HWREG8_H(UCB0BRW))
351 #define EUSCI_B0_SPI_BRW (HWREG16(0x40002006))
352 #define UCB0CTLW0_H (HWREG8_L(UCB0CTLW0))
353 #define UCB0CTLW0_L (HWREG8_H(UCB0CTLW0))
354 #define EUSCI_B0_SPI_CTLW0 (HWREG16(0x40002000))
355 #define EUSCI_B0_I2C_I2COA0 (HWREG16(0x40002014))
356 #define EUSCI_B0_I2C_I2COA1 (HWREG16(0x40002016))
357 #define EUSCI_B0_I2C_I2COA2 (HWREG16(0x40002018))
358 #define EUSCI_B0_I2C_I2COA3 (HWREG16(0x4000201A))
359 #define EUSCI_B0_I2C_I2CSA (HWREG16(0x40002020))
360 #define EUSCI_B0_SPI_IE (HWREG16(0x4000202A))
361 #define EUSCI_B0_SPI_IFG (HWREG16(0x4000202C))
362 #define EUSCI_B0_SPI_IV (HWREG16(0x4000202E))
363 #define EUSCI_B0_SPI_RXBUF (HWREG16(0x4000200C))
364 #define EUSCI_B0_SPI_STATW (HWREG16(0x40002008))
365 #define EUSCI_B0_SPI_TXBUF (HWREG16(0x4000200E))
366 #define EUSCI_B1_I2C_ADDMASK (HWREG16(0x4000241E))
367 #define EUSCI_B1_I2C_ADDRX (HWREG16(0x4000241C))
368 #define UCB1BRW_L (HWREG8_L(UCB1BRW))
369 #define UCB1BRW_H (HWREG8_H(UCB1BRW))
370 #define EUSCI_B1_SPI_BRW (HWREG16(0x40002406))
371 #define UCB1CTLW0_H (HWREG8_L(UCB1CTLW0))
372 #define UCB1CTLW0_L (HWREG8_H(UCB1CTLW0))
373 #define EUSCI_B1_SPI_CTLW0 (HWREG16(0x40002400))
374 #define EUSCI_B1_I2C_I2COA0 (HWREG16(0x40002414))
375 #define EUSCI_B1_I2C_I2COA1 (HWREG16(0x40002416))
376 #define EUSCI_B1_I2C_I2COA2 (HWREG16(0x40002418))
377 #define EUSCI_B1_I2C_I2COA3 (HWREG16(0x4000241A))
378 #define EUSCI_B1_I2C_I2CSA (HWREG16(0x40002420))
379 #define EUSCI_B1_IE (HWREG16(0x4000242A))
380 #define EUSCI_B1_IFG (HWREG16(0x4000242C))
381 #define EUSCI_B1_IV (HWREG16(0x4000242E))
382 #define EUSCI_B1_SPI_RXBUF (HWREG16(0x4000240C))
383 #define EUSCI_B1_SPI_STATW (HWREG16(0x40002408))
384 #define EUSCI_B1_SPI_TXBUF (HWREG16(0x4000240E))
385 #define EUSCI_B2_I2C_ADDMASK (HWREG16(0x4000281E))
386 #define EUSCI_B2_I2C_ADDRX (HWREG16(0x4000281C))
387 #define UCB2BRW_L (HWREG8_L(UCB2BRW))
388 #define UCB2BRW_H (HWREG8_H(UCB2BRW))
389 #define EUSCI_B2_SPI_BRW (HWREG16(0x40002806))
390 #define UCB2CTLW0_H (HWREG8_L(UCB2CTLW0))
391 #define UCB2CTLW0_L (HWREG8_H(UCB2CTLW0))
392 #define EUSCI_B2_SPI_CTLW0 (HWREG16(0x40002800))
393 #define EUSCI_B2_I2C_I2COA0 (HWREG16(0x40002814))
394 #define EUSCI_B2_I2C_I2COA1 (HWREG16(0x40002816))
395 #define EUSCI_B2_I2C_I2COA2 (HWREG16(0x40002818))
396 #define EUSCI_B2_I2C_I2COA3 (HWREG16(0x4000281A))
397 #define EUSCI_B2_I2C_I2CSA (HWREG16(0x40002820))
398 #define EUSCI_B2_IE (HWREG16(0x4000282A))
399 #define EUSCI_B2_IFG (HWREG16(0x4000282C))
400 #define EUSCI_B2_IV (HWREG16(0x4000282E))
401 #define EUSCI_B2_SPI_RXBUF (HWREG16(0x4000280C))
402 #define EUSCI_B2_SPI_STATW (HWREG16(0x40002808))
403 #define EUSCI_B2_SPI_TXBUF (HWREG16(0x4000280E))
404 #define EUSCI_B3_I2C_ADDMASK (HWREG16(0x40002C1E))
405 #define EUSCI_B3_I2C_ADDRX (HWREG16(0x40002C1C))
406 #define UCB3BRW_L (HWREG8_L(UCB3BRW))
407 #define UCB3BRW_H (HWREG8_H(UCB3BRW))
408 #define EUSCI_B3_SPI_BRW (HWREG16(0x40002C06))
409 #define UCB3CTLW0_H (HWREG8_L(UCB3CTLW0))
410 #define UCB3CTLW0_L (HWREG8_H(UCB3CTLW0))
411 #define EUSCI_B3_SPI_CTLW0 (HWREG16(0x40002C00))
412 #define EUSCI_B3_I2C_I2COA0 (HWREG16(0x40002C14))
413 #define EUSCI_B3_I2C_I2COA1 (HWREG16(0x40002C16))
414 #define EUSCI_B3_I2C_I2COA2 (HWREG16(0x40002C18))
415 #define EUSCI_B3_I2C_I2COA3 (HWREG16(0x40002C1A))
416 #define EUSCI_B3_I2C_I2CSA (HWREG16(0x40002C20))
417 #define EUSCI_B3_IE (HWREG16(0x40002C2A))
418 #define EUSCI_B3_IFG (HWREG16(0x40002C2C))
419 #define EUSCI_B3_IV (HWREG16(0x40002C2E))
420 #define EUSCI_B3_SPI_RXBUF (HWREG16(0x40002C0C))
421 #define EUSCI_B3_SPI_STATW (HWREG16(0x40002C08))
422 #define EUSCI_B3_SPI_TXBUF (HWREG16(0x40002C0E))
423 #define WDT_A_CTL (HWREG16(0x4000480C))
424 #define WDTPW_VAL (0x5A00)
427 #define ADC14BATMAP_0 (0x00000000)
428 #define ADC14BATMAP_1 (0x00400000)
429 #define ADC14BUSY_0 (0x00000000)
430 #define ADC14BUSY_1 (0x00010000)
431 #define ADC14CAP1M_M (0x00007c00)
432 #define ADC14CAP1P_M (0x7c000000)
433 #define ADC14CAP2M_M (0x000003e0)
434 #define ADC14CAP2P_M (0x03e00000)
435 #define ADC14CAP3M_M (0x0000001f)
436 #define ADC14CAP3P_M (0x001f0000)
437 #define ADC14CAP4M_M (0x7c000000)
438 #define ADC14CAP4P_M (0x00007c00)
439 #define ADC14CAP5M_M (0x03e00000)
440 #define ADC14CAP5P_M (0x000003e0)
441 #define ADC14CAP6M_M (0x001f0000)
442 #define ADC14CAP6P_M (0x0000001f)
443 #define ADC14CAP7M_M (0x00007c00)
444 #define ADC14CAP7P_M (0x7c000000)
445 #define ADC14CH0MAP_0 (0x00000000)
446 #define ADC14CH0MAP_1 (0x01000000)
447 #define ADC14CH1MAP_0 (0x00000000)
448 #define ADC14CH1MAP_1 (0x02000000)
449 #define ADC14CH2MAP_0 (0x00000000)
450 #define ADC14CH2MAP_1 (0x04000000)
451 #define ADC14CH3MAP_0 (0x00000000)
452 #define ADC14CH3MAP_1 (0x08000000)
453 #define ADC14CLKCTRL (0x00000001)
454 #define ADC14DBG0 (HWREG32(0x40012340))
455 #define ADC14DF_0 (0x00000000)
456 #define ADC14DF_1 (0x00000008)
457 #define ADC14DIF_0 (0x00000000)
458 #define ADC14DIF_1 (0x00002000)
459 #define ADC14DIV_0__1 (0x00000000)
460 #define ADC14DIV_1__2 (0x00400000)
461 #define ADC14DIV_2__3 (0x00800000)
462 #define ADC14DIV_3__4 (0x00c00000)
463 #define ADC14DIV_4__5 (0x01000000)
464 #define ADC14DIV_5__6 (0x01400000)
465 #define ADC14DIV_6__7 (0x01800000)
466 #define ADC14DIV_7__8 (0x01c00000)
467 #define ADC14DSCR0 (HWREG32(0x40012380))
468 #define ADC14ENC_0 (0x00000000)
469 #define ADC14ENC_0_ADC14_DISABLED (0x00000000)
470 #define ADC14ENC_1 (0x00000002)
471 #define ADC14ENC_1_ADC14_ENABLED (0x00000002)
472 #define ADC14EOS_0 (0x00000000)
473 #define ADC14EOS_1 (0x00000080)
474 #define ADC14EOS_1_END_OF_SEQUENCE (0x00000080)
475 #define ADC14HIIE_0 (0x00000000)
476 #define ADC14HIIE_1 (0x00000008)
477 #define ADC14HIIFG_0 (0x00000000)
478 #define ADC14HIIFG_1 (0x00000008)
479 #define ADC14IE0_0 (0x00000000)
480 #define ADC14IE0_1 (0x00000001)
481 #define ADC14IE10_0 (0x00000000)
482 #define ADC14IE10_1 (0x00000400)
483 #define ADC14IE11_0 (0x00000000)
484 #define ADC14IE11_1 (0x00000800)
485 #define ADC14IE12_0 (0x00000000)
486 #define ADC14IE12_1 (0x00001000)
487 #define ADC14IE13_0 (0x00000000)
488 #define ADC14IE13_1 (0x00002000)
489 #define ADC14IE14_0 (0x00000000)
490 #define ADC14IE14_1 (0x00004000)
491 #define ADC14IE15_0 (0x00000000)
492 #define ADC14IE15_1 (0x00008000)
493 #define ADC14IE16_0 (0x00000000)
494 #define ADC14IE16_1 (0x00010000)
495 #define ADC14IE17_0 (0x00000000)
496 #define ADC14IE17_1 (0x00020000)
497 #define ADC14IE18_0 (0x00000000)
498 #define ADC14IE18_1 (0x00040000)
499 #define ADC14IE19_0 (0x00000000)
500 #define ADC14IE19_1 (0x00080000)
501 #define ADC14IE1_0 (0x00000000)
502 #define ADC14IE1_1 (0x00000002)
503 #define ADC14IE20_0 (0x00000000)
504 #define ADC14IE20_1 (0x00100000)
505 #define ADC14IE21_0 (0x00000000)
506 #define ADC14IE21_1 (0x00200000)
507 #define ADC14IE22_0 (0x00000000)
508 #define ADC14IE22_1 (0x00400000)
509 #define ADC14IE23_0 (0x00000000)
510 #define ADC14IE23_1 (0x00800000)
511 #define ADC14IE24_0 (0x00000000)
512 #define ADC14IE24_1 (0x01000000)
513 #define ADC14IE25_0 (0x00000000)
514 #define ADC14IE25_1 (0x02000000)
515 #define ADC14IE26_0 (0x00000000)
516 #define ADC14IE26_1 (0x04000000)
517 #define ADC14IE27_0 (0x00000000)
518 #define ADC14IE27_1 (0x08000000)
519 #define ADC14IE28_0 (0x00000000)
520 #define ADC14IE28_1 (0x10000000)
521 #define ADC14IE29_0 (0x00000000)
522 #define ADC14IE29_1 (0x20000000)
523 #define ADC14IE2_0 (0x00000000)
524 #define ADC14IE2_1 (0x00000004)
525 #define ADC14IE30_0 (0x00000000)
526 #define ADC14IE30_1 (0x40000000)
527 #define ADC14IE31_0 (0x00000000)
528 #define ADC14IE31_1 (0x80000000)
529 #define ADC14IE3_0 (0x00000000)
530 #define ADC14IE3_1 (0x00000008)
531 #define ADC14IE4_0 (0x00000000)
532 #define ADC14IE4_1 (0x00000010)
533 #define ADC14IE5_0 (0x00000000)
534 #define ADC14IE5_1 (0x00000020)
535 #define ADC14IE6_0 (0x00000000)
536 #define ADC14IE6_1 (0x00000040)
537 #define ADC14IE7_0 (0x00000000)
538 #define ADC14IE7_1 (0x00000080)
539 #define ADC14IE8_0 (0x00000000)
540 #define ADC14IE8_1 (0x00000100)
541 #define ADC14IE9_0 (0x00000000)
542 #define ADC14IE9_1 (0x00000200)
543 #define ADC14IFG0_0 (0x00000000)
544 #define ADC14IFG0_1 (0x00000001)
545 #define ADC14IFG10_0 (0x00000000)
546 #define ADC14IFG10_1 (0x00000400)
547 #define ADC14IFG11_0 (0x00000000)
548 #define ADC14IFG11_1 (0x00000800)
549 #define ADC14IFG12_0 (0x00000000)
550 #define ADC14IFG12_1 (0x00001000)
551 #define ADC14IFG13_0 (0x00000000)
552 #define ADC14IFG13_1 (0x00002000)
553 #define ADC14IFG14_0 (0x00000000)
554 #define ADC14IFG14_1 (0x00004000)
555 #define ADC14IFG15_0 (0x00000000)
556 #define ADC14IFG15_1 (0x00008000)
557 #define ADC14IFG16_0 (0x00000000)
558 #define ADC14IFG16_1 (0x00010000)
559 #define ADC14IFG17_0 (0x00000000)
560 #define ADC14IFG17_1 (0x00020000)
561 #define ADC14IFG18_0 (0x00000000)
562 #define ADC14IFG18_1 (0x00040000)
563 #define ADC14IFG19_0 (0x00000000)
564 #define ADC14IFG19_1 (0x00080000)
565 #define ADC14IFG1_0 (0x00000000)
566 #define ADC14IFG1_1 (0x00000002)
567 #define ADC14IFG20_0 (0x00000000)
568 #define ADC14IFG20_1 (0x00100000)
569 #define ADC14IFG21_0 (0x00000000)
570 #define ADC14IFG21_1 (0x00200000)
571 #define ADC14IFG22_0 (0x00000000)
572 #define ADC14IFG22_1 (0x00400000)
573 #define ADC14IFG23_0 (0x00000000)
574 #define ADC14IFG23_1 (0x00800000)
575 #define ADC14IFG24_0 (0x00000000)
576 #define ADC14IFG24_1 (0x01000000)
577 #define ADC14IFG25_0 (0x00000000)
578 #define ADC14IFG25_1 (0x02000000)
579 #define ADC14IFG26_0 (0x00000000)
580 #define ADC14IFG26_1 (0x04000000)
581 #define ADC14IFG27_0 (0x00000000)
582 #define ADC14IFG27_1 (0x08000000)
583 #define ADC14IFG28_0 (0x00000000)
584 #define ADC14IFG28_1 (0x10000000)
585 #define ADC14IFG29_0 (0x00000000)
586 #define ADC14IFG29_1 (0x20000000)
587 #define ADC14IFG2_0 (0x00000000)
588 #define ADC14IFG2_1 (0x00000004)
589 #define ADC14IFG30_0 (0x00000000)
590 #define ADC14IFG30_1 (0x40000000)
591 #define ADC14IFG31_1 (0x80000000)
592 #define ADC14IFG3_0 (0x00000000)
593 #define ADC14IFG3_1 (0x00000008)
594 #define ADC14IFG4_0 (0x00000000)
595 #define ADC14IFG4_1 (0x00000010)
596 #define ADC14IFG5_0 (0x00000000)
597 #define ADC14IFG5_1 (0x00000020)
598 #define ADC14IFG6_0 (0x00000000)
599 #define ADC14IFG6_1 (0x00000040)
600 #define ADC14IFG7_0 (0x00000000)
601 #define ADC14IFG7_1 (0x00000080)
602 #define ADC14IFG8_0 (0x00000000)
603 #define ADC14IFG8_1 (0x00000100)
604 #define ADC14IFG9_0 (0x00000000)
605 #define ADC14IFG9_1 (0x00000200)
606 #define ADC14INIE_0 (0x00000000)
607 #define ADC14INIE_1 (0x00000002)
608 #define ADC14INIFG_0 (0x00000000)
609 #define ADC14INIFG_1 (0x00000002)
610 #define ADC14ISSH_0 (0x00000000)
611 #define ADC14ISSH_1 (0x02000000)
612 #define ADC14LOIE_0 (0x00000000)
613 #define ADC14LOIE_1 (0x00000004)
614 #define ADC14LOIFG_0 (0x00000000)
615 #define ADC14LOIFG_1 (0x00000004)
616 #define ADC14MSC_0 (0x00000000)
617 #define ADC14MSC_1 (0x00000080)
618 #define ADC14ON_0 (0x00000000)
619 #define ADC14ON_0_ADC14_OFF (0x00000000)
620 #define ADC14ON_1 (0x00000010)
621 #define ADC14OVIE_0 (0x00000000)
622 #define ADC14OVIE_1 (0x00000010)
623 #define ADC14OVIFG_0 (0x00000000)
624 #define ADC14OVIFG_1 (0x00000010)
625 #define ADC14PDIV_0_PREDIVIDE_BY_1 (0x00000000)
626 #define ADC14PDIV_1_PREDIVIDE_BY_4 (0x40000000)
627 #define ADC14PDIV_2_PREDIVIDE_BY_32 (0x80000000)
628 #define ADC14PDIV_3_PREDIVIDE_BY_64 (0xc0000000)
629 #define ADC14RDYIE_0 (0x00000000)
630 #define ADC14RDYIE_1 (0x00000040)
631 #define ADC14RDYIFG_0 (0x00000000)
632 #define ADC14RDYIFG_1 (0x00000040)
633 #define ADC14REFBURST_0 (0x00000000)
634 #define ADC14REFBURST_1 (0x00000004)
635 #define ADC14SC_0 (0x00000000)
636 #define ADC14SC_1 (0x00000001)
637 #define ADC14SHP_0 (0x00000000)
638 #define ADC14SHP_1 (0x04000000)
639 #define ADC14SHS_0_ADC14SC_BIT (0x00000000)
640 #define ADC14SHT0_0_4 (0x00000000)
641 #define ADC14SHT0_1_8 (0x00000100)
642 #define ADC14SHT0_2_16 (0x00000200)
643 #define ADC14SHT0_3_32 (0x00000300)
644 #define ADC14SHT0_4_64 (0x00000400)
645 #define ADC14SHT0_5_96 (0x00000500)
646 #define ADC14SHT0_6_128 (0x00000600)
647 #define ADC14SHT0_7_192 (0x00000700)
648 #define ADC14SHT1_0_4 (0x00000000)
649 #define ADC14SHT1_1_8 (0x00001000)
650 #define ADC14SHT1_2_16 (0x00002000)
651 #define ADC14SHT1_3_32 (0x00003000)
652 #define ADC14SHT1_4_64 (0x00004000)
653 #define ADC14SHT1_5_96 (0x00005000)
654 #define ADC14SHT1_6_128 (0x00006000)
655 #define ADC14SHT1_7_192 (0x00007000)
656 #define ADC14SSEL_0_MODCLK (0x00000000)
657 #define ADC14SSEL_1_SYSCLK (0x00080000)
658 #define ADC14SSEL_2_ACLK (0x00100000)
659 #define ADC14SSEL_3_MCLK (0x00180000)
660 #define ADC14SSEL_4_SMCLK (0x00200000)
661 #define ADC14SSEL_5_HSMCLK (0x00280000)
662 #define ADC14TCMAP_0 (0x00000000)
663 #define ADC14TCMAP_1 (0x00800000)
664 #define ADC14TEST0 (HWREG32(0x40012300))
665 #define ADC14TEST1 (HWREG32(0x40012304))
666 #define ADC14TEST2 (HWREG32(0x40012308))
667 #define ADC14TEST3 (HWREG32(0x4001230C))
668 #define ADC14TEST4 (HWREG32(0x40012310))
669 #define ADC14TEST5 (HWREG32(0x40012314))
670 #define ADC14TEST6 (HWREG32(0x40012318))
671 #define ADC14TEST7 (HWREG32(0x4001231C))
672 #define ADC14TOVIE_0 (0x00000000)
673 #define ADC14TOVIE_1 (0x00000020)
674 #define ADC14TOVIFG_0 (0x00000000)
675 #define ADC14TOVIFG_1 (0x00000020)
676 #define ADC14WINCTH_0 (0x00000000)
677 #define ADC14WINCTH_1 (0x00008000)
678 #define ADC14WINC_0 (0x00000000)
679 #define ADC14WINC_1 (0x00004000)
680 #define ADC14_CLRIFGR0 (HWREG32(0x4001214C))
681 #define ADC14_CLRIFGR0_CLRADC14IFG0 (0x00000001)
682 #define ADC14_CLRIFGR0_CLRADC14IFG0__0 (0x00000000)
683 #define ADC14_CLRIFGR0_CLRADC14IFG0__0_NO_EFFECT (0x00000000)
684 #define ADC14_CLRIFGR0_CLRADC14IFG0__1 (0x00000001)
685 #define ADC14_CLRIFGR0_CLRADC14IFG1 (0x00000002)
686 #define ADC14_CLRIFGR0_CLRADC14IFG10 (0x00000400)
687 #define ADC14_CLRIFGR0_CLRADC14IFG10__0 (0x00000000)
688 #define ADC14_CLRIFGR0_CLRADC14IFG10__0_NO_EFFECT (0x00000000)
689 #define ADC14_CLRIFGR0_CLRADC14IFG10__1 (0x00000400)
690 #define ADC14_CLRIFGR0_CLRADC14IFG11 (0x00000800)
691 #define ADC14_CLRIFGR0_CLRADC14IFG11__0 (0x00000000)
692 #define ADC14_CLRIFGR0_CLRADC14IFG11__0_NO_EFFECT (0x00000000)
693 #define ADC14_CLRIFGR0_CLRADC14IFG11__1 (0x00000800)
694 #define ADC14_CLRIFGR0_CLRADC14IFG12 (0x00001000)
695 #define ADC14_CLRIFGR0_CLRADC14IFG12__0 (0x00000000)
696 #define ADC14_CLRIFGR0_CLRADC14IFG12__0_NO_EFFECT (0x00000000)
697 #define ADC14_CLRIFGR0_CLRADC14IFG12__1 (0x00001000)
698 #define ADC14_CLRIFGR0_CLRADC14IFG13 (0x00002000)
699 #define ADC14_CLRIFGR0_CLRADC14IFG13__0 (0x00000000)
700 #define ADC14_CLRIFGR0_CLRADC14IFG13__0_NO_EFFECT (0x00000000)
701 #define ADC14_CLRIFGR0_CLRADC14IFG13__1 (0x00002000)
702 #define ADC14_CLRIFGR0_CLRADC14IFG14 (0x00004000)
703 #define ADC14_CLRIFGR0_CLRADC14IFG14__0 (0x00000000)
704 #define ADC14_CLRIFGR0_CLRADC14IFG14__0_NO_EFFECT (0x00000000)
705 #define ADC14_CLRIFGR0_CLRADC14IFG14__1 (0x00004000)
706 #define ADC14_CLRIFGR0_CLRADC14IFG15 (0x00008000)
707 #define ADC14_CLRIFGR0_CLRADC14IFG15__0 (0x00000000)
708 #define ADC14_CLRIFGR0_CLRADC14IFG15__0_NO_EFFECT (0x00000000)
709 #define ADC14_CLRIFGR0_CLRADC14IFG15__1 (0x00008000)
710 #define ADC14_CLRIFGR0_CLRADC14IFG16 (0x00010000)
711 #define ADC14_CLRIFGR0_CLRADC14IFG16__0 (0x00000000)
712 #define ADC14_CLRIFGR0_CLRADC14IFG16__0_NO_EFFECT (0x00000000)
713 #define ADC14_CLRIFGR0_CLRADC14IFG16__1 (0x00010000)
714 #define ADC14_CLRIFGR0_CLRADC14IFG17 (0x00020000)
715 #define ADC14_CLRIFGR0_CLRADC14IFG17__0 (0x00000000)
716 #define ADC14_CLRIFGR0_CLRADC14IFG17__0_NO_EFFECT (0x00000000)
717 #define ADC14_CLRIFGR0_CLRADC14IFG17__1 (0x00020000)
718 #define ADC14_CLRIFGR0_CLRADC14IFG18 (0x00040000)
719 #define ADC14_CLRIFGR0_CLRADC14IFG18__0 (0x00000000)
720 #define ADC14_CLRIFGR0_CLRADC14IFG18__0_NO_EFFECT (0x00000000)
721 #define ADC14_CLRIFGR0_CLRADC14IFG18__1 (0x00040000)
722 #define ADC14_CLRIFGR0_CLRADC14IFG19 (0x00080000)
723 #define ADC14_CLRIFGR0_CLRADC14IFG19__0 (0x00000000)
724 #define ADC14_CLRIFGR0_CLRADC14IFG19__0_NO_EFFECT (0x00000000)
725 #define ADC14_CLRIFGR0_CLRADC14IFG19__1 (0x00080000)
726 #define ADC14_CLRIFGR0_CLRADC14IFG1__0 (0x00000000)
727 #define ADC14_CLRIFGR0_CLRADC14IFG1__0_NO_EFFECT (0x00000000)
728 #define ADC14_CLRIFGR0_CLRADC14IFG1__1 (0x00000002)
729 #define ADC14_CLRIFGR0_CLRADC14IFG2 (0x00000004)
730 #define ADC14_CLRIFGR0_CLRADC14IFG20 (0x00100000)
731 #define ADC14_CLRIFGR0_CLRADC14IFG20__0 (0x00000000)
732 #define ADC14_CLRIFGR0_CLRADC14IFG20__0_NO_EFFECT (0x00000000)
733 #define ADC14_CLRIFGR0_CLRADC14IFG20__1 (0x00100000)
734 #define ADC14_CLRIFGR0_CLRADC14IFG21 (0x00200000)
735 #define ADC14_CLRIFGR0_CLRADC14IFG21__0 (0x00000000)
736 #define ADC14_CLRIFGR0_CLRADC14IFG21__0_NO_EFFECT (0x00000000)
737 #define ADC14_CLRIFGR0_CLRADC14IFG21__1 (0x00200000)
738 #define ADC14_CLRIFGR0_CLRADC14IFG22 (0x00400000)
739 #define ADC14_CLRIFGR0_CLRADC14IFG22__0 (0x00000000)
740 #define ADC14_CLRIFGR0_CLRADC14IFG22__0_NO_EFFECT (0x00000000)
741 #define ADC14_CLRIFGR0_CLRADC14IFG22__1 (0x00400000)
742 #define ADC14_CLRIFGR0_CLRADC14IFG23 (0x00800000)
743 #define ADC14_CLRIFGR0_CLRADC14IFG23__0 (0x00000000)
744 #define ADC14_CLRIFGR0_CLRADC14IFG23__0_NO_EFFECT (0x00000000)
745 #define ADC14_CLRIFGR0_CLRADC14IFG23__1 (0x00800000)
746 #define ADC14_CLRIFGR0_CLRADC14IFG24 (0x01000000)
747 #define ADC14_CLRIFGR0_CLRADC14IFG24__0 (0x00000000)
748 #define ADC14_CLRIFGR0_CLRADC14IFG24__0_NO_EFFECT (0x00000000)
749 #define ADC14_CLRIFGR0_CLRADC14IFG24__1 (0x01000000)
750 #define ADC14_CLRIFGR0_CLRADC14IFG25 (0x02000000)
751 #define ADC14_CLRIFGR0_CLRADC14IFG25__0 (0x00000000)
752 #define ADC14_CLRIFGR0_CLRADC14IFG25__0_NO_EFFECT (0x00000000)
753 #define ADC14_CLRIFGR0_CLRADC14IFG25__1 (0x02000000)
754 #define ADC14_CLRIFGR0_CLRADC14IFG26 (0x04000000)
755 #define ADC14_CLRIFGR0_CLRADC14IFG26__0 (0x00000000)
756 #define ADC14_CLRIFGR0_CLRADC14IFG26__0_NO_EFFECT (0x00000000)
757 #define ADC14_CLRIFGR0_CLRADC14IFG26__1 (0x04000000)
758 #define ADC14_CLRIFGR0_CLRADC14IFG27 (0x08000000)
759 #define ADC14_CLRIFGR0_CLRADC14IFG27__0 (0x00000000)
760 #define ADC14_CLRIFGR0_CLRADC14IFG27__0_NO_EFFECT (0x00000000)
761 #define ADC14_CLRIFGR0_CLRADC14IFG27__1 (0x08000000)
762 #define ADC14_CLRIFGR0_CLRADC14IFG28 (0x10000000)
763 #define ADC14_CLRIFGR0_CLRADC14IFG28__0 (0x00000000)
764 #define ADC14_CLRIFGR0_CLRADC14IFG28__0_NO_EFFECT (0x00000000)
765 #define ADC14_CLRIFGR0_CLRADC14IFG28__1 (0x10000000)
766 #define ADC14_CLRIFGR0_CLRADC14IFG29 (0x20000000)
767 #define ADC14_CLRIFGR0_CLRADC14IFG29__0 (0x00000000)
768 #define ADC14_CLRIFGR0_CLRADC14IFG29__0_NO_EFFECT (0x00000000)
769 #define ADC14_CLRIFGR0_CLRADC14IFG29__1 (0x20000000)
770 #define ADC14_CLRIFGR0_CLRADC14IFG2__0 (0x00000000)
771 #define ADC14_CLRIFGR0_CLRADC14IFG2__0_NO_EFFECT (0x00000000)
772 #define ADC14_CLRIFGR0_CLRADC14IFG2__1 (0x00000004)
773 #define ADC14_CLRIFGR0_CLRADC14IFG3 (0x00000008)
774 #define ADC14_CLRIFGR0_CLRADC14IFG30 (0x40000000)
775 #define ADC14_CLRIFGR0_CLRADC14IFG30__0 (0x00000000)
776 #define ADC14_CLRIFGR0_CLRADC14IFG30__0_NO_EFFECT (0x00000000)
777 #define ADC14_CLRIFGR0_CLRADC14IFG30__1 (0x40000000)
778 #define ADC14_CLRIFGR0_CLRADC14IFG31 (0x80000000)
779 #define ADC14_CLRIFGR0_CLRADC14IFG31__0 (0x00000000)
780 #define ADC14_CLRIFGR0_CLRADC14IFG31__0_NO_EFFECT (0x00000000)
781 #define ADC14_CLRIFGR0_CLRADC14IFG31__1 (0x80000000)
782 #define ADC14_CLRIFGR0_CLRADC14IFG3__0 (0x00000000)
783 #define ADC14_CLRIFGR0_CLRADC14IFG3__0_NO_EFFECT (0x00000000)
784 #define ADC14_CLRIFGR0_CLRADC14IFG3__1 (0x00000008)
785 #define ADC14_CLRIFGR0_CLRADC14IFG4 (0x00000010)
786 #define ADC14_CLRIFGR0_CLRADC14IFG4__0 (0x00000000)
787 #define ADC14_CLRIFGR0_CLRADC14IFG4__0_NO_EFFECT (0x00000000)
788 #define ADC14_CLRIFGR0_CLRADC14IFG4__1 (0x00000010)
789 #define ADC14_CLRIFGR0_CLRADC14IFG5 (0x00000020)
790 #define ADC14_CLRIFGR0_CLRADC14IFG5__0 (0x00000000)
791 #define ADC14_CLRIFGR0_CLRADC14IFG5__0_NO_EFFECT (0x00000000)
792 #define ADC14_CLRIFGR0_CLRADC14IFG5__1 (0x00000020)
793 #define ADC14_CLRIFGR0_CLRADC14IFG6 (0x00000040)
794 #define ADC14_CLRIFGR0_CLRADC14IFG6__0 (0x00000000)
795 #define ADC14_CLRIFGR0_CLRADC14IFG6__0_NO_EFFECT (0x00000000)
796 #define ADC14_CLRIFGR0_CLRADC14IFG6__1 (0x00000040)
797 #define ADC14_CLRIFGR0_CLRADC14IFG7 (0x00000080)
798 #define ADC14_CLRIFGR0_CLRADC14IFG7__0 (0x00000000)
799 #define ADC14_CLRIFGR0_CLRADC14IFG7__0_NO_EFFECT (0x00000000)
800 #define ADC14_CLRIFGR0_CLRADC14IFG7__1 (0x00000080)
801 #define ADC14_CLRIFGR0_CLRADC14IFG8 (0x00000100)
802 #define ADC14_CLRIFGR0_CLRADC14IFG8__0 (0x00000000)
803 #define ADC14_CLRIFGR0_CLRADC14IFG8__0_NO_EFFECT (0x00000000)
804 #define ADC14_CLRIFGR0_CLRADC14IFG8__1 (0x00000100)
805 #define ADC14_CLRIFGR0_CLRADC14IFG9 (0x00000200)
806 #define ADC14_CLRIFGR0_CLRADC14IFG9__0 (0x00000000)
807 #define ADC14_CLRIFGR0_CLRADC14IFG9__0_NO_EFFECT (0x00000000)
808 #define ADC14_CLRIFGR0_CLRADC14IFG9__1 (0x00000200)
809 #define ADC14_CLRIFGR1 (HWREG32(0x40012150))
810 #define ADC14_CLRIFGR1_CLRADC14HIIFG (0x00000008)
811 #define ADC14_CLRIFGR1_CLRADC14HIIFG__0 (0x00000000)
812 #define ADC14_CLRIFGR1_CLRADC14HIIFG__0_NO_EFFECT (0x00000000)
813 #define ADC14_CLRIFGR1_CLRADC14HIIFG__1 (0x00000008)
814 #define ADC14_CLRIFGR1_CLRADC14INIFG (0x00000002)
815 #define ADC14_CLRIFGR1_CLRADC14INIFG__0 (0x00000000)
816 #define ADC14_CLRIFGR1_CLRADC14INIFG__0_NO_EFFECT (0x00000000)
817 #define ADC14_CLRIFGR1_CLRADC14INIFG__1 (0x00000002)
818 #define ADC14_CLRIFGR1_CLRADC14LOIFG (0x00000004)
819 #define ADC14_CLRIFGR1_CLRADC14LOIFG__0 (0x00000000)
820 #define ADC14_CLRIFGR1_CLRADC14LOIFG__0_NO_EFFECT (0x00000000)
821 #define ADC14_CLRIFGR1_CLRADC14LOIFG__1 (0x00000004)
822 #define ADC14_CLRIFGR1_CLRADC14OVIFG (0x00000010)
823 #define ADC14_CLRIFGR1_CLRADC14OVIFG__0 (0x00000000)
824 #define ADC14_CLRIFGR1_CLRADC14OVIFG__0_NO_EFFECT (0x00000000)
825 #define ADC14_CLRIFGR1_CLRADC14OVIFG__1 (0x00000010)
826 #define ADC14_CLRIFGR1_CLRADC14RDYIFG (0x00000040)
827 #define ADC14_CLRIFGR1_CLRADC14RDYIFG__0 (0x00000000)
828 #define ADC14_CLRIFGR1_CLRADC14RDYIFG__0_NO_EFFECT (0x00000000)
829 #define ADC14_CLRIFGR1_CLRADC14RDYIFG__1 (0x00000040)
830 #define ADC14_CLRIFGR1_CLRADC14TOVIFG (0x00000020)
831 #define ADC14_CLRIFGR1_CLRADC14TOVIFG__0 (0x00000000)
832 #define ADC14_CLRIFGR1_CLRADC14TOVIFG__0_NO_EFFECT (0x00000000)
833 #define ADC14_CLRIFGR1_CLRADC14TOVIFG__1 (0x00000020)
834 #define ADC14_CTL0 (HWREG32(0x40012000))
835 #define ADC14_CTL0_BUSY (0x00010000)
836 #define ADC14_CTL0_BUSY__0 (0x00000000)
837 #define ADC14_CTL0_BUSY__1 (0x00010000)
838 #define ADC14_CTL0_CONSEQ__0 (0x00000000)
839 #define ADC14_CTL0_CONSEQ__1 (0x00020000)
840 #define ADC14_CTL0_CONSEQ__2 (0x00040000)
841 #define ADC14_CTL0_CONSEQ__3 (0x00060000)
842 #define ADC14_CTL0_CONSEQ__M (0x00060000)
843 #define ADC14_CTL0_DIV__0 (0x00000000)
844 #define ADC14_CTL0_DIV__0__1 (0x00000000)
845 #define ADC14_CTL0_DIV__1 (0x00400000)
846 #define ADC14_CTL0_DIV__1__2 (0x00400000)
847 #define ADC14_CTL0_DIV__2 (0x00800000)
848 #define ADC14_CTL0_DIV__2__3 (0x00800000)
849 #define ADC14_CTL0_DIV__3 (0x00c00000)
850 #define ADC14_CTL0_DIV__3__4 (0x00c00000)
851 #define ADC14_CTL0_DIV__4 (0x01000000)
852 #define ADC14_CTL0_DIV__4__5 (0x01000000)
853 #define ADC14_CTL0_DIV__5 (0x01400000)
854 #define ADC14_CTL0_DIV__5__6 (0x01400000)
855 #define ADC14_CTL0_DIV__6 (0x01800000)
856 #define ADC14_CTL0_DIV__6__7 (0x01800000)
857 #define ADC14_CTL0_DIV__7 (0x01c00000)
858 #define ADC14_CTL0_DIV__7__8 (0x01c00000)
859 #define ADC14_CTL0_DIV__M (0x01c00000)
860 #define ADC14_CTL0_ENC (0x00000002)
861 #define ADC14_CTL0_ENC__0 (0x00000000)
862 #define ADC14_CTL0_ENC__0_ADC14_DISABLED (0x00000000)
863 #define ADC14_CTL0_ENC__1 (0x00000002)
864 #define ADC14_CTL0_ENC__1_ADC14_ENABLED (0x00000002)
865 #define ADC14_CTL0_ISSH (0x02000000)
866 #define ADC14_CTL0_ISSH__0 (0x00000000)
867 #define ADC14_CTL0_ISSH__1 (0x02000000)
868 #define ADC14_CTL0_MSC (0x00000080)
869 #define ADC14_CTL0_MSC__0 (0x00000000)
870 #define ADC14_CTL0_MSC__1 (0x00000080)
871 #define ADC14_CTL0_ON (0x00000010)
872 #define ADC14_CTL0_ON__0 (0x00000000)
873 #define ADC14_CTL0_ON__0_ADC14_OFF (0x00000000)
874 #define ADC14_CTL0_ON__1 (0x00000010)
875 #define ADC14_CTL0_PDIV__0 (0x00000000)
876 #define ADC14_CTL0_PDIV__0_PREDIVIDE_BY_1 (0x00000000)
877 #define ADC14_CTL0_PDIV__1 (0x40000000)
878 #define ADC14_CTL0_PDIV__1_PREDIVIDE_BY_4 (0x40000000)
879 #define ADC14_CTL0_PDIV__2 (0x80000000)
880 #define ADC14_CTL0_PDIV__2_PREDIVIDE_BY_32 (0x80000000)
881 #define ADC14_CTL0_PDIV__3 (0xc0000000)
882 #define ADC14_CTL0_PDIV__3_PREDIVIDE_BY_64 (0xc0000000)
883 #define ADC14_CTL0_PDIV__M (0xc0000000)
884 #define ADC14_CTL0_SC (0x00000001)
885 #define ADC14_CTL0_SC__0 (0x00000000)
886 #define ADC14_CTL0_SC__1 (0x00000001)
887 #define ADC14_CTL0_SHP (0x04000000)
888 #define ADC14_CTL0_SHP__0 (0x00000000)
889 #define ADC14_CTL0_SHP__1 (0x04000000)
890 #define ADC14_CTL0_SHS__0 (0x00000000)
891 #define ADC14_CTL0_SHS__0_ADC14SC_BIT (0x00000000)
892 #define ADC14_CTL0_SHS__1 (0x08000000)
893 #define ADC14_CTL0_SHS__2 (0x10000000)
894 #define ADC14_CTL0_SHS__3 (0x18000000)
895 #define ADC14_CTL0_SHS__4 (0x20000000)
896 #define ADC14_CTL0_SHS__5 (0x28000000)
897 #define ADC14_CTL0_SHS__6 (0x30000000)
898 #define ADC14_CTL0_SHS__7 (0x38000000)
899 #define ADC14_CTL0_SHS__M (0x38000000)
900 #define ADC14_CTL0_SHT0__0 (0x00000000)
901 #define ADC14_CTL0_SHT0__0_4 (0x00000000)
902 #define ADC14_CTL0_SHT0__1 (0x00000100)
903 #define ADC14_CTL0_SHT0__1_8 (0x00000100)
904 #define ADC14_CTL0_SHT0__2 (0x00000200)
905 #define ADC14_CTL0_SHT0__2_16 (0x00000200)
906 #define ADC14_CTL0_SHT0__3 (0x00000300)
907 #define ADC14_CTL0_SHT0__3_32 (0x00000300)
908 #define ADC14_CTL0_SHT0__4 (0x00000400)
909 #define ADC14_CTL0_SHT0__4_64 (0x00000400)
910 #define ADC14_CTL0_SHT0__5 (0x00000500)
911 #define ADC14_CTL0_SHT0__5_96 (0x00000500)
912 #define ADC14_CTL0_SHT0__6 (0x00000600)
913 #define ADC14_CTL0_SHT0__6_128 (0x00000600)
914 #define ADC14_CTL0_SHT0__7 (0x00000700)
915 #define ADC14_CTL0_SHT0__7_192 (0x00000700)
916 #define ADC14_CTL0_SHT0__M (0x00000f00)
917 #define ADC14_CTL0_SHT1__0 (0x00000000)
918 #define ADC14_CTL0_SHT1__0_4 (0x00000000)
919 #define ADC14_CTL0_SHT1__1 (0x00001000)
920 #define ADC14_CTL0_SHT1__1_8 (0x00001000)
921 #define ADC14_CTL0_SHT1__2 (0x00002000)
922 #define ADC14_CTL0_SHT1__2_16 (0x00002000)
923 #define ADC14_CTL0_SHT1__3 (0x00003000)
924 #define ADC14_CTL0_SHT1__3_32 (0x00003000)
925 #define ADC14_CTL0_SHT1__4 (0x00004000)
926 #define ADC14_CTL0_SHT1__4_64 (0x00004000)
927 #define ADC14_CTL0_SHT1__5 (0x00005000)
928 #define ADC14_CTL0_SHT1__5_96 (0x00005000)
929 #define ADC14_CTL0_SHT1__6 (0x00006000)
930 #define ADC14_CTL0_SHT1__6_128 (0x00006000)
931 #define ADC14_CTL0_SHT1__7 (0x00007000)
932 #define ADC14_CTL0_SHT1__7_192 (0x00007000)
933 #define ADC14_CTL0_SHT1__M (0x0000f000)
934 #define ADC14_CTL0_SSEL__0 (0x00000000)
935 #define ADC14_CTL0_SSEL__0_MODCLK (0x00000000)
936 #define ADC14_CTL0_SSEL__1 (0x00080000)
937 #define ADC14_CTL0_SSEL__1_SYSCLK (0x00080000)
938 #define ADC14_CTL0_SSEL__2 (0x00100000)
939 #define ADC14_CTL0_SSEL__2_ACLK (0x00100000)
940 #define ADC14_CTL0_SSEL__3 (0x00180000)
941 #define ADC14_CTL0_SSEL__3_MCLK (0x00180000)
942 #define ADC14_CTL0_SSEL__4 (0x00200000)
943 #define ADC14_CTL0_SSEL__4_SMCLK (0x00200000)
944 #define ADC14_CTL0_SSEL__5 (0x00280000)
945 #define ADC14_CTL0_SSEL__5_HSMCLK (0x00280000)
946 #define ADC14_CTL0_SSEL__M (0x00380000)
947 #define ADC14_CTL1 (HWREG32(0x40012004))
948 #define ADC14_CTL1_BATMAP (0x00400000)
949 #define ADC14_CTL1_BATMAP__0 (0x00000000)
950 #define ADC14_CTL1_BATMAP__1 (0x00400000)
951 #define ADC14_CTL1_CH0MAP (0x01000000)
952 #define ADC14_CTL1_CH0MAP__0 (0x00000000)
953 #define ADC14_CTL1_CH0MAP__1 (0x01000000)
954 #define ADC14_CTL1_CH1MAP (0x02000000)
955 #define ADC14_CTL1_CH1MAP__0 (0x00000000)
956 #define ADC14_CTL1_CH1MAP__1 (0x02000000)
957 #define ADC14_CTL1_CH2MAP (0x04000000)
958 #define ADC14_CTL1_CH2MAP__0 (0x00000000)
959 #define ADC14_CTL1_CH2MAP__1 (0x04000000)
960 #define ADC14_CTL1_CH3MAP (0x08000000)
961 #define ADC14_CTL1_CH3MAP__0 (0x00000000)
962 #define ADC14_CTL1_CH3MAP__1 (0x08000000)
963 #define ADC14_CTL1_CSTARTADD__M (0x001f0000)
964 #define ADC14_CTL1_DF (0x00000008)
965 #define ADC14_CTL1_DF__0 (0x00000000)
966 #define ADC14_CTL1_DF__1 (0x00000008)
967 #define ADC14_CTL1_PWRMD__0 (0x00000000)
968 #define ADC14_CTL1_PWRMD__2 (0x00000002)
969 #define ADC14_CTL1_PWRMD__M (0x00000003)
970 #define ADC14_CTL1_REFBURST (0x00000004)
971 #define ADC14_CTL1_REFBURST__0 (0x00000000)
972 #define ADC14_CTL1_REFBURST__1 (0x00000004)
973 #define ADC14_CTL1_RES__0 (0x00000000)
974 #define ADC14_CTL1_RES__1 (0x00000010)
975 #define ADC14_CTL1_RES__2 (0x00000020)
976 #define ADC14_CTL1_RES__3 (0x00000030)
977 #define ADC14_CTL1_RES__M (0x00000030)
978 #define ADC14_CTL1_TCMAP (0x00800000)
979 #define ADC14_CTL1_TCMAP__0 (0x00000000)
980 #define ADC14_CTL1_TCMAP__1 (0x00800000)
981 #define ADC14_DMACTRL (0x00000004)
982 #define ADC14_EN14BIT (0x00000008)
983 #define ADC14_HI0 (HWREG32(0x4001200C))
984 #define ADC14_HI0_HI0__M (0x0000ffff)
985 #define ADC14_HI1 (HWREG32(0x40012014))
986 #define ADC14_HI1_HI1__M (0x0000ffff)
987 #define ADC14_IER0 (HWREG32(0x4001213C))
988 #define ADC14_IER0_IE0 (0x00000001)
989 #define ADC14_IER0_IE0__0 (0x00000000)
990 #define ADC14_IER0_IE0__1 (0x00000001)
991 #define ADC14_IER0_IE1 (0x00000002)
992 #define ADC14_IER0_IE10 (0x00000400)
993 #define ADC14_IER0_IE10__0 (0x00000000)
994 #define ADC14_IER0_IE10__1 (0x00000400)
995 #define ADC14_IER0_IE11 (0x00000800)
996 #define ADC14_IER0_IE11__0 (0x00000000)
997 #define ADC14_IER0_IE11__1 (0x00000800)
998 #define ADC14_IER0_IE12 (0x00001000)
999 #define ADC14_IER0_IE12__0 (0x00000000)
1000 #define ADC14_IER0_IE12__1 (0x00001000)
1001 #define ADC14_IER0_IE13 (0x00002000)
1002 #define ADC14_IER0_IE13__0 (0x00000000)
1003 #define ADC14_IER0_IE13__1 (0x00002000)
1004 #define ADC14_IER0_IE14 (0x00004000)
1005 #define ADC14_IER0_IE14__0 (0x00000000)
1006 #define ADC14_IER0_IE14__1 (0x00004000)
1007 #define ADC14_IER0_IE15 (0x00008000)
1008 #define ADC14_IER0_IE15__0 (0x00000000)
1009 #define ADC14_IER0_IE15__1 (0x00008000)
1010 #define ADC14_IER0_IE16 (0x00010000)
1011 #define ADC14_IER0_IE16__0 (0x00000000)
1012 #define ADC14_IER0_IE16__1 (0x00010000)
1013 #define ADC14_IER0_IE17 (0x00020000)
1014 #define ADC14_IER0_IE17__0 (0x00000000)
1015 #define ADC14_IER0_IE17__1 (0x00020000)
1016 #define ADC14_IER0_IE18 (0x00040000)
1017 #define ADC14_IER0_IE18__0 (0x00000000)
1018 #define ADC14_IER0_IE18__1 (0x00040000)
1019 #define ADC14_IER0_IE19 (0x00080000)
1020 #define ADC14_IER0_IE19__0 (0x00000000)
1021 #define ADC14_IER0_IE19__1 (0x00080000)
1022 #define ADC14_IER0_IE1__0 (0x00000000)
1023 #define ADC14_IER0_IE1__1 (0x00000002)
1024 #define ADC14_IER0_IE2 (0x00000004)
1025 #define ADC14_IER0_IE20 (0x00100000)
1026 #define ADC14_IER0_IE20__0 (0x00000000)
1027 #define ADC14_IER0_IE20__1 (0x00100000)
1028 #define ADC14_IER0_IE21 (0x00200000)
1029 #define ADC14_IER0_IE21__0 (0x00000000)
1030 #define ADC14_IER0_IE21__1 (0x00200000)
1031 #define ADC14_IER0_IE22 (0x00400000)
1032 #define ADC14_IER0_IE22__0 (0x00000000)
1033 #define ADC14_IER0_IE22__1 (0x00400000)
1034 #define ADC14_IER0_IE23 (0x00800000)
1035 #define ADC14_IER0_IE23__0 (0x00000000)
1036 #define ADC14_IER0_IE23__1 (0x00800000)
1037 #define ADC14_IER0_IE24 (0x01000000)
1038 #define ADC14_IER0_IE24__0 (0x00000000)
1039 #define ADC14_IER0_IE24__1 (0x01000000)
1040 #define ADC14_IER0_IE25 (0x02000000)
1041 #define ADC14_IER0_IE25__0 (0x00000000)
1042 #define ADC14_IER0_IE25__1 (0x02000000)
1043 #define ADC14_IER0_IE26 (0x04000000)
1044 #define ADC14_IER0_IE26__0 (0x00000000)
1045 #define ADC14_IER0_IE26__1 (0x04000000)
1046 #define ADC14_IER0_IE27 (0x08000000)
1047 #define ADC14_IER0_IE27__0 (0x00000000)
1048 #define ADC14_IER0_IE27__1 (0x08000000)
1049 #define ADC14_IER0_IE28 (0x10000000)
1050 #define ADC14_IER0_IE28__0 (0x00000000)
1051 #define ADC14_IER0_IE28__1 (0x10000000)
1052 #define ADC14_IER0_IE29 (0x20000000)
1053 #define ADC14_IER0_IE29__0 (0x00000000)
1054 #define ADC14_IER0_IE29__1 (0x20000000)
1055 #define ADC14_IER0_IE2__0 (0x00000000)
1056 #define ADC14_IER0_IE2__1 (0x00000004)
1057 #define ADC14_IER0_IE3 (0x00000008)
1058 #define ADC14_IER0_IE30 (0x40000000)
1059 #define ADC14_IER0_IE30__0 (0x00000000)
1060 #define ADC14_IER0_IE30__1 (0x40000000)
1061 #define ADC14_IER0_IE31 (0x80000000)
1062 #define ADC14_IER0_IE31__0 (0x00000000)
1063 #define ADC14_IER0_IE31__1 (0x80000000)
1064 #define ADC14_IER0_IE3__0 (0x00000000)
1065 #define ADC14_IER0_IE3__1 (0x00000008)
1066 #define ADC14_IER0_IE4 (0x00000010)
1067 #define ADC14_IER0_IE4__0 (0x00000000)
1068 #define ADC14_IER0_IE4__1 (0x00000010)
1069 #define ADC14_IER0_IE5 (0x00000020)
1070 #define ADC14_IER0_IE5__0 (0x00000000)
1071 #define ADC14_IER0_IE5__1 (0x00000020)
1072 #define ADC14_IER0_IE6 (0x00000040)
1073 #define ADC14_IER0_IE6__0 (0x00000000)
1074 #define ADC14_IER0_IE6__1 (0x00000040)
1075 #define ADC14_IER0_IE7 (0x00000080)
1076 #define ADC14_IER0_IE7__0 (0x00000000)
1077 #define ADC14_IER0_IE7__1 (0x00000080)
1078 #define ADC14_IER0_IE8 (0x00000100)
1079 #define ADC14_IER0_IE8__0 (0x00000000)
1080 #define ADC14_IER0_IE8__1 (0x00000100)
1081 #define ADC14_IER0_IE9 (0x00000200)
1082 #define ADC14_IER0_IE9__0 (0x00000000)
1083 #define ADC14_IER0_IE9__1 (0x00000200)
1084 #define ADC14_IER1 (HWREG32(0x40012140))
1085 #define ADC14_IER1_HIIE (0x00000008)
1086 #define ADC14_IER1_HIIE__0 (0x00000000)
1087 #define ADC14_IER1_HIIE__1 (0x00000008)
1088 #define ADC14_IER1_INIE (0x00000002)
1089 #define ADC14_IER1_INIE__0 (0x00000000)
1090 #define ADC14_IER1_INIE__1 (0x00000002)
1091 #define ADC14_IER1_LOIE (0x00000004)
1092 #define ADC14_IER1_LOIE__0 (0x00000000)
1093 #define ADC14_IER1_LOIE__1 (0x00000004)
1094 #define ADC14_IER1_OVIE (0x00000010)
1095 #define ADC14_IER1_OVIE__0 (0x00000000)
1096 #define ADC14_IER1_OVIE__1 (0x00000010)
1097 #define ADC14_IER1_RDYIE (0x00000040)
1098 #define ADC14_IER1_RDYIE__0 (0x00000000)
1099 #define ADC14_IER1_RDYIE__1 (0x00000040)
1100 #define ADC14_IER1_TOVIE (0x00000020)
1101 #define ADC14_IER1_TOVIE__0 (0x00000000)
1102 #define ADC14_IER1_TOVIE__1 (0x00000020)
1103 #define ADC14_IFGR0 (HWREG32(0x40012144))
1104 #define ADC14_IFGR0_IFG0 (0x00000001)
1105 #define ADC14_IFGR0_IFG0__0 (0x00000000)
1106 #define ADC14_IFGR0_IFG0__1 (0x00000001)
1107 #define ADC14_IFGR0_IFG1 (0x00000002)
1108 #define ADC14_IFGR0_IFG10 (0x00000400)
1109 #define ADC14_IFGR0_IFG10__0 (0x00000000)
1110 #define ADC14_IFGR0_IFG10__1 (0x00000400)
1111 #define ADC14_IFGR0_IFG11 (0x00000800)
1112 #define ADC14_IFGR0_IFG11__0 (0x00000000)
1113 #define ADC14_IFGR0_IFG11__1 (0x00000800)
1114 #define ADC14_IFGR0_IFG12 (0x00001000)
1115 #define ADC14_IFGR0_IFG12__0 (0x00000000)
1116 #define ADC14_IFGR0_IFG12__1 (0x00001000)
1117 #define ADC14_IFGR0_IFG13 (0x00002000)
1118 #define ADC14_IFGR0_IFG13__0 (0x00000000)
1119 #define ADC14_IFGR0_IFG13__1 (0x00002000)
1120 #define ADC14_IFGR0_IFG14 (0x00004000)
1121 #define ADC14_IFGR0_IFG14__0 (0x00000000)
1122 #define ADC14_IFGR0_IFG14__1 (0x00004000)
1123 #define ADC14_IFGR0_IFG15 (0x00008000)
1124 #define ADC14_IFGR0_IFG15__0 (0x00000000)
1125 #define ADC14_IFGR0_IFG15__1 (0x00008000)
1126 #define ADC14_IFGR0_IFG16 (0x00010000)
1127 #define ADC14_IFGR0_IFG16__0 (0x00000000)
1128 #define ADC14_IFGR0_IFG16__1 (0x00010000)
1129 #define ADC14_IFGR0_IFG17 (0x00020000)
1130 #define ADC14_IFGR0_IFG17__0 (0x00000000)
1131 #define ADC14_IFGR0_IFG17__1 (0x00020000)
1132 #define ADC14_IFGR0_IFG18 (0x00040000)
1133 #define ADC14_IFGR0_IFG18__0 (0x00000000)
1134 #define ADC14_IFGR0_IFG18__1 (0x00040000)
1135 #define ADC14_IFGR0_IFG19 (0x00080000)
1136 #define ADC14_IFGR0_IFG19__0 (0x00000000)
1137 #define ADC14_IFGR0_IFG19__1 (0x00080000)
1138 #define ADC14_IFGR0_IFG1__0 (0x00000000)
1139 #define ADC14_IFGR0_IFG1__1 (0x00000002)
1140 #define ADC14_IFGR0_IFG2 (0x00000004)
1141 #define ADC14_IFGR0_IFG20 (0x00100000)
1142 #define ADC14_IFGR0_IFG20__0 (0x00000000)
1143 #define ADC14_IFGR0_IFG20__1 (0x00100000)
1144 #define ADC14_IFGR0_IFG21 (0x00200000)
1145 #define ADC14_IFGR0_IFG21__0 (0x00000000)
1146 #define ADC14_IFGR0_IFG21__1 (0x00200000)
1147 #define ADC14_IFGR0_IFG22 (0x00400000)
1148 #define ADC14_IFGR0_IFG22__0 (0x00000000)
1149 #define ADC14_IFGR0_IFG22__1 (0x00400000)
1150 #define ADC14_IFGR0_IFG23 (0x00800000)
1151 #define ADC14_IFGR0_IFG23__0 (0x00000000)
1152 #define ADC14_IFGR0_IFG23__1 (0x00800000)
1153 #define ADC14_IFGR0_IFG24 (0x01000000)
1154 #define ADC14_IFGR0_IFG24__0 (0x00000000)
1155 #define ADC14_IFGR0_IFG24__1 (0x01000000)
1156 #define ADC14_IFGR0_IFG25 (0x02000000)
1157 #define ADC14_IFGR0_IFG25__0 (0x00000000)
1158 #define ADC14_IFGR0_IFG25__1 (0x02000000)
1159 #define ADC14_IFGR0_IFG26 (0x04000000)
1160 #define ADC14_IFGR0_IFG26__0 (0x00000000)
1161 #define ADC14_IFGR0_IFG26__1 (0x04000000)
1162 #define ADC14_IFGR0_IFG27 (0x08000000)
1163 #define ADC14_IFGR0_IFG27__0 (0x00000000)
1164 #define ADC14_IFGR0_IFG27__1 (0x08000000)
1165 #define ADC14_IFGR0_IFG28 (0x10000000)
1166 #define ADC14_IFGR0_IFG28__0 (0x00000000)
1167 #define ADC14_IFGR0_IFG28__1 (0x10000000)
1168 #define ADC14_IFGR0_IFG29 (0x20000000)
1169 #define ADC14_IFGR0_IFG29__0 (0x00000000)
1170 #define ADC14_IFGR0_IFG29__1 (0x20000000)
1171 #define ADC14_IFGR0_IFG2__0 (0x00000000)
1172 #define ADC14_IFGR0_IFG2__1 (0x00000004)
1173 #define ADC14_IFGR0_IFG3 (0x00000008)
1174 #define ADC14_IFGR0_IFG30 (0x40000000)
1175 #define ADC14_IFGR0_IFG30__0 (0x00000000)
1176 #define ADC14_IFGR0_IFG30__1 (0x40000000)
1177 #define ADC14_IFGR0_IFG31 (0x80000000)
1178 #define ADC14_IFGR0_IFG31__1 (0x80000000)
1179 #define ADC14_IFGR0_IFG3__0 (0x00000000)
1180 #define ADC14_IFGR0_IFG3__1 (0x00000008)
1181 #define ADC14_IFGR0_IFG4 (0x00000010)
1182 #define ADC14_IFGR0_IFG4__0 (0x00000000)
1183 #define ADC14_IFGR0_IFG4__1 (0x00000010)
1184 #define ADC14_IFGR0_IFG5 (0x00000020)
1185 #define ADC14_IFGR0_IFG5__0 (0x00000000)
1186 #define ADC14_IFGR0_IFG5__1 (0x00000020)
1187 #define ADC14_IFGR0_IFG6 (0x00000040)
1188 #define ADC14_IFGR0_IFG6__0 (0x00000000)
1189 #define ADC14_IFGR0_IFG6__1 (0x00000040)
1190 #define ADC14_IFGR0_IFG7 (0x00000080)
1191 #define ADC14_IFGR0_IFG7__0 (0x00000000)
1192 #define ADC14_IFGR0_IFG7__1 (0x00000080)
1193 #define ADC14_IFGR0_IFG8 (0x00000100)
1194 #define ADC14_IFGR0_IFG8__0 (0x00000000)
1195 #define ADC14_IFGR0_IFG8__1 (0x00000100)
1196 #define ADC14_IFGR0_IFG9 (0x00000200)
1197 #define ADC14_IFGR0_IFG9__0 (0x00000000)
1198 #define ADC14_IFGR0_IFG9__1 (0x00000200)
1199 #define ADC14_IFGR1 (HWREG32(0x40012148))
1200 #define ADC14_IFGR1_HIIFG (0x00000008)
1201 #define ADC14_IFGR1_HIIFG__0 (0x00000000)
1202 #define ADC14_IFGR1_HIIFG__1 (0x00000008)
1203 #define ADC14_IFGR1_INIFG (0x00000002)
1204 #define ADC14_IFGR1_INIFG__0 (0x00000000)
1205 #define ADC14_IFGR1_INIFG__1 (0x00000002)
1206 #define ADC14_IFGR1_LOIFG (0x00000004)
1207 #define ADC14_IFGR1_LOIFG__0 (0x00000000)
1208 #define ADC14_IFGR1_LOIFG__1 (0x00000004)
1209 #define ADC14_IFGR1_OVIFG (0x00000010)
1210 #define ADC14_IFGR1_OVIFG__0 (0x00000000)
1211 #define ADC14_IFGR1_OVIFG__1 (0x00000010)
1212 #define ADC14_IFGR1_RDYIFG (0x00000040)
1213 #define ADC14_IFGR1_RDYIFG__0 (0x00000000)
1214 #define ADC14_IFGR1_RDYIFG__1 (0x00000040)
1215 #define ADC14_IFGR1_TOVIFG (0x00000020)
1216 #define ADC14_IFGR1_TOVIFG__0 (0x00000000)
1217 #define ADC14_IFGR1_TOVIFG__1 (0x00000020)
1218 #define ADC14_INTCTRL (0x00000002)
1219 #define ADC14_IV (HWREG32(0x40012154))
1220 #define ADC14_LO0 (HWREG32(0x40012008))
1221 #define ADC14_LO0_LO0__M (0x0000ffff)
1222 #define ADC14_LO1 (HWREG32(0x40012010))
1223 #define ADC14_LO1_LO1__M (0x0000ffff)
1224 #define ADC14_MCTL0 (HWREG32(0x40012018))
1225 #define ADC14_MCTL1 (HWREG32(0x4001201C))
1226 #define ADC14_MCTL10 (HWREG32(0x40012040))
1227 #define ADC14_MCTL11 (HWREG32(0x40012044))
1228 #define ADC14_MCTL12 (HWREG32(0x40012048))
1229 #define ADC14_MCTL13 (HWREG32(0x4001204C))
1230 #define ADC14_MCTL14 (HWREG32(0x40012050))
1231 #define ADC14_MCTL15 (HWREG32(0x40012054))
1232 #define ADC14_MCTL16 (HWREG32(0x40012058))
1233 #define ADC14_MCTL17 (HWREG32(0x4001205C))
1234 #define ADC14_MCTL18 (HWREG32(0x40012060))
1235 #define ADC14_MCTL19 (HWREG32(0x40012064))
1236 #define ADC14_MCTL2 (HWREG32(0x40012020))
1237 #define ADC14_MCTL20 (HWREG32(0x40012068))
1238 #define ADC14_MCTL21 (HWREG32(0x4001206C))
1239 #define ADC14_MCTL22 (HWREG32(0x40012070))
1240 #define ADC14_MCTL23 (HWREG32(0x40012074))
1241 #define ADC14_MCTL24 (HWREG32(0x40012078))
1242 #define ADC14_MCTL25 (HWREG32(0x4001207C))
1243 #define ADC14_MCTL26 (HWREG32(0x40012080))
1244 #define ADC14_MCTL27 (HWREG32(0x40012084))
1245 #define ADC14_MCTL28 (HWREG32(0x40012088))
1246 #define ADC14_MCTL29 (HWREG32(0x4001208C))
1247 #define ADC14_MCTL3 (HWREG32(0x40012024))
1248 #define ADC14_MCTL30 (HWREG32(0x40012090))
1249 #define ADC14_MCTL31 (HWREG32(0x40012094))
1250 #define ADC14_MCTL4 (HWREG32(0x40012028))
1251 #define ADC14_MCTL5 (HWREG32(0x4001202C))
1252 #define ADC14_MCTL6 (HWREG32(0x40012030))
1253 #define ADC14_MCTL7 (HWREG32(0x40012034))
1254 #define ADC14_MCTL8 (HWREG32(0x40012038))
1255 #define ADC14_MCTL9 (HWREG32(0x4001203C))
1256 #define ADC14_MCTL_DIF (0x00002000)
1257 #define ADC14_MCTL_DIF__0 (0x00000000)
1258 #define ADC14_MCTL_DIF__1 (0x00002000)
1259 #define ADC14_MCTL_EOS (0x00000080)
1260 #define ADC14_MCTL_EOS__0 (0x00000000)
1261 #define ADC14_MCTL_EOS__1 (0x00000080)
1262 #define ADC14_MCTL_EOS__1_END_OF_SEQUENCE (0x00000080)
1263 #define ADC14_MCTL_INCH__0 (0x00000000)
1264 #define ADC14_MCTL_INCH__1 (0x00000001)
1265 #define ADC14_MCTL_INCH__10 (0x0000000a)
1266 #define ADC14_MCTL_INCH__11 (0x0000000b)
1267 #define ADC14_MCTL_INCH__12 (0x0000000c)
1268 #define ADC14_MCTL_INCH__13 (0x0000000d)
1269 #define ADC14_MCTL_INCH__14 (0x0000000e)
1270 #define ADC14_MCTL_INCH__15 (0x0000000f)
1271 #define ADC14_MCTL_INCH__16 (0x00000010)
1272 #define ADC14_MCTL_INCH__17 (0x00000011)
1273 #define ADC14_MCTL_INCH__18 (0x00000012)
1274 #define ADC14_MCTL_INCH__19 (0x00000013)
1275 #define ADC14_MCTL_INCH__2 (0x00000002)
1276 #define ADC14_MCTL_INCH__20 (0x00000014)
1277 #define ADC14_MCTL_INCH__21 (0x00000015)
1278 #define ADC14_MCTL_INCH__22 (0x00000016)
1279 #define ADC14_MCTL_INCH__23 (0x00000017)
1280 #define ADC14_MCTL_INCH__24 (0x00000018)
1281 #define ADC14_MCTL_INCH__25 (0x00000019)
1282 #define ADC14_MCTL_INCH__26 (0x0000001a)
1283 #define ADC14_MCTL_INCH__27 (0x0000001b)
1284 #define ADC14_MCTL_INCH__28 (0x0000001c)
1285 #define ADC14_MCTL_INCH__29 (0x0000001d)
1286 #define ADC14_MCTL_INCH__3 (0x00000003)
1287 #define ADC14_MCTL_INCH__30 (0x0000001e)
1288 #define ADC14_MCTL_INCH__31 (0x0000001f)
1289 #define ADC14_MCTL_INCH__4 (0x00000004)
1290 #define ADC14_MCTL_INCH__5 (0x00000005)
1291 #define ADC14_MCTL_INCH__6 (0x00000006)
1292 #define ADC14_MCTL_INCH__7 (0x00000007)
1293 #define ADC14_MCTL_INCH__8 (0x00000008)
1294 #define ADC14_MCTL_INCH__9 (0x00000009)
1295 #define ADC14_MCTL_INCH__M (0x0000001f)
1296 #define ADC14_MCTL_VRSEL__0 (0x00000000)
1297 #define ADC14_MCTL_VRSEL__1 (0x00000100)
1298 #define ADC14_MCTL_VRSEL__14 (0x00000e00)
1299 #define ADC14_MCTL_VRSEL__15 (0x00000f00)
1300 #define ADC14_MCTL_VRSEL__M (0x00000f00)
1301 #define ADC14_MCTL_WINC (0x00004000)
1302 #define ADC14_MCTL_WINCTH (0x00008000)
1303 #define ADC14_MCTL_WINCTH__0 (0x00000000)
1304 #define ADC14_MCTL_WINCTH__1 (0x00008000)
1305 #define ADC14_MCTL_WINC__0 (0x00000000)
1306 #define ADC14_MCTL_WINC__1 (0x00004000)
1307 #define ADC14_MEM0 (HWREG32(0x40012098))
1308 #define ADC14_MEM1 (HWREG32(0x4001209C))
1309 #define ADC14_MEM10 (HWREG32(0x400120C0))
1310 #define ADC14_MEM11 (HWREG32(0x400120C4))
1311 #define ADC14_MEM12 (HWREG32(0x400120C8))
1312 #define ADC14_MEM13 (HWREG32(0x400120CC))
1313 #define ADC14_MEM14 (HWREG32(0x400120D0))
1314 #define ADC14_MEM15 (HWREG32(0x400120D4))
1315 #define ADC14_MEM16 (HWREG32(0x400120D8))
1316 #define ADC14_MEM17 (HWREG32(0x400120DC))
1317 #define ADC14_MEM18 (HWREG32(0x400120E0))
1318 #define ADC14_MEM19 (HWREG32(0x400120E4))
1319 #define ADC14_MEM2 (HWREG32(0x400120A0))
1320 #define ADC14_MEM20 (HWREG32(0x400120E8))
1321 #define ADC14_MEM21 (HWREG32(0x400120EC))
1322 #define ADC14_MEM22 (HWREG32(0x400120F0))
1323 #define ADC14_MEM23 (HWREG32(0x400120F4))
1324 #define ADC14_MEM24 (HWREG32(0x400120F8))
1325 #define ADC14_MEM25 (HWREG32(0x400120FC))
1326 #define ADC14_MEM26 (HWREG32(0x40012100))
1327 #define ADC14_MEM27 (HWREG32(0x40012104))
1328 #define ADC14_MEM28 (HWREG32(0x40012108))
1329 #define ADC14_MEM29 (HWREG32(0x4001210C))
1330 #define ADC14_MEM3 (HWREG32(0x400120A4))
1331 #define ADC14_MEM30 (HWREG32(0x40012110))
1332 #define ADC14_MEM31 (HWREG32(0x40012114))
1333 #define ADC14_MEM4 (HWREG32(0x400120A8))
1334 #define ADC14_MEM5 (HWREG32(0x400120AC))
1335 #define ADC14_MEM6 (HWREG32(0x400120B0))
1336 #define ADC14_MEM7 (HWREG32(0x400120B4))
1337 #define ADC14_MEM8 (HWREG32(0x400120B8))
1338 #define ADC14_MEM9 (HWREG32(0x400120BC))
1339 #define ADC14_MEM_CONVERSION_RESULTS__M (0x0000ffff)
1340 #define ADC14_NUMCH_M (0x00000060)
1341 #define ADC14_TESTPORTSEL20_M (0x00000700)
1342 #define ADC14_TMBOOST (0x02000000)
1343 #define ADC14_TMCLKDEL_M (0xc0000000)
1344 #define ADC14_TMCMRFI (0x00000010)
1345 #define ADC14_TMENCAL_M (0x00c00000)
1346 #define ADC14_TMEXTREF_M (0x00000060)
1347 #define ADC14_TMFINESTORE_M (0x00000300)
1348 #define ADC14_TMHIBW_M (0x00003000)
1349 #define ADC14_TMHPMC (0x00000200)
1350 #define ADC14_TMHPMF (0x00000100)
1351 #define ADC14_TMIBIAS_M (0x00000003)
1352 #define ADC14_TMIPREAMPF_M (0x000f0000)
1353 #define ADC14_TMLPMREF_M (0x0c000000)
1354 #define ADC14_TMMUXON (0x00000080)
1355 #define ADC14_TMPMLATCHC_M (0x70000000)
1356 #define ADC14_TMPMLATCHF_M (0x07000000)
1357 #define ADC14_TMPREAMPC_M (0x000000f0)
1358 #define ADC14_TMPREAMPF_M (0x0000000f)
1359 #define ADC14_TMREF1CTRL_M (0x00001c00)
1360 #define ADC14_TMREF2CTRL_M (0x0000e000)
1361 #define ADC14_TMREFINTPAD (0x00000080)
1362 #define ADC14_TMREFOUTCTRL_M (0x00000007)
1363 #define ADC14_TMSELCAPZ_M (0x30000000)
1364 #define ADC14_TMSPARE_M (0x0000ff00)
1365 #define ADC14_TSTCHEN_M (0x00006000)
1366 #define ADC14_TSTCHSEL3932_M (0x000000ff)
1367 #define AES256_ACTL0 (HWREG16(0x40003C00))
1368 #define AES256_ACTL0_CMEN (0x8000)
1369 #define AES256_ACTL0_CMEN__0 (0x0000)
1370 #define AES256_ACTL0_CMEN__1 (0x8000)
1371 #define AES256_ACTL0_CM__0 (0x0000)
1372 #define AES256_ACTL0_CM__0_ECB (0x0000)
1373 #define AES256_ACTL0_CM__1 (0x0020)
1374 #define AES256_ACTL0_CM__1_CBC (0x0020)
1375 #define AES256_ACTL0_CM__2 (0x0040)
1376 #define AES256_ACTL0_CM__2_OFB (0x0040)
1377 #define AES256_ACTL0_CM__3 (0x0060)
1378 #define AES256_ACTL0_CM__3_CFB (0x0060)
1379 #define AES256_ACTL0_CM__M (0x0060)
1380 #define AES256_ACTL0_ERRFG (0x0800)
1381 #define AES256_ACTL0_ERRFG__0 (0x0000)
1382 #define AES256_ACTL0_ERRFG__0_NO_ERROR (0x0000)
1383 #define AES256_ACTL0_ERRFG__1 (0x0800)
1384 #define AES256_ACTL0_ERRFG__1_ERROR_OCCURRED (0x0800)
1385 #define AES256_ACTL0_KL__0 (0x0000)
1386 #define AES256_ACTL0_KL__1 (0x0004)
1387 #define AES256_ACTL0_KL__2 (0x0008)
1388 #define AES256_ACTL0_KL__M (0x000c)
1389 #define AES256_ACTL0_OP__0 (0x0000)
1390 #define AES256_ACTL0_OP__0_ENCRYPTION (0x0000)
1391 #define AES256_ACTL0_OP__1 (0x0001)
1392 #define AES256_ACTL0_OP__2 (0x0002)
1393 #define AES256_ACTL0_OP__3 (0x0003)
1394 #define AES256_ACTL0_OP__M (0x0003)
1395 #define AES256_ACTL0_RDYIE (0x1000)
1396 #define AES256_ACTL0_RDYIE__0 (0x0000)
1397 #define AES256_ACTL0_RDYIE__1 (0x1000)
1398 #define AES256_ACTL0_RDYIFG (0x0100)
1399 #define AES256_ACTL0_RDYIFG__0 (0x0000)
1400 #define AES256_ACTL0_RDYIFG__1 (0x0100)
1401 #define AES256_ACTL0_SWRST (0x0080)
1402 #define AES256_ACTL0_SWRST__0 (0x0000)
1403 #define AES256_ACTL0_SWRST__0_NO_RESET (0x0000)
1404 #define AES256_ACTL0_SWRST__1 (0x0080)
1405 #define AES256_ACTL1 (HWREG16(0x40003C02))
1406 #define AES256_ACTL1_BLKCNT__M (0x00ff)
1407 #define AES256_ADIN (HWREG16(0x40003C08))
1408 #define AES256_ADIN_DIN0__M (0x00ff)
1409 #define AES256_ADIN_DIN1__M (0xff00)
1410 #define AES256_ADOUT (HWREG16(0x40003C0A))
1411 #define AES256_ADOUT_DOUT0__M (0x00ff)
1412 #define AES256_ADOUT_DOUT1__M (0xff00)
1413 #define AES256_AKEY (HWREG16(0x40003C06))
1414 #define AES256_AKEY_KEY0__M (0x00ff)
1415 #define AES256_AKEY_KEY1__M (0xff00)
1416 #define AES256_ASTAT (HWREG16(0x40003C04))
1417 #define AES256_ASTAT_BUSY (0x0001)
1418 #define AES256_ASTAT_BUSY__0 (0x0000)
1419 #define AES256_ASTAT_BUSY__0_NOT_BUSY (0x0000)
1420 #define AES256_ASTAT_BUSY__1 (0x0001)
1421 #define AES256_ASTAT_BUSY__1_BUSY (0x0001)
1422 #define AES256_ASTAT_DINCNT__M (0x0f00)
1423 #define AES256_ASTAT_DINWR (0x0004)
1424 #define AES256_ASTAT_DINWR__0 (0x0000)
1425 #define AES256_ASTAT_DINWR__1 (0x0004)
1426 #define AES256_ASTAT_DOUTCNT__M (0xf000)
1427 #define AES256_ASTAT_DOUTRD (0x0008)
1428 #define AES256_ASTAT_DOUTRD__0 (0x0000)
1429 #define AES256_ASTAT_DOUTRD__1 (0x0008)
1430 #define AES256_ASTAT_DOUTRD__1_ALL_BYTES_READ (0x0008)
1431 #define AES256_ASTAT_KEYCNT__M (0x00f0)
1432 #define AES256_ASTAT_KEYWR (0x0002)
1433 #define AES256_ASTAT_KEYWR__0 (0x0000)
1434 #define AES256_ASTAT_KEYWR__1 (0x0002)
1435 #define AES256_AXDIN (HWREG16(0x40003C0C))
1436 #define AES256_AXDIN_XDIN0__M (0x00ff)
1437 #define AES256_AXDIN_XDIN1__M (0xff00)
1438 #define AES256_AXIN (HWREG16(0x40003C0E))
1439 #define AES256_AXIN_XIN0__M (0x00ff)
1440 #define AES256_AXIN_XIN1__M (0xff00)
1441 #define AESBLKCNT0_L (0x0001)
1442 #define AESBLKCNT1_L (0x0002)
1443 #define AESBLKCNT2_L (0x0004)
1444 #define AESBLKCNT3_L (0x0008)
1445 #define AESBLKCNT4_L (0x0010)
1446 #define AESBLKCNT5_L (0x0020)
1447 #define AESBLKCNT6_L (0x0040)
1448 #define AESBLKCNT7_L (0x0080)
1449 #define AESBUSY_L (0x0001)
1450 #define AESCM0_L (0x0020)
1451 #define AESCM1_L (0x0040)
1452 #define AESCMEN_H (0x0080)
1453 #define AESDINCNT0_H (0x0001)
1454 #define AESDINCNT1_H (0x0002)
1455 #define AESDINCNT2_H (0x0004)
1456 #define AESDINCNT3_H (0x0008)
1457 #define AESDINWR_L (0x0004)
1458 #define AESDOUTCNT0_H (0x0010)
1459 #define AESDOUTCNT1_H (0x0020)
1460 #define AESDOUTCNT2_H (0x0040)
1461 #define AESDOUTCNT3_H (0x0080)
1462 #define AESDOUTRD_L (0x0008)
1463 #define AESERRFG_H (0x0008)
1464 #define AESKEYCNT0_L (0x0010)
1465 #define AESKEYCNT1_L (0x0020)
1466 #define AESKEYCNT2_L (0x0040)
1467 #define AESKEYCNT3_L (0x0080)
1468 #define AESKEYWR_L (0x0002)
1469 #define AESKL0_L (0x0004)
1470 #define AESKL1_L (0x0008)
1471 #define AESKL__128 (0x0000)
1472 #define AESKL__192 (0x0004)
1473 #define AESKL__256 (0x0008)
1474 #define AESOP0_L (0x0001)
1475 #define AESOP1_L (0x0002)
1476 #define AESRDYIE_H (0x0010)
1477 #define AESRDYIFG_H (0x0001)
1478 #define AESSWRST_L (0x0080)
1479 #define AESTRIG (0x0010)
1480 #define AESTRIG_L (0x0010)
1481 #define AUX3RST (0x0002)
1482 #define BCD2BIN (RTC_C_BCD2BIN)
1483 #define BGMODE_H (0x0008)
1484 #define BIN2BCD (RTC_C_BIN2BCD)
1485 #define CAPES (0x0004)
1486 #define CAPEV (0x0001)
1487 #define CAPSIO (0x0200)
1488 #define CAPSIO0CTL (CAPTIO0_CTL)
1489 #define CAPSIO1CTL (CAPTIO1_CTL)
1490 #define CAPSIOEN (0x0100)
1491 #define CAPSIOEN_H (0x0001)
1492 #define CAPSIOPISEL0 (0x0002)
1493 #define CAPSIOPISEL0_L (0x0002)
1494 #define CAPSIOPISEL1 (0x0004)
1495 #define CAPSIOPISEL1_L (0x0004)
1496 #define CAPSIOPISEL2 (0x0008)
1497 #define CAPSIOPISEL2_L (0x0008)
1498 #define CAPSIOPOSEL0 (0x0010)
1499 #define CAPSIOPOSEL0_L (0x0010)
1500 #define CAPSIOPOSEL1 (0x0020)
1501 #define CAPSIOPOSEL1_L (0x0020)
1502 #define CAPSIOPOSEL2 (0x0040)
1503 #define CAPSIOPOSEL2_L (0x0040)
1504 #define CAPSIOPOSEL3 (0x0080)
1505 #define CAPSIOPOSEL3_L (0x0080)
1506 #define CAPSIO_H (0x0002)
1507 #define CAPTIO0_CTL (HWREG16(0x4000540E))
1508 #define CAPTIO0_CTL_EN (0x0100)
1509 #define CAPTIO0_CTL_EN__0 (0x0000)
1510 #define CAPTIO0_CTL_EN__1 (0x0100)
1511 #define CAPTIO0_CTL_PISEL__0 (0x0000)
1512 #define CAPTIO0_CTL_PISEL__0_PX_0 (0x0000)
1513 #define CAPTIO0_CTL_PISEL__1 (0x0002)
1514 #define CAPTIO0_CTL_PISEL__1_PX_1 (0x0002)
1515 #define CAPTIO0_CTL_PISEL__2 (0x0004)
1516 #define CAPTIO0_CTL_PISEL__2_PX_2 (0x0004)
1517 #define CAPTIO0_CTL_PISEL__3 (0x0006)
1518 #define CAPTIO0_CTL_PISEL__3_PX_3 (0x0006)
1519 #define CAPTIO0_CTL_PISEL__4 (0x0008)
1520 #define CAPTIO0_CTL_PISEL__4_PX_4 (0x0008)
1521 #define CAPTIO0_CTL_PISEL__5 (0x000a)
1522 #define CAPTIO0_CTL_PISEL__5_PX_5 (0x000a)
1523 #define CAPTIO0_CTL_PISEL__6 (0x000c)
1524 #define CAPTIO0_CTL_PISEL__6_PX_6 (0x000c)
1525 #define CAPTIO0_CTL_PISEL__7 (0x000e)
1526 #define CAPTIO0_CTL_PISEL__7_PX_7 (0x000e)
1527 #define CAPTIO0_CTL_PISEL__M (0x000e)
1528 #define CAPTIO0_CTL_POSEL__0 (0x0000)
1529 #define CAPTIO0_CTL_POSEL__0_PX___PJ (0x0000)
1530 #define CAPTIO0_CTL_POSEL__1 (0x0010)
1531 #define CAPTIO0_CTL_POSEL__10 (0x00a0)
1532 #define CAPTIO0_CTL_POSEL__10_PX___P10 (0x00a0)
1533 #define CAPTIO0_CTL_POSEL__11 (0x00b0)
1534 #define CAPTIO0_CTL_POSEL__11_PX___P11 (0x00b0)
1535 #define CAPTIO0_CTL_POSEL__12 (0x00c0)
1536 #define CAPTIO0_CTL_POSEL__12_PX___P12 (0x00c0)
1537 #define CAPTIO0_CTL_POSEL__13 (0x00d0)
1538 #define CAPTIO0_CTL_POSEL__13_PX___P13 (0x00d0)
1539 #define CAPTIO0_CTL_POSEL__14 (0x00e0)
1540 #define CAPTIO0_CTL_POSEL__14_PX___P14 (0x00e0)
1541 #define CAPTIO0_CTL_POSEL__15 (0x00f0)
1542 #define CAPTIO0_CTL_POSEL__15_PX___P15 (0x00f0)
1543 #define CAPTIO0_CTL_POSEL__1_PX___P1 (0x0010)
1544 #define CAPTIO0_CTL_POSEL__2 (0x0020)
1545 #define CAPTIO0_CTL_POSEL__2_PX___P2 (0x0020)
1546 #define CAPTIO0_CTL_POSEL__3 (0x0030)
1547 #define CAPTIO0_CTL_POSEL__3_PX___P3 (0x0030)
1548 #define CAPTIO0_CTL_POSEL__4 (0x0040)
1549 #define CAPTIO0_CTL_POSEL__4_PX___P4 (0x0040)
1550 #define CAPTIO0_CTL_POSEL__5 (0x0050)
1551 #define CAPTIO0_CTL_POSEL__5_PX___P5 (0x0050)
1552 #define CAPTIO0_CTL_POSEL__6 (0x0060)
1553 #define CAPTIO0_CTL_POSEL__6_PX___P6 (0x0060)
1554 #define CAPTIO0_CTL_POSEL__7 (0x0070)
1555 #define CAPTIO0_CTL_POSEL__7_PX___P7 (0x0070)
1556 #define CAPTIO0_CTL_POSEL__8 (0x0080)
1557 #define CAPTIO0_CTL_POSEL__8_PX___P8 (0x0080)
1558 #define CAPTIO0_CTL_POSEL__9 (0x0090)
1559 #define CAPTIO0_CTL_POSEL__9_PX___P9 (0x0090)
1560 #define CAPTIO0_CTL_POSEL__M (0x00f0)
1561 #define CAPTIO0_CTL_STATE (0x0200)
1562 #define CAPTIO0_CTL_STATE__0 (0x0000)
1563 #define CAPTIO0_CTL_STATE__1 (0x0200)
1564 #define CAPTIO1_CTL (HWREG16(0x4000580E))
1565 #define CAPTIO1_CTL_EN (0x0100)
1566 #define CAPTIO1_CTL_EN__0 (0x0000)
1567 #define CAPTIO1_CTL_EN__1 (0x0100)
1568 #define CAPTIO1_CTL_PISEL__0 (0x0000)
1569 #define CAPTIO1_CTL_PISEL__0_PX_0 (0x0000)
1570 #define CAPTIO1_CTL_PISEL__1 (0x0002)
1571 #define CAPTIO1_CTL_PISEL__1_PX_1 (0x0002)
1572 #define CAPTIO1_CTL_PISEL__2 (0x0004)
1573 #define CAPTIO1_CTL_PISEL__2_PX_2 (0x0004)
1574 #define CAPTIO1_CTL_PISEL__3 (0x0006)
1575 #define CAPTIO1_CTL_PISEL__3_PX_3 (0x0006)
1576 #define CAPTIO1_CTL_PISEL__4 (0x0008)
1577 #define CAPTIO1_CTL_PISEL__4_PX_4 (0x0008)
1578 #define CAPTIO1_CTL_PISEL__5 (0x000a)
1579 #define CAPTIO1_CTL_PISEL__5_PX_5 (0x000a)
1580 #define CAPTIO1_CTL_PISEL__6 (0x000c)
1581 #define CAPTIO1_CTL_PISEL__6_PX_6 (0x000c)
1582 #define CAPTIO1_CTL_PISEL__7 (0x000e)
1583 #define CAPTIO1_CTL_PISEL__7_PX_7 (0x000e)
1584 #define CAPTIO1_CTL_PISEL__M (0x000e)
1585 #define CAPTIO1_CTL_POSEL__0 (0x0000)
1586 #define CAPTIO1_CTL_POSEL__0_PX___PJ (0x0000)
1587 #define CAPTIO1_CTL_POSEL__1 (0x0010)
1588 #define CAPTIO1_CTL_POSEL__10 (0x00a0)
1589 #define CAPTIO1_CTL_POSEL__10_PX___P10 (0x00a0)
1590 #define CAPTIO1_CTL_POSEL__11 (0x00b0)
1591 #define CAPTIO1_CTL_POSEL__11_PX___P11 (0x00b0)
1592 #define CAPTIO1_CTL_POSEL__12 (0x00c0)
1593 #define CAPTIO1_CTL_POSEL__12_PX___P12 (0x00c0)
1594 #define CAPTIO1_CTL_POSEL__13 (0x00d0)
1595 #define CAPTIO1_CTL_POSEL__13_PX___P13 (0x00d0)
1596 #define CAPTIO1_CTL_POSEL__14 (0x00e0)
1597 #define CAPTIO1_CTL_POSEL__14_PX___P14 (0x00e0)
1598 #define CAPTIO1_CTL_POSEL__15 (0x00f0)
1599 #define CAPTIO1_CTL_POSEL__15_PX___P15 (0x00f0)
1600 #define CAPTIO1_CTL_POSEL__1_PX___P1 (0x0010)
1601 #define CAPTIO1_CTL_POSEL__2 (0x0020)
1602 #define CAPTIO1_CTL_POSEL__2_PX___P2 (0x0020)
1603 #define CAPTIO1_CTL_POSEL__3 (0x0030)
1604 #define CAPTIO1_CTL_POSEL__3_PX___P3 (0x0030)
1605 #define CAPTIO1_CTL_POSEL__4 (0x0040)
1606 #define CAPTIO1_CTL_POSEL__4_PX___P4 (0x0040)
1607 #define CAPTIO1_CTL_POSEL__5 (0x0050)
1608 #define CAPTIO1_CTL_POSEL__5_PX___P5 (0x0050)
1609 #define CAPTIO1_CTL_POSEL__6 (0x0060)
1610 #define CAPTIO1_CTL_POSEL__6_PX___P6 (0x0060)
1611 #define CAPTIO1_CTL_POSEL__7 (0x0070)
1612 #define CAPTIO1_CTL_POSEL__7_PX___P7 (0x0070)
1613 #define CAPTIO1_CTL_POSEL__8 (0x0080)
1614 #define CAPTIO1_CTL_POSEL__8_PX___P8 (0x0080)
1615 #define CAPTIO1_CTL_POSEL__9 (0x0090)
1616 #define CAPTIO1_CTL_POSEL__9_PX___P9 (0x0090)
1617 #define CAPTIO1_CTL_POSEL__M (0x00f0)
1618 #define CAPTIO1_CTL_STATE (0x0200)
1619 #define CAPTIO1_CTL_STATE__0 (0x0000)
1620 #define CAPTIO1_CTL_STATE__1 (0x0200)
1621 #define CCIS0 (0x1000)
1622 #define CCIS1 (0x2000)
1623 #define CE0CTL0_H (HWREG8_H(CE0CTL0))
1624 #define CE0CTL0_L (HWREG8_L(CE0CTL0))
1625 #define CE0CTL1_H (HWREG8_H(CE0CTL1))
1626 #define CE0CTL1_L (HWREG8_L(CE0CTL1))
1627 #define CE0CTL2_H (HWREG8_H(CE0CTL2))
1628 #define CE0CTL2_L (HWREG8_L(CE0CTL2))
1629 #define CE0CTL3_H (HWREG8_H(CE0CTL3))
1630 #define CE0CTL3_L (HWREG8_L(CE0CTL3))
1631 #define CE0EX (0x0020)
1632 #define CE0EX_L (0x0020)
1633 #define CE0F (0x0004)
1634 #define CE0FDLY0 (0x0040)
1635 #define CE0FDLY0_L (0x0040)
1636 #define CE0FDLY1 (0x0080)
1637 #define CE0FDLY1_L (0x0080)
1638 #define CE0FDLY_0 (0x0000)
1639 #define CE0FDLY_1 (0x0040)
1640 #define CE0FDLY_2 (0x0080)
1641 #define CE0FDLY_3 (0x00C0)
1642 #define CE0F_L (0x0004)
1643 #define CE0IE (0x0100)
1644 #define CE0IES (0x0008)
1645 #define CE0IES_L (0x0008)
1646 #define CE0IE_H (0x0001)
1647 #define CE0IFG (0x0001)
1648 #define CE0IFG_L (0x0001)
1649 #define CE0IIE (0x0200)
1650 #define CE0IIE_H (0x0002)
1651 #define CE0IIFG (0x0002)
1652 #define CE0IIFG_L (0x0002)
1653 #define CE0IMEN (0x8000)
1654 #define CE0IMEN_H (0x0080)
1655 #define CE0IMSEL0 (0x0100)
1656 #define CE0IMSEL0_H (0x0001)
1657 #define CE0IMSEL1 (0x0200)
1658 #define CE0IMSEL1_H (0x0002)
1659 #define CE0IMSEL2 (0x0400)
1660 #define CE0IMSEL2_H (0x0004)
1661 #define CE0IMSEL3 (0x0800)
1662 #define CE0IMSEL3_H (0x0008)
1663 #define CE0IMSEL_0 (0x0000)
1664 #define CE0IMSEL_1 (0x0100)
1665 #define CE0IMSEL_10 (0x0A00)
1666 #define CE0IMSEL_11 (0x0B00)
1667 #define CE0IMSEL_12 (0x0C00)
1668 #define CE0IMSEL_13 (0x0D00)
1669 #define CE0IMSEL_14 (0x0E00)
1670 #define CE0IMSEL_15 (0x0F00)
1671 #define CE0IMSEL_2 (0x0200)
1672 #define CE0IMSEL_3 (0x0300)
1673 #define CE0IMSEL_4 (0x0400)
1674 #define CE0IMSEL_5 (0x0500)
1675 #define CE0IMSEL_6 (0x0600)
1676 #define CE0IMSEL_7 (0x0700)
1677 #define CE0IMSEL_8 (0x0800)
1678 #define CE0IMSEL_9 (0x0900)
1679 #define CE0INT_H (HWREG8_H(CE0INT))
1680 #define CE0INT_L (HWREG8_L(CE0INT))
1681 #define CE0IPEN (0x0080)
1682 #define CE0IPEN_L (0x0080)
1683 #define CE0IPSEL0 (0x0001)
1684 #define CE0IPSEL0_L (0x0001)
1685 #define CE0IPSEL1 (0x0002)
1686 #define CE0IPSEL1_L (0x0002)
1687 #define CE0IPSEL2 (0x0004)
1688 #define CE0IPSEL2_L (0x0004)
1689 #define CE0IPSEL3 (0x0008)
1690 #define CE0IPSEL3_L (0x0008)
1691 #define CE0IPSEL_0 (0x0000)
1692 #define CE0IPSEL_1 (0x0001)
1693 #define CE0IPSEL_10 (0x000A)
1694 #define CE0IPSEL_11 (0x000B)
1695 #define CE0IPSEL_12 (0x000C)
1696 #define CE0IPSEL_13 (0x000D)
1697 #define CE0IPSEL_14 (0x000E)
1698 #define CE0IPSEL_15 (0x000F)
1699 #define CE0IPSEL_2 (0x0002)
1700 #define CE0IPSEL_3 (0x0003)
1701 #define CE0IPSEL_4 (0x0004)
1702 #define CE0IPSEL_5 (0x0005)
1703 #define CE0IPSEL_6 (0x0006)
1704 #define CE0IPSEL_7 (0x0007)
1705 #define CE0IPSEL_8 (0x0008)
1706 #define CE0IPSEL_9 (0x0009)
1707 #define CE0IV_CEIFG (0x0002)
1708 #define CE0IV_CEIIFG (0x0004)
1709 #define CE0IV_CERDYIFG (0x000A)
1710 #define CE0IV_H (HWREG8_H(CE0IV))
1711 #define CE0IV_L (HWREG8_L(CE0IV))
1712 #define CE0IV_NONE (0x0000)
1713 #define CE0MRVL (0x0800)
1714 #define CE0MRVL_H (0x0008)
1715 #define CE0MRVS (0x1000)
1716 #define CE0MRVS_H (0x0010)
1717 #define CE0ON (0x0400)
1718 #define CE0ON_H (0x0004)
1719 #define CE0OUT (0x0001)
1720 #define CE0OUTPOL (0x0002)
1721 #define CE0OUTPOL_L (0x0002)
1722 #define CE0OUT_L (0x0001)
1723 #define CE0PD0 (0x0001)
1724 #define CE0PD0_L (0x0001)
1725 #define CE0PD1 (0x0002)
1726 #define CE0PD10 (0x0400)
1727 #define CE0PD10_H (0x0004)
1728 #define CE0PD11 (0x0800)
1729 #define CE0PD11_H (0x0008)
1730 #define CE0PD12 (0x1000)
1731 #define CE0PD12_H (0x0010)
1732 #define CE0PD13 (0x2000)
1733 #define CE0PD13_H (0x0020)
1734 #define CE0PD14 (0x4000)
1735 #define CE0PD14_H (0x0040)
1736 #define CE0PD15 (0x8000)
1737 #define CE0PD15_H (0x0080)
1738 #define CE0PD1_L (0x0002)
1739 #define CE0PD2 (0x0004)
1740 #define CE0PD2_L (0x0004)
1741 #define CE0PD3 (0x0008)
1742 #define CE0PD3_L (0x0008)
1743 #define CE0PD4 (0x0010)
1744 #define CE0PD4_L (0x0010)
1745 #define CE0PD5 (0x0020)
1746 #define CE0PD5_L (0x0020)
1747 #define CE0PD6 (0x0040)
1748 #define CE0PD6_L (0x0040)
1749 #define CE0PD7 (0x0080)
1750 #define CE0PD7_L (0x0080)
1751 #define CE0PD8 (0x0100)
1752 #define CE0PD8_H (0x0001)
1753 #define CE0PD9 (0x0200)
1754 #define CE0PD9_H (0x0002)
1755 #define CE0PWRMD0 (0x0100)
1756 #define CE0PWRMD0_H (0x0001)
1757 #define CE0PWRMD1 (0x0200)
1758 #define CE0PWRMD1_H (0x0002)
1759 #define CE0PWRMD_0 (0x0000)
1760 #define CE0PWRMD_1 (0x0100)
1761 #define CE0PWRMD_2 (0x0200)
1762 #define CE0PWRMD_3 (0x0300)
1763 #define CE0RDYIE (0x1000)
1764 #define CE0RDYIE_H (0x0010)
1765 #define CE0RDYIFG (0x0010)
1766 #define CE0RDYIFG_L (0x0010)
1767 #define CE0REF00 (0x0001)
1768 #define CE0REF00_L (0x0001)
1769 #define CE0REF01 (0x0002)
1770 #define CE0REF01_L (0x0002)
1771 #define CE0REF02 (0x0004)
1772 #define CE0REF02_L (0x0004)
1773 #define CE0REF03 (0x0008)
1774 #define CE0REF03_L (0x0008)
1775 #define CE0REF04 (0x0010)
1776 #define CE0REF04_L (0x0010)
1777 #define CE0REF0_0 (0x0000)
1778 #define CE0REF0_10 (0x000A)
1779 #define CE0REF0_11 (0x000B)
1780 #define CE0REF0_12 (0x000C)
1781 #define CE0REF0_13 (0x000D)
1782 #define CE0REF0_14 (0x000E)
1783 #define CE0REF0_15 (0x000F)
1784 #define CE0REF0_16 (0x0010)
1785 #define CE0REF0_17 (0x0011)
1786 #define CE0REF0_18 (0x0012)
1787 #define CE0REF0_19 (0x0013)
1788 #define CE0REF0_2 (0x0002)
1789 #define CE0REF0_20 (0x0014)
1790 #define CE0REF0_21 (0x0015)
1791 #define CE0REF0_22 (0x0016)
1792 #define CE0REF0_23 (0x0017)
1793 #define CE0REF0_24 (0x0018)
1794 #define CE0REF0_25 (0x0019)
1795 #define CE0REF0_26 (0x001A)
1796 #define CE0REF0_27 (0x001B)
1797 #define CE0REF0_28 (0x001C)
1798 #define CE0REF0_29 (0x001D)
1799 #define CE0REF0_3 (0x0003)
1800 #define CE0REF0_30 (0x001E)
1801 #define CE0REF0_31 (0x001F)
1802 #define CE0REF0_4 (0x0004)
1803 #define CE0REF0_5 (0x0005)
1804 #define CE0REF0_6 (0x0006)
1805 #define CE0REF0_7 (0x0007)
1806 #define CE0REF0_8 (0x0008)
1807 #define CE0REF0_9 (0x0009)
1808 #define CE0REF10 (0x0100)
1809 #define CE0REF10_H (0x0001)
1810 #define CE0REF11 (0x0200)
1811 #define CE0REF11_H (0x0002)
1812 #define CE0REF12 (0x0400)
1813 #define CE0REF12_H (0x0004)
1814 #define CE0REF13 (0x0800)
1815 #define CE0REF13_H (0x0008)
1816 #define CE0REF14 (0x1000)
1817 #define CE0REF14_H (0x0010)
1818 #define CE0REF1_0 (0x0000)
1819 #define CE0REF1_1 (0x0100)
1820 #define CE0REF1_10 (0x0A00)
1821 #define CE0REF1_11 (0x0B00)
1822 #define CE0REF1_12 (0x0C00)
1823 #define CE0REF1_13 (0x0D00)
1824 #define CE0REF1_14 (0x0E00)
1825 #define CE0REF1_15 (0x0F00)
1826 #define CE0REF1_16 (0x1000)
1827 #define CE0REF1_17 (0x1100)
1828 #define CE0REF1_18 (0x1200)
1829 #define CE0REF1_19 (0x1300)
1830 #define CE0REF1_2 (0x0200)
1831 #define CE0REF1_20 (0x1400)
1832 #define CE0REF1_21 (0x1500)
1833 #define CE0REF1_22 (0x1600)
1834 #define CE0REF1_23 (0x1700)
1835 #define CE0REF1_24 (0x1800)
1836 #define CE0REF1_25 (0x1900)
1837 #define CE0REF1_26 (0x1A00)
1838 #define CE0REF1_27 (0x1B00)
1839 #define CE0REF1_28 (0x1C00)
1840 #define CE0REF1_29 (0x1D00)
1841 #define CE0REF1_3 (0x0300)
1842 #define CE0REF1_30 (0x1E00)
1843 #define CE0REF1_31 (0x1F00)
1844 #define CE0REF1_4 (0x0400)
1845 #define CE0REF1_5 (0x0500)
1846 #define CE0REF1_6 (0x0600)
1847 #define CE0REF1_7 (0x0700)
1848 #define CE0REF1_8 (0x0800)
1849 #define CE0REF1_9 (0x0900)
1850 #define CE0REFACC (0x8000)
1851 #define CE0REFACC_H (0x0080)
1852 #define CE0REFL0 (0x2000)
1853 #define CE0REFL0_H (0x0020)
1854 #define CE0REFL1 (0x4000)
1855 #define CE0REFL1_H (0x0040)
1856 #define CE0REFL_0 (0x0000)
1857 #define CE0REFL_1 (0x2000)
1858 #define CE0REFL_2 (0x4000)
1859 #define CE0REFL_3 (0x6000)
1860 #define CE0RS0 (0x0040)
1861 #define CE0RS0_L (0x0040)
1862 #define CE0RS1 (0x0080)
1863 #define CE0RS1_L (0x0080)
1864 #define CE0RSEL (0x0020)
1865 #define CE0RSEL_L (0x0020)
1866 #define CE0RS_0 (0x0000)
1867 #define CE0RS_2 (0x0080)
1868 #define CE0RS_3 (0x00C0)
1869 #define CE0SHORT (0x0010)
1870 #define CE0SHORT_L (0x0010)
1871 #define CECTL0 (COMP_E0_CTL0)
1872 #define CECTL0_H (HWREG8_H(CECTL0))
1873 #define CECTL0_L (HWREG8_L(CECTL0))
1874 #define CECTL1 (COMP_E0_CTL1)
1875 #define CECTL1_H (HWREG8_H(CECTL1))
1876 #define CECTL1_L (HWREG8_L(CECTL1))
1877 #define CECTL2 (COMP_E0_CTL2)
1878 #define CECTL2_H (HWREG8_H(CECTL2))
1879 #define CECTL2_L (HWREG8_L(CECTL2))
1880 #define CECTL3 (COMP_E0_CTL3)
1881 #define CECTL3_H (HWREG8_H(CECTL3))
1882 #define CECTL3_L (HWREG8_L(CECTL3))
1883 #define CEEX_L (0x0020)
1884 #define CEFDLY0 (0x0040)
1885 #define CEFDLY0_L (0x0040)
1886 #define CEFDLY1 (0x0080)
1887 #define CEFDLY1_L (0x0080)
1888 #define CEF_L (0x0004)
1889 #define CEIES_L (0x0008)
1890 #define CEIE_H (0x0001)
1891 #define CEIFG_L (0x0001)
1892 #define CEIIE_H (0x0002)
1893 #define CEIIFG_L (0x0002)
1894 #define CEIMEN_H (0x0080)
1895 #define CEIMSEL0 (0x0100)
1896 #define CEIMSEL0_H (0x0001)
1897 #define CEIMSEL1 (0x0200)
1898 #define CEIMSEL1_H (0x0002)
1899 #define CEIMSEL2 (0x0400)
1900 #define CEIMSEL2_H (0x0004)
1901 #define CEIMSEL3 (0x0800)
1902 #define CEIMSEL3_H (0x0008)
1903 #define CEIMSEL_0 (0x0000)
1904 #define CEIMSEL_1 (0x0100)
1905 #define CEIMSEL_10 (0x0A00)
1906 #define CEIMSEL_11 (0x0B00)
1907 #define CEIMSEL_12 (0x0C00)
1908 #define CEIMSEL_13 (0x0D00)
1909 #define CEIMSEL_14 (0x0E00)
1910 #define CEIMSEL_15 (0x0F00)
1911 #define CEIMSEL_2 (0x0200)
1912 #define CEIMSEL_3 (0x0300)
1913 #define CEIMSEL_4 (0x0400)
1914 #define CEIMSEL_5 (0x0500)
1915 #define CEIMSEL_6 (0x0600)
1916 #define CEIMSEL_7 (0x0700)
1917 #define CEIMSEL_8 (0x0800)
1918 #define CEIMSEL_9 (0x0900)
1919 #define CEINT (COMP_E0_INT)
1920 #define CEINT_H (HWREG8_H(CEINT))
1921 #define CEINT_L (HWREG8_L(CEINT))
1922 #define CEIPEN_L (0x0080)
1923 #define CEIPSEL0 (0x0001)
1924 #define CEIPSEL0_L (0x0001)
1925 #define CEIPSEL1 (0x0002)
1926 #define CEIPSEL1_L (0x0002)
1927 #define CEIPSEL2 (0x0004)
1928 #define CEIPSEL2_L (0x0004)
1929 #define CEIPSEL3 (0x0008)
1930 #define CEIPSEL3_L (0x0008)
1931 #define CEIPSEL_0 (0x0000)
1932 #define CEIPSEL_1 (0x0001)
1933 #define CEIPSEL_10 (0x000A)
1934 #define CEIPSEL_11 (0x000B)
1935 #define CEIPSEL_12 (0x000C)
1936 #define CEIPSEL_13 (0x000D)
1937 #define CEIPSEL_14 (0x000E)
1938 #define CEIPSEL_15 (0x000F)
1939 #define CEIPSEL_2 (0x0002)
1940 #define CEIPSEL_3 (0x0003)
1941 #define CEIPSEL_4 (0x0004)
1942 #define CEIPSEL_5 (0x0005)
1943 #define CEIPSEL_6 (0x0006)
1944 #define CEIPSEL_7 (0x0007)
1945 #define CEIPSEL_8 (0x0008)
1946 #define CEIPSEL_9 (0x0009)
1947 #define CEIV (COMP_E0_IV)
1948 #define CEIV_CEIFG (0x0002)
1949 #define CEIV_CEIIFG (0x0004)
1950 #define CEIV_CERDYIFG (0x000A)
1951 #define CEIV_H (HWREG8_H(CEIV))
1952 #define CEIV_L (HWREG8_L(CEIV))
1953 #define CEIV_NONE (0x0000)
1954 #define CEMRVL_H (0x0008)
1955 #define CEMRVS_H (0x0010)
1956 #define CEON_H (0x0004)
1957 #define CEOUTPOL_L (0x0002)
1958 #define CEOUT_L (0x0001)
1959 #define CEPD0_L (0x0001)
1960 #define CEPD10_H (0x0004)
1961 #define CEPD11_H (0x0008)
1962 #define CEPD12_H (0x0010)
1963 #define CEPD13_H (0x0020)
1964 #define CEPD14_H (0x0040)
1965 #define CEPD15_H (0x0080)
1966 #define CEPD1_L (0x0002)
1967 #define CEPD2_L (0x0004)
1968 #define CEPD3_L (0x0008)
1969 #define CEPD4_L (0x0010)
1970 #define CEPD5_L (0x0020)
1971 #define CEPD6_L (0x0040)
1972 #define CEPD7_L (0x0080)
1973 #define CEPD8_H (0x0001)
1974 #define CEPD9_H (0x0002)
1975 #define CEPWRMD0 (0x0100)
1976 #define CEPWRMD0_H (0x0001)
1977 #define CEPWRMD1 (0x0200)
1978 #define CEPWRMD1_H (0x0002)
1979 #define CEPWRMD_3 (0x0300)
1980 #define CERDYIE_H (0x0010)
1981 #define CERDYIFG_L (0x0010)
1982 #define CEREF00 (0x0001)
1983 #define CEREF00_L (0x0001)
1984 #define CEREF01 (0x0002)
1985 #define CEREF01_L (0x0002)
1986 #define CEREF02 (0x0004)
1987 #define CEREF02_L (0x0004)
1988 #define CEREF03 (0x0008)
1989 #define CEREF03_L (0x0008)
1990 #define CEREF04 (0x0010)
1991 #define CEREF04_L (0x0010)
1992 #define CEREF0_0 (0x0000)
1993 #define CEREF0_1 (0x0001)
1994 #define CEREF0_10 (0x000A)
1995 #define CEREF0_11 (0x000B)
1996 #define CEREF0_12 (0x000C)
1997 #define CEREF0_13 (0x000D)
1998 #define CEREF0_14 (0x000E)
1999 #define CEREF0_15 (0x000F)
2000 #define CEREF0_16 (0x0010)
2001 #define CEREF0_17 (0x0011)
2002 #define CEREF0_18 (0x0012)
2003 #define CEREF0_19 (0x0013)
2004 #define CEREF0_2 (0x0002)
2005 #define CEREF0_20 (0x0014)
2006 #define CEREF0_21 (0x0015)
2007 #define CEREF0_22 (0x0016)
2008 #define CEREF0_23 (0x0017)
2009 #define CEREF0_24 (0x0018)
2010 #define CEREF0_25 (0x0019)
2011 #define CEREF0_26 (0x001A)
2012 #define CEREF0_27 (0x001B)
2013 #define CEREF0_28 (0x001C)
2014 #define CEREF0_29 (0x001D)
2015 #define CEREF0_3 (0x0003)
2016 #define CEREF0_30 (0x001E)
2017 #define CEREF0_31 (0x001F)
2018 #define CEREF0_4 (0x0004)
2019 #define CEREF0_5 (0x0005)
2020 #define CEREF0_6 (0x0006)
2021 #define CEREF0_7 (0x0007)
2022 #define CEREF0_8 (0x0008)
2023 #define CEREF0_9 (0x0009)
2024 #define CEREF10 (0x0100)
2025 #define CEREF10_H (0x0001)
2026 #define CEREF11 (0x0200)
2027 #define CEREF11_H (0x0002)
2028 #define CEREF12 (0x0400)
2029 #define CEREF12_H (0x0004)
2030 #define CEREF13 (0x0800)
2031 #define CEREF13_H (0x0008)
2032 #define CEREF14 (0x1000)
2033 #define CEREF14_H (0x0010)
2034 #define CEREF1_0 (0x0000)
2035 #define CEREF1_1 (0x0100)
2036 #define CEREF1_10 (0x0A00)
2037 #define CEREF1_11 (0x0B00)
2038 #define CEREF1_12 (0x0C00)
2039 #define CEREF1_13 (0x0D00)
2040 #define CEREF1_14 (0x0E00)
2041 #define CEREF1_15 (0x0F00)
2042 #define CEREF1_16 (0x1000)
2043 #define CEREF1_17 (0x1100)
2044 #define CEREF1_18 (0x1200)
2045 #define CEREF1_19 (0x1300)
2046 #define CEREF1_2 (0x0200)
2047 #define CEREF1_20 (0x1400)
2048 #define CEREF1_21 (0x1500)
2049 #define CEREF1_22 (0x1600)
2050 #define CEREF1_23 (0x1700)
2051 #define CEREF1_24 (0x1800)
2052 #define CEREF1_25 (0x1900)
2053 #define CEREF1_26 (0x1A00)
2054 #define CEREF1_27 (0x1B00)
2055 #define CEREF1_28 (0x1C00)
2056 #define CEREF1_29 (0x1D00)
2057 #define CEREF1_3 (0x0300)
2058 #define CEREF1_30 (0x1E00)
2059 #define CEREF1_31 (0x1F00)
2060 #define CEREF1_4 (0x0400)
2061 #define CEREF1_5 (0x0500)
2062 #define CEREF1_6 (0x0600)
2063 #define CEREF1_7 (0x0700)
2064 #define CEREF1_8 (0x0800)
2065 #define CEREF1_9 (0x0900)
2066 #define CEREFACC_H (0x0080)
2067 #define CEREFL0 (0x2000)
2068 #define CEREFL0_H (0x0020)
2069 #define CEREFL1 (0x4000)
2070 #define CEREFL1_H (0x0040)
2071 #define CERS0 (0x0040)
2072 #define CERS0_L (0x0040)
2073 #define CERS1 (0x0080)
2074 #define CERS1_L (0x0080)
2075 #define CERSEL_L (0x0020)
2076 #define CESHORT_L (0x0010)
2077 #define CLRADC14HIIFG_0 (0x00000000)
2078 #define CLRADC14HIIFG_0_NO_EFFECT (0x00000000)
2079 #define CLRADC14HIIFG_1 (0x00000008)
2080 #define CLRADC14IFG0_0 (0x00000000)
2081 #define CLRADC14IFG0_0_NO_EFFECT (0x00000000)
2082 #define CLRADC14IFG0_1 (0x00000001)
2083 #define CLRADC14IFG10_0 (0x00000000)
2084 #define CLRADC14IFG10_0_NO_EFFECT (0x00000000)
2085 #define CLRADC14IFG10_1 (0x00000400)
2086 #define CLRADC14IFG11_0 (0x00000000)
2087 #define CLRADC14IFG11_0_NO_EFFECT (0x00000000)
2088 #define CLRADC14IFG11_1 (0x00000800)
2089 #define CLRADC14IFG12_0 (0x00000000)
2090 #define CLRADC14IFG12_0_NO_EFFECT (0x00000000)
2091 #define CLRADC14IFG12_1 (0x00001000)
2092 #define CLRADC14IFG13_0 (0x00000000)
2093 #define CLRADC14IFG13_0_NO_EFFECT (0x00000000)
2094 #define CLRADC14IFG13_1 (0x00002000)
2095 #define CLRADC14IFG14_0 (0x00000000)
2096 #define CLRADC14IFG14_0_NO_EFFECT (0x00000000)
2097 #define CLRADC14IFG14_1 (0x00004000)
2098 #define CLRADC14IFG15_0 (0x00000000)
2099 #define CLRADC14IFG15_0_NO_EFFECT (0x00000000)
2100 #define CLRADC14IFG15_1 (0x00008000)
2101 #define CLRADC14IFG16_0 (0x00000000)
2102 #define CLRADC14IFG16_0_NO_EFFECT (0x00000000)
2103 #define CLRADC14IFG16_1 (0x00010000)
2104 #define CLRADC14IFG17_0 (0x00000000)
2105 #define CLRADC14IFG17_0_NO_EFFECT (0x00000000)
2106 #define CLRADC14IFG17_1 (0x00020000)
2107 #define CLRADC14IFG18_0 (0x00000000)
2108 #define CLRADC14IFG18_0_NO_EFFECT (0x00000000)
2109 #define CLRADC14IFG18_1 (0x00040000)
2110 #define CLRADC14IFG19_0 (0x00000000)
2111 #define CLRADC14IFG19_0_NO_EFFECT (0x00000000)
2112 #define CLRADC14IFG19_1 (0x00080000)
2113 #define CLRADC14IFG1_0 (0x00000000)
2114 #define CLRADC14IFG1_0_NO_EFFECT (0x00000000)
2115 #define CLRADC14IFG1_1 (0x00000002)
2116 #define CLRADC14IFG20_0 (0x00000000)
2117 #define CLRADC14IFG20_0_NO_EFFECT (0x00000000)
2118 #define CLRADC14IFG20_1 (0x00100000)
2119 #define CLRADC14IFG21_0 (0x00000000)
2120 #define CLRADC14IFG21_0_NO_EFFECT (0x00000000)
2121 #define CLRADC14IFG21_1 (0x00200000)
2122 #define CLRADC14IFG22_0 (0x00000000)
2123 #define CLRADC14IFG22_0_NO_EFFECT (0x00000000)
2124 #define CLRADC14IFG22_1 (0x00400000)
2125 #define CLRADC14IFG23_0 (0x00000000)
2126 #define CLRADC14IFG23_0_NO_EFFECT (0x00000000)
2127 #define CLRADC14IFG23_1 (0x00800000)
2128 #define CLRADC14IFG24_0 (0x00000000)
2129 #define CLRADC14IFG24_0_NO_EFFECT (0x00000000)
2130 #define CLRADC14IFG24_1 (0x01000000)
2131 #define CLRADC14IFG25_0 (0x00000000)
2132 #define CLRADC14IFG25_0_NO_EFFECT (0x00000000)
2133 #define CLRADC14IFG25_1 (0x02000000)
2134 #define CLRADC14IFG26_0 (0x00000000)
2135 #define CLRADC14IFG26_0_NO_EFFECT (0x00000000)
2136 #define CLRADC14IFG26_1 (0x04000000)
2137 #define CLRADC14IFG27_0 (0x00000000)
2138 #define CLRADC14IFG27_0_NO_EFFECT (0x00000000)
2139 #define CLRADC14IFG27_1 (0x08000000)
2140 #define CLRADC14IFG28_0 (0x00000000)
2141 #define CLRADC14IFG28_0_NO_EFFECT (0x00000000)
2142 #define CLRADC14IFG28_1 (0x10000000)
2143 #define CLRADC14IFG29_0 (0x00000000)
2144 #define CLRADC14IFG29_0_NO_EFFECT (0x00000000)
2145 #define CLRADC14IFG29_1 (0x20000000)
2146 #define CLRADC14IFG2_0 (0x00000000)
2147 #define CLRADC14IFG2_0_NO_EFFECT (0x00000000)
2148 #define CLRADC14IFG2_1 (0x00000004)
2149 #define CLRADC14IFG30_0 (0x00000000)
2150 #define CLRADC14IFG30_0_NO_EFFECT (0x00000000)
2151 #define CLRADC14IFG30_1 (0x40000000)
2152 #define CLRADC14IFG31_0 (0x00000000)
2153 #define CLRADC14IFG31_0_NO_EFFECT (0x00000000)
2154 #define CLRADC14IFG31_1 (0x80000000)
2155 #define CLRADC14IFG3_0 (0x00000000)
2156 #define CLRADC14IFG3_0_NO_EFFECT (0x00000000)
2157 #define CLRADC14IFG3_1 (0x00000008)
2158 #define CLRADC14IFG4_0 (0x00000000)
2159 #define CLRADC14IFG4_0_NO_EFFECT (0x00000000)
2160 #define CLRADC14IFG4_1 (0x00000010)
2161 #define CLRADC14IFG5_0 (0x00000000)
2162 #define CLRADC14IFG5_0_NO_EFFECT (0x00000000)
2163 #define CLRADC14IFG5_1 (0x00000020)
2164 #define CLRADC14IFG6_0 (0x00000000)
2165 #define CLRADC14IFG6_0_NO_EFFECT (0x00000000)
2166 #define CLRADC14IFG6_1 (0x00000040)
2167 #define CLRADC14IFG7_0 (0x00000000)
2168 #define CLRADC14IFG7_0_NO_EFFECT (0x00000000)
2169 #define CLRADC14IFG7_1 (0x00000080)
2170 #define CLRADC14IFG8_0 (0x00000000)
2171 #define CLRADC14IFG8_0_NO_EFFECT (0x00000000)
2172 #define CLRADC14IFG8_1 (0x00000100)
2173 #define CLRADC14IFG9_0 (0x00000000)
2174 #define CLRADC14IFG9_0_NO_EFFECT (0x00000000)
2175 #define CLRADC14IFG9_1 (0x00000200)
2176 #define CLRADC14INIFG_0 (0x00000000)
2177 #define CLRADC14INIFG_0_NO_EFFECT (0x00000000)
2178 #define CLRADC14INIFG_1 (0x00000002)
2179 #define CLRADC14LOIFG_0 (0x00000000)
2180 #define CLRADC14LOIFG_0_NO_EFFECT (0x00000000)
2181 #define CLRADC14LOIFG_1 (0x00000004)
2182 #define CLRADC14OVIFG_0 (0x00000000)
2183 #define CLRADC14OVIFG_0_NO_EFFECT (0x00000000)
2184 #define CLRADC14OVIFG_1 (0x00000010)
2185 #define CLRADC14RDYIFG_0 (0x00000000)
2186 #define CLRADC14RDYIFG_0_NO_EFFECT (0x00000000)
2187 #define CLRADC14RDYIFG_1 (0x00000040)
2188 #define CLRADC14TOVIFG_0 (0x00000000)
2189 #define CLRADC14TOVIFG_0_NO_EFFECT (0x00000000)
2190 #define CLRADC14TOVIFG_1 (0x00000020)
2191 #define CM0 (0x4000)
2192 #define CM1 (0x8000)
2193 #define COMP_E0_CTL0 (HWREG16(0x40003400))
2194 #define COMP_E0_CTL0_IMEN (0x8000)
2195 #define COMP_E0_CTL0_IMEN__0 (0x0000)
2196 #define COMP_E0_CTL0_IMEN__1 (0x8000)
2197 #define COMP_E0_CTL0_IMSEL__M (0x0f00)
2198 #define COMP_E0_CTL0_IPEN (0x0080)
2199 #define COMP_E0_CTL0_IPEN__0 (0x0000)
2200 #define COMP_E0_CTL0_IPEN__1 (0x0080)
2201 #define COMP_E0_CTL0_IPSEL__M (0x000f)
2202 #define COMP_E0_CTL1 (HWREG16(0x40003402))
2203 #define COMP_E0_CTL1_EX (0x0020)
2204 #define COMP_E0_CTL1_F (0x0004)
2205 #define COMP_E0_CTL1_FDLY__0 (0x0000)
2206 #define COMP_E0_CTL1_FDLY__1 (0x0040)
2207 #define COMP_E0_CTL1_FDLY__2 (0x0080)
2208 #define COMP_E0_CTL1_FDLY__3 (0x00c0)
2209 #define COMP_E0_CTL1_FDLY__M (0x00c0)
2210 #define COMP_E0_CTL1_F__0 (0x0000)
2211 #define COMP_E0_CTL1_F__1 (0x0004)
2212 #define COMP_E0_CTL1_IES (0x0008)
2213 #define COMP_E0_CTL1_IES__0 (0x0000)
2214 #define COMP_E0_CTL1_IES__1 (0x0008)
2215 #define COMP_E0_CTL1_MRVL (0x0800)
2216 #define COMP_E0_CTL1_MRVL__0 (0x0000)
2217 #define COMP_E0_CTL1_MRVL__1 (0x0800)
2218 #define COMP_E0_CTL1_MRVS (0x1000)
2219 #define COMP_E0_CTL1_MRVS__0 (0x0000)
2220 #define COMP_E0_CTL1_MRVS__1 (0x1000)
2221 #define COMP_E0_CTL1_ON (0x0400)
2222 #define COMP_E0_CTL1_ON__0 (0x0000)
2223 #define COMP_E0_CTL1_ON__0_OFF (0x0000)
2224 #define COMP_E0_CTL1_ON__1 (0x0400)
2225 #define COMP_E0_CTL1_ON__1_ON (0x0400)
2226 #define COMP_E0_CTL1_OUT (0x0001)
2227 #define COMP_E0_CTL1_OUTPOL (0x0002)
2228 #define COMP_E0_CTL1_OUTPOL__0 (0x0000)
2229 #define COMP_E0_CTL1_OUTPOL__0_NONINVERTED (0x0000)
2230 #define COMP_E0_CTL1_OUTPOL__1 (0x0002)
2231 #define COMP_E0_CTL1_OUTPOL__1_INVERTED (0x0002)
2232 #define COMP_E0_CTL1_PWRMD__0 (0x0000)
2233 #define COMP_E0_CTL1_PWRMD__0_HIGH_SPEED_MODE (0x0000)
2234 #define COMP_E0_CTL1_PWRMD__1 (0x0100)
2235 #define COMP_E0_CTL1_PWRMD__1_NORMAL_MODE (0x0100)
2236 #define COMP_E0_CTL1_PWRMD__2 (0x0200)
2237 #define COMP_E0_CTL1_PWRMD__M (0x0300)
2238 #define COMP_E0_CTL1_SHORT (0x0010)
2239 #define COMP_E0_CTL1_SHORT__0 (0x0000)
2240 #define COMP_E0_CTL1_SHORT__1 (0x0010)
2241 #define COMP_E0_CTL1_SHORT__1_INPUTS_SHORTED (0x0010)
2242 #define COMP_E0_CTL2 (HWREG16(0x40003404))
2243 #define COMP_E0_CTL2_REF0__M (0x001f)
2244 #define COMP_E0_CTL2_REF1__M (0x1f00)
2245 #define COMP_E0_CTL2_REFACC (0x8000)
2246 #define COMP_E0_CTL2_REFACC__0 (0x0000)
2247 #define COMP_E0_CTL2_REFACC__0_STATIC_MODE (0x0000)
2248 #define COMP_E0_CTL2_REFACC__1 (0x8000)
2249 #define COMP_E0_CTL2_REFL__0 (0x0000)
2250 #define COMP_E0_CTL2_REFL__1 (0x2000)
2251 #define COMP_E0_CTL2_REFL__2 (0x4000)
2252 #define COMP_E0_CTL2_REFL__3 (0x6000)
2253 #define COMP_E0_CTL2_REFL__M (0x6000)
2254 #define COMP_E0_CTL2_RSEL (0x0020)
2255 #define COMP_E0_CTL2_RSEL__0 (0x0000)
2256 #define COMP_E0_CTL2_RSEL__1 (0x0020)
2257 #define COMP_E0_CTL2_RS__0 (0x0000)
2258 #define COMP_E0_CTL2_RS__1 (0x0040)
2259 #define COMP_E0_CTL2_RS__2 (0x0080)
2260 #define COMP_E0_CTL2_RS__3 (0x00c0)
2261 #define COMP_E0_CTL2_RS__M (0x00c0)
2262 #define COMP_E0_CTL3 (HWREG16(0x40003406))
2263 #define COMP_E0_CTL3_PD0 (0x0001)
2264 #define COMP_E0_CTL3_PD0__0 (0x0000)
2265 #define COMP_E0_CTL3_PD0__1 (0x0001)
2266 #define COMP_E0_CTL3_PD1 (0x0002)
2267 #define COMP_E0_CTL3_PD10 (0x0400)
2268 #define COMP_E0_CTL3_PD10__0 (0x0000)
2269 #define COMP_E0_CTL3_PD10__1 (0x0400)
2270 #define COMP_E0_CTL3_PD11 (0x0800)
2271 #define COMP_E0_CTL3_PD11__0 (0x0000)
2272 #define COMP_E0_CTL3_PD11__1 (0x0800)
2273 #define COMP_E0_CTL3_PD12 (0x1000)
2274 #define COMP_E0_CTL3_PD12__0 (0x0000)
2275 #define COMP_E0_CTL3_PD12__1 (0x1000)
2276 #define COMP_E0_CTL3_PD13 (0x2000)
2277 #define COMP_E0_CTL3_PD13__0 (0x0000)
2278 #define COMP_E0_CTL3_PD13__1 (0x2000)
2279 #define COMP_E0_CTL3_PD14 (0x4000)
2280 #define COMP_E0_CTL3_PD14__0 (0x0000)
2281 #define COMP_E0_CTL3_PD14__1 (0x4000)
2282 #define COMP_E0_CTL3_PD15 (0x8000)
2283 #define COMP_E0_CTL3_PD15__0 (0x0000)
2284 #define COMP_E0_CTL3_PD15__1 (0x8000)
2285 #define COMP_E0_CTL3_PD1__0 (0x0000)
2286 #define COMP_E0_CTL3_PD1__1 (0x0002)
2287 #define COMP_E0_CTL3_PD2 (0x0004)
2288 #define COMP_E0_CTL3_PD2__0 (0x0000)
2289 #define COMP_E0_CTL3_PD2__1 (0x0004)
2290 #define COMP_E0_CTL3_PD3 (0x0008)
2291 #define COMP_E0_CTL3_PD3__0 (0x0000)
2292 #define COMP_E0_CTL3_PD3__1 (0x0008)
2293 #define COMP_E0_CTL3_PD4 (0x0010)
2294 #define COMP_E0_CTL3_PD4__0 (0x0000)
2295 #define COMP_E0_CTL3_PD4__1 (0x0010)
2296 #define COMP_E0_CTL3_PD5 (0x0020)
2297 #define COMP_E0_CTL3_PD5__0 (0x0000)
2298 #define COMP_E0_CTL3_PD5__1 (0x0020)
2299 #define COMP_E0_CTL3_PD6 (0x0040)
2300 #define COMP_E0_CTL3_PD6__0 (0x0000)
2301 #define COMP_E0_CTL3_PD6__1 (0x0040)
2302 #define COMP_E0_CTL3_PD7 (0x0080)
2303 #define COMP_E0_CTL3_PD7__0 (0x0000)
2304 #define COMP_E0_CTL3_PD7__1 (0x0080)
2305 #define COMP_E0_CTL3_PD8 (0x0100)
2306 #define COMP_E0_CTL3_PD8__0 (0x0000)
2307 #define COMP_E0_CTL3_PD8__1 (0x0100)
2308 #define COMP_E0_CTL3_PD9 (0x0200)
2309 #define COMP_E0_CTL3_PD9__0 (0x0000)
2310 #define COMP_E0_CTL3_PD9__1 (0x0200)
2311 #define COMP_E0_INT (HWREG16(0x4000340C))
2312 #define COMP_E0_INT_IE (0x0100)
2313 #define COMP_E0_INT_IE__0 (0x0000)
2314 #define COMP_E0_INT_IE__1 (0x0100)
2315 #define COMP_E0_INT_IFG (0x0001)
2316 #define COMP_E0_INT_IFG__0 (0x0000)
2317 #define COMP_E0_INT_IFG__1 (0x0001)
2318 #define COMP_E0_INT_IIE (0x0200)
2319 #define COMP_E0_INT_IIE__0 (0x0000)
2320 #define COMP_E0_INT_IIE__1 (0x0200)
2321 #define COMP_E0_INT_IIFG (0x0002)
2322 #define COMP_E0_INT_IIFG__0 (0x0000)
2323 #define COMP_E0_INT_IIFG__1 (0x0002)
2324 #define COMP_E0_INT_RDYIE (0x1000)
2325 #define COMP_E0_INT_RDYIE__0 (0x0000)
2326 #define COMP_E0_INT_RDYIE__1 (0x1000)
2327 #define COMP_E0_INT_RDYIFG (0x0010)
2328 #define COMP_E0_INT_RDYIFG__0 (0x0000)
2329 #define COMP_E0_INT_RDYIFG__1 (0x0010)
2330 #define COMP_E0_IV (HWREG16(0x4000340E))
2331 #define COMP_E1CTL0 (COMP_E1_CTL0)
2332 #define COMP_E1CTL1 (COMP_E1_CTL1)
2333 #define COMP_E1CTL2 (COMP_E1_CTL2)
2334 #define COMP_E1CTL3 (COMP_E1_CTL3)
2335 #define COMP_E1EX (0x0020)
2336 #define COMP_E1EX_0 (0x0000)
2337 #define COMP_E1EX_0_EXCHANGE_OFF (0x0000)
2338 #define COMP_E1EX_1 (0x0020)
2339 #define COMP_E1EX_1_EXCHANGE_ON (0x0020)
2340 #define COMP_E1F (0x0004)
2341 #define COMP_E1FDLY_0 (0x0000)
2342 #define COMP_E1FDLY_1 (0x0040)
2343 #define COMP_E1FDLY_2 (0x0080)
2344 #define COMP_E1FDLY_3 (0x00c0)
2345 #define COMP_E1FDLY_M (0x00c0)
2346 #define COMP_E1F_0 (0x0000)
2347 #define COMP_E1F_1 (0x0004)
2348 #define COMP_E1IE (0x0100)
2349 #define COMP_E1IES (0x0008)
2350 #define COMP_E1IES_0 (0x0000)
2351 #define COMP_E1IES_1 (0x0008)
2352 #define COMP_E1IE_0 (0x0000)
2353 #define COMP_E1IE_1 (0x0100)
2354 #define COMP_E1IFG (0x0001)
2355 #define COMP_E1IFG_0 (0x0000)
2356 #define COMP_E1IFG_1 (0x0001)
2357 #define COMP_E1IIE (0x0200)
2358 #define COMP_E1IIE_0 (0x0000)
2359 #define COMP_E1IIE_1 (0x0200)
2360 #define COMP_E1IIFG (0x0002)
2361 #define COMP_E1IIFG_0 (0x0000)
2362 #define COMP_E1IIFG_1 (0x0002)
2363 #define COMP_E1IMEN (0x8000)
2364 #define COMP_E1IMEN_0 (0x0000)
2365 #define COMP_E1IMEN_1 (0x8000)
2366 #define COMP_E1IMSEL_M (0x0f00)
2367 #define COMP_E1INT (COMP_E1_INT)
2368 #define COMP_E1IPEN (0x0080)
2369 #define COMP_E1IPEN_0 (0x0000)
2370 #define COMP_E1IPEN_1 (0x0080)
2371 #define COMP_E1IPSEL_M (0x000f)
2372 #define COMP_E1IV (COMP_E1_IV)
2373 #define COMP_E1MRVL (0x0800)
2374 #define COMP_E1MRVL_0 (0x0000)
2375 #define COMP_E1MRVL_1 (0x0800)
2376 #define COMP_E1MRVS (0x1000)
2377 #define COMP_E1MRVS_0 (0x0000)
2378 #define COMP_E1MRVS_1 (0x1000)
2379 #define COMP_E1ON (0x0400)
2380 #define COMP_E1ON_0 (0x0000)
2381 #define COMP_E1ON_0_OFF (0x0000)
2382 #define COMP_E1ON_1 (0x0400)
2383 #define COMP_E1ON_1_ON (0x0400)
2384 #define COMP_E1OUT (0x0001)
2385 #define COMP_E1OUTPOL (0x0002)
2386 #define COMP_E1OUTPOL_0 (0x0000)
2387 #define COMP_E1OUTPOL_0_NONINVERTED (0x0000)
2388 #define COMP_E1OUTPOL_1 (0x0002)
2389 #define COMP_E1OUTPOL_1_INVERTED (0x0002)
2390 #define COMP_E1PD0 (0x0001)
2391 #define COMP_E1PD0_0 (0x0000)
2392 #define COMP_E1PD0_1 (0x0001)
2393 #define COMP_E1PD1 (0x0002)
2394 #define COMP_E1PD10 (0x0400)
2395 #define COMP_E1PD10_0 (0x0000)
2396 #define COMP_E1PD10_1 (0x0400)
2397 #define COMP_E1PD11 (0x0800)
2398 #define COMP_E1PD11_0 (0x0000)
2399 #define COMP_E1PD11_1 (0x0800)
2400 #define COMP_E1PD12 (0x1000)
2401 #define COMP_E1PD12_0 (0x0000)
2402 #define COMP_E1PD12_1 (0x1000)
2403 #define COMP_E1PD13 (0x2000)
2404 #define COMP_E1PD13_0 (0x0000)
2405 #define COMP_E1PD13_1 (0x2000)
2406 #define COMP_E1PD14 (0x4000)
2407 #define COMP_E1PD14_0 (0x0000)
2408 #define COMP_E1PD14_1 (0x4000)
2409 #define COMP_E1PD15 (0x8000)
2410 #define COMP_E1PD15_0 (0x0000)
2411 #define COMP_E1PD15_1 (0x8000)
2412 #define COMP_E1PD1_0 (0x0000)
2413 #define COMP_E1PD1_1 (0x0002)
2414 #define COMP_E1PD2 (0x0004)
2415 #define COMP_E1PD2_0 (0x0000)
2416 #define COMP_E1PD2_1 (0x0004)
2417 #define COMP_E1PD3 (0x0008)
2418 #define COMP_E1PD3_0 (0x0000)
2419 #define COMP_E1PD3_1 (0x0008)
2420 #define COMP_E1PD4 (0x0010)
2421 #define COMP_E1PD4_0 (0x0000)
2422 #define COMP_E1PD4_1 (0x0010)
2423 #define COMP_E1PD5 (0x0020)
2424 #define COMP_E1PD5_0 (0x0000)
2425 #define COMP_E1PD5_1 (0x0020)
2426 #define COMP_E1PD6 (0x0040)
2427 #define COMP_E1PD6_0 (0x0000)
2428 #define COMP_E1PD6_1 (0x0040)
2429 #define COMP_E1PD7 (0x0080)
2430 #define COMP_E1PD7_0 (0x0000)
2431 #define COMP_E1PD7_1 (0x0080)
2432 #define COMP_E1PD8 (0x0100)
2433 #define COMP_E1PD8_0 (0x0000)
2434 #define COMP_E1PD8_1 (0x0100)
2435 #define COMP_E1PD9 (0x0200)
2436 #define COMP_E1PD9_0 (0x0000)
2437 #define COMP_E1PD9_1 (0x0200)
2438 #define COMP_E1PWRMD_0 (0x0000)
2439 #define COMP_E1PWRMD_0_HIGH_SPEED_MODE (0x0000)
2440 #define COMP_E1PWRMD_1 (0x0100)
2441 #define COMP_E1PWRMD_1_NORMAL_MODE (0x0100)
2442 #define COMP_E1PWRMD_2 (0x0200)
2443 #define COMP_E1PWRMD_M (0x0300)
2444 #define COMP_E1RDYIE (0x1000)
2445 #define COMP_E1RDYIE_0 (0x0000)
2446 #define COMP_E1RDYIE_1 (0x1000)
2447 #define COMP_E1RDYIFG (0x0010)
2448 #define COMP_E1RDYIFG_0 (0x0000)
2449 #define COMP_E1RDYIFG_1 (0x0010)
2450 #define COMP_E1REF0_M (0x001f)
2451 #define COMP_E1REF1_M (0x1f00)
2452 #define COMP_E1REFACC (0x8000)
2453 #define COMP_E1REFACC_0 (0x0000)
2454 #define COMP_E1REFACC_0_STATIC_MODE (0x0000)
2455 #define COMP_E1REFACC_1 (0x8000)
2456 #define COMP_E1REFL_0 (0x0000)
2457 #define COMP_E1REFL_1 (0x2000)
2458 #define COMP_E1REFL_2 (0x4000)
2459 #define COMP_E1REFL_3 (0x6000)
2460 #define COMP_E1REFL_M (0x6000)
2461 #define COMP_E1RSEL (0x0020)
2462 #define COMP_E1RSEL_0 (0x0000)
2463 #define COMP_E1RSEL_1 (0x0020)
2464 #define COMP_E1RS_0 (0x0000)
2465 #define COMP_E1RS_1 (0x0040)
2466 #define COMP_E1RS_2 (0x0080)
2467 #define COMP_E1RS_3 (0x00c0)
2468 #define COMP_E1RS_M (0x00c0)
2469 #define COMP_E1SHORT (0x0010)
2470 #define COMP_E1SHORT_0 (0x0000)
2471 #define COMP_E1SHORT_1 (0x0010)
2472 #define COMP_E1SHORT_1_INPUTS_SHORTED (0x0010)
2473 #define COMP_E1_CTL0 (HWREG16(0x40003800))
2474 #define COMP_E1_CTL0_IMEN (0x8000)
2475 #define COMP_E1_CTL0_IMEN__0 (0x0000)
2476 #define COMP_E1_CTL0_IMEN__1 (0x8000)
2477 #define COMP_E1_CTL0_IMSEL__M (0x0f00)
2478 #define COMP_E1_CTL0_IPEN (0x0080)
2479 #define COMP_E1_CTL0_IPEN__0 (0x0000)
2480 #define COMP_E1_CTL0_IPEN__1 (0x0080)
2481 #define COMP_E1_CTL0_IPSEL__M (0x000f)
2482 #define COMP_E1_CTL1 (HWREG16(0x40003802))
2483 #define COMP_E1_CTL1_EX (0x0020)
2484 #define COMP_E1_CTL1_F (0x0004)
2485 #define COMP_E1_CTL1_FDLY__0 (0x0000)
2486 #define COMP_E1_CTL1_FDLY__1 (0x0040)
2487 #define COMP_E1_CTL1_FDLY__2 (0x0080)
2488 #define COMP_E1_CTL1_FDLY__3 (0x00c0)
2489 #define COMP_E1_CTL1_FDLY__M (0x00c0)
2490 #define COMP_E1_CTL1_F__0 (0x0000)
2491 #define COMP_E1_CTL1_F__1 (0x0004)
2492 #define COMP_E1_CTL1_IES (0x0008)
2493 #define COMP_E1_CTL1_IES__0 (0x0000)
2494 #define COMP_E1_CTL1_IES__1 (0x0008)
2495 #define COMP_E1_CTL1_MRVL (0x0800)
2496 #define COMP_E1_CTL1_MRVL__0 (0x0000)
2497 #define COMP_E1_CTL1_MRVL__1 (0x0800)
2498 #define COMP_E1_CTL1_MRVS (0x1000)
2499 #define COMP_E1_CTL1_MRVS__0 (0x0000)
2500 #define COMP_E1_CTL1_MRVS__1 (0x1000)
2501 #define COMP_E1_CTL1_ON (0x0400)
2502 #define COMP_E1_CTL1_ON__0 (0x0000)
2503 #define COMP_E1_CTL1_ON__0_OFF (0x0000)
2504 #define COMP_E1_CTL1_ON__1 (0x0400)
2505 #define COMP_E1_CTL1_ON__1_ON (0x0400)
2506 #define COMP_E1_CTL1_OUT (0x0001)
2507 #define COMP_E1_CTL1_OUTPOL (0x0002)
2508 #define COMP_E1_CTL1_OUTPOL__0 (0x0000)
2509 #define COMP_E1_CTL1_OUTPOL__0_NONINVERTED (0x0000)
2510 #define COMP_E1_CTL1_OUTPOL__1 (0x0002)
2511 #define COMP_E1_CTL1_OUTPOL__1_INVERTED (0x0002)
2512 #define COMP_E1_CTL1_PWRMD__0 (0x0000)
2513 #define COMP_E1_CTL1_PWRMD__0_HIGH_SPEED_MODE (0x0000)
2514 #define COMP_E1_CTL1_PWRMD__1 (0x0100)
2515 #define COMP_E1_CTL1_PWRMD__1_NORMAL_MODE (0x0100)
2516 #define COMP_E1_CTL1_PWRMD__2 (0x0200)
2517 #define COMP_E1_CTL1_PWRMD__M (0x0300)
2518 #define COMP_E1_CTL1_SHORT (0x0010)
2519 #define COMP_E1_CTL1_SHORT__0 (0x0000)
2520 #define COMP_E1_CTL1_SHORT__1 (0x0010)
2521 #define COMP_E1_CTL1_SHORT__1_INPUTS_SHORTED (0x0010)
2522 #define COMP_E1_CTL2 (HWREG16(0x40003804))
2523 #define COMP_E1_CTL2_REF0__M (0x001f)
2524 #define COMP_E1_CTL2_REF1__M (0x1f00)
2525 #define COMP_E1_CTL2_REFACC (0x8000)
2526 #define COMP_E1_CTL2_REFACC__0 (0x0000)
2527 #define COMP_E1_CTL2_REFACC__0_STATIC_MODE (0x0000)
2528 #define COMP_E1_CTL2_REFACC__1 (0x8000)
2529 #define COMP_E1_CTL2_REFL__0 (0x0000)
2530 #define COMP_E1_CTL2_REFL__1 (0x2000)
2531 #define COMP_E1_CTL2_REFL__2 (0x4000)
2532 #define COMP_E1_CTL2_REFL__3 (0x6000)
2533 #define COMP_E1_CTL2_REFL__M (0x6000)
2534 #define COMP_E1_CTL2_RSEL (0x0020)
2535 #define COMP_E1_CTL2_RSEL__0 (0x0000)
2536 #define COMP_E1_CTL2_RSEL__1 (0x0020)
2537 #define COMP_E1_CTL2_RS__0 (0x0000)
2538 #define COMP_E1_CTL2_RS__1 (0x0040)
2539 #define COMP_E1_CTL2_RS__2 (0x0080)
2540 #define COMP_E1_CTL2_RS__3 (0x00c0)
2541 #define COMP_E1_CTL2_RS__M (0x00c0)
2542 #define COMP_E1_CTL3 (HWREG16(0x40003806))
2543 #define COMP_E1_CTL3_PD0 (0x0001)
2544 #define COMP_E1_CTL3_PD0__0 (0x0000)
2545 #define COMP_E1_CTL3_PD0__1 (0x0001)
2546 #define COMP_E1_CTL3_PD1 (0x0002)
2547 #define COMP_E1_CTL3_PD10 (0x0400)
2548 #define COMP_E1_CTL3_PD10__0 (0x0000)
2549 #define COMP_E1_CTL3_PD10__1 (0x0400)
2550 #define COMP_E1_CTL3_PD11 (0x0800)
2551 #define COMP_E1_CTL3_PD11__0 (0x0000)
2552 #define COMP_E1_CTL3_PD11__1 (0x0800)
2553 #define COMP_E1_CTL3_PD12 (0x1000)
2554 #define COMP_E1_CTL3_PD12__0 (0x0000)
2555 #define COMP_E1_CTL3_PD12__1 (0x1000)
2556 #define COMP_E1_CTL3_PD13 (0x2000)
2557 #define COMP_E1_CTL3_PD13__0 (0x0000)
2558 #define COMP_E1_CTL3_PD13__1 (0x2000)
2559 #define COMP_E1_CTL3_PD14 (0x4000)
2560 #define COMP_E1_CTL3_PD14__0 (0x0000)
2561 #define COMP_E1_CTL3_PD14__1 (0x4000)
2562 #define COMP_E1_CTL3_PD15 (0x8000)
2563 #define COMP_E1_CTL3_PD15__0 (0x0000)
2564 #define COMP_E1_CTL3_PD15__1 (0x8000)
2565 #define COMP_E1_CTL3_PD1__0 (0x0000)
2566 #define COMP_E1_CTL3_PD1__1 (0x0002)
2567 #define COMP_E1_CTL3_PD2 (0x0004)
2568 #define COMP_E1_CTL3_PD2__0 (0x0000)
2569 #define COMP_E1_CTL3_PD2__1 (0x0004)
2570 #define COMP_E1_CTL3_PD3 (0x0008)
2571 #define COMP_E1_CTL3_PD3__0 (0x0000)
2572 #define COMP_E1_CTL3_PD3__1 (0x0008)
2573 #define COMP_E1_CTL3_PD4 (0x0010)
2574 #define COMP_E1_CTL3_PD4__0 (0x0000)
2575 #define COMP_E1_CTL3_PD4__1 (0x0010)
2576 #define COMP_E1_CTL3_PD5 (0x0020)
2577 #define COMP_E1_CTL3_PD5__0 (0x0000)
2578 #define COMP_E1_CTL3_PD5__1 (0x0020)
2579 #define COMP_E1_CTL3_PD6 (0x0040)
2580 #define COMP_E1_CTL3_PD6__0 (0x0000)
2581 #define COMP_E1_CTL3_PD6__1 (0x0040)
2582 #define COMP_E1_CTL3_PD7 (0x0080)
2583 #define COMP_E1_CTL3_PD7__0 (0x0000)
2584 #define COMP_E1_CTL3_PD7__1 (0x0080)
2585 #define COMP_E1_CTL3_PD8 (0x0100)
2586 #define COMP_E1_CTL3_PD8__0 (0x0000)
2587 #define COMP_E1_CTL3_PD8__1 (0x0100)
2588 #define COMP_E1_CTL3_PD9 (0x0200)
2589 #define COMP_E1_CTL3_PD9__0 (0x0000)
2590 #define COMP_E1_CTL3_PD9__1 (0x0200)
2591 #define COMP_E1_INT (HWREG16(0x4000380C))
2592 #define COMP_E1_INT_IE (0x0100)
2593 #define COMP_E1_INT_IE__0 (0x0000)
2594 #define COMP_E1_INT_IE__1 (0x0100)
2595 #define COMP_E1_INT_IFG (0x0001)
2596 #define COMP_E1_INT_IFG__0 (0x0000)
2597 #define COMP_E1_INT_IFG__1 (0x0001)
2598 #define COMP_E1_INT_IIE (0x0200)
2599 #define COMP_E1_INT_IIE__0 (0x0000)
2600 #define COMP_E1_INT_IIE__1 (0x0200)
2601 #define COMP_E1_INT_IIFG (0x0002)
2602 #define COMP_E1_INT_IIFG__0 (0x0000)
2603 #define COMP_E1_INT_IIFG__1 (0x0002)
2604 #define COMP_E1_INT_RDYIE (0x1000)
2605 #define COMP_E1_INT_RDYIE__0 (0x0000)
2606 #define COMP_E1_INT_RDYIE__1 (0x1000)
2607 #define COMP_E1_INT_RDYIFG (0x0010)
2608 #define COMP_E1_INT_RDYIFG__0 (0x0000)
2609 #define COMP_E1_INT_RDYIFG__1 (0x0010)
2610 #define COMP_E1_IV (HWREG16(0x4000380E))
2611 #define CRCDI (CRC32DI)
2612 #define CRCDIRB (CRC32DIRB)
2613 #define CRCDIRB_H (HWREG8_H(CRCDIRB))
2614 #define CRCDIRB_L (HWREG8_L(CRCDIRB))
2615 #define CRCDI_H (HWREG8_H(CRCDI))
2616 #define CRCDI_L (HWREG8_L(CRCDI))
2617 #define CRCINIRES (CRC32INIRES_LO)
2618 #define CRCINIRES_H (HWREG8_H(CRC_INIRES))
2619 #define CRCINIRES_L (HWREG8_L(CRC_INIRES))
2620 #define CRCRESR (CRC32RESR_LO)
2621 #define CRCRESR_H (HWREG8_H(CRCRESR))
2622 #define CRCRESR_L (HWREG8_L(CRCRESR))
2623 #define CSKEY (0x0000695A)
2624 #define CS_ACC (HWREG32(0x40010400))
2625 #define CS_ACC_KEY_VAL (0x0000695A)
2626 #define CS_ACC_KEY__M (0x0000ffff)
2627 #define CS_CLKEN (HWREG32(0x40010430))
2628 #define CS_CLKEN_ACLK_EN (0x00000001)
2629 #define CS_CLKEN_ACLK_EN__0 (0x00000000)
2630 #define CS_CLKEN_ACLK_EN__1 (0x00000001)
2631 #define CS_CLKEN_HSMCLK_EN (0x00000004)
2632 #define CS_CLKEN_HSMCLK_EN__0 (0x00000000)
2633 #define CS_CLKEN_HSMCLK_EN__1 (0x00000004)
2634 #define CS_CLKEN_MCLK_EN (0x00000002)
2635 #define CS_CLKEN_MCLK_EN__0 (0x00000000)
2636 #define CS_CLKEN_MCLK_EN__1 (0x00000002)
2637 #define CS_CLKEN_MODOSC_EN (0x00000400)
2638 #define CS_CLKEN_MODOSC_EN__0 (0x00000000)
2639 #define CS_CLKEN_MODOSC_EN__1 (0x00000400)
2640 #define CS_CLKEN_MODOSC_EN__1_MODOSC_IS_ON (0x00000400)
2641 #define CS_CLKEN_REFOFSEL (0x00008000)
2642 #define CS_CLKEN_REFOFSEL__0 (0x00000000)
2643 #define CS_CLKEN_REFOFSEL__0_32_KHZ (0x00000000)
2644 #define CS_CLKEN_REFOFSEL__1 (0x00008000)
2645 #define CS_CLKEN_REFOFSEL__1_128_KHZ (0x00008000)
2646 #define CS_CLKEN_REFO_EN (0x00000200)
2647 #define CS_CLKEN_REFO_EN__0 (0x00000000)
2648 #define CS_CLKEN_REFO_EN__1 (0x00000200)
2649 #define CS_CLKEN_REFO_EN__1_REFO_IS_ON (0x00000200)
2650 #define CS_CLKEN_SMCLK_EN (0x00000008)
2651 #define CS_CLKEN_SMCLK_EN__0 (0x00000000)
2652 #define CS_CLKEN_SMCLK_EN__1 (0x00000008)
2653 #define CS_CLKEN_VLO_EN (0x00000100)
2654 #define CS_CLKEN_VLO_EN__0 (0x00000000)
2655 #define CS_CLKEN_VLO_EN__1 (0x00000100)
2656 #define CS_CLKEN_VLO_EN__1_VLO_IS_ON (0x00000100)
2657 #define CS_CLRIFG (HWREG32(0x40010450))
2658 #define CS_CLRIFG_CLR_CALIFG (0x00000080)
2659 #define CS_CLRIFG_CLR_CALIFG__0 (0x00000000)
2660 #define CS_CLRIFG_CLR_CALIFG__0_NO_EFFECT (0x00000000)
2661 #define CS_CLRIFG_CLR_CALIFG__1 (0x00000080)
2662 #define CS_CLRIFG_CLR_DCOMAXIFG (0x00000020)
2663 #define CS_CLRIFG_CLR_DCOMAXIFG__0 (0x00000000)
2664 #define CS_CLRIFG_CLR_DCOMAXIFG__0_NO_EFFECT (0x00000000)
2665 #define CS_CLRIFG_CLR_DCOMAXIFG__1 (0x00000020)
2666 #define CS_CLRIFG_CLR_DCOMINIFG (0x00000010)
2667 #define CS_CLRIFG_CLR_DCOMINIFG__0 (0x00000000)
2668 #define CS_CLRIFG_CLR_DCOMINIFG__0_NO_EFFECT (0x00000000)
2669 #define CS_CLRIFG_CLR_DCOMINIFG__1 (0x00000010)
2670 #define CS_CLRIFG_CLR_DCORIFG (0x00000040)
2671 #define CS_CLRIFG_CLR_DCORIFG__0 (0x00000000)
2672 #define CS_CLRIFG_CLR_DCORIFG__0_NO_EFFECT (0x00000000)
2673 #define CS_CLRIFG_CLR_DCORIFG__1 (0x00000040)
2674 #define CS_CLRIFG_CLR_FCNTHF2IFG (0x00000400)
2675 #define CS_CLRIFG_CLR_FCNTHF2IFG__0 (0x00000000)
2676 #define CS_CLRIFG_CLR_FCNTHF2IFG__0_NO_EFFECT (0x00000000)
2677 #define CS_CLRIFG_CLR_FCNTHF2IFG__1 (0x00000400)
2678 #define CS_CLRIFG_CLR_FCNTHFIFG (0x00000200)
2679 #define CS_CLRIFG_CLR_FCNTHFIFG__0 (0x00000000)
2680 #define CS_CLRIFG_CLR_FCNTHFIFG__0_NO_EFFECT (0x00000000)
2681 #define CS_CLRIFG_CLR_FCNTHFIFG__1 (0x00000200)
2682 #define CS_CLRIFG_CLR_FCNTLFIFG (0x00000100)
2683 #define CS_CLRIFG_CLR_FCNTLFIFG__0 (0x00000000)
2684 #define CS_CLRIFG_CLR_FCNTLFIFG__0_NO_EFFECT (0x00000000)
2685 #define CS_CLRIFG_CLR_FCNTLFIFG__1 (0x00000100)
2686 #define CS_CLRIFG_CLR_HFXT2IFG (0x00000004)
2687 #define CS_CLRIFG_CLR_HFXT2IFG__0 (0x00000000)
2688 #define CS_CLRIFG_CLR_HFXT2IFG__0_NO_EFFECT (0x00000000)
2689 #define CS_CLRIFG_CLR_HFXT2IFG__1 (0x00000004)
2690 #define CS_CLRIFG_CLR_HFXTIFG (0x00000002)
2691 #define CS_CLRIFG_CLR_HFXTIFG__0 (0x00000000)
2692 #define CS_CLRIFG_CLR_HFXTIFG__0_NO_EFFECT (0x00000000)
2693 #define CS_CLRIFG_CLR_HFXTIFG__1 (0x00000002)
2694 #define CS_CLRIFG_CLR_LFXTIFG (0x00000001)
2695 #define CS_CLRIFG_CLR_LFXTIFG__0 (0x00000000)
2696 #define CS_CLRIFG_CLR_LFXTIFG__0_NO_EFFECT (0x00000000)
2697 #define CS_CLRIFG_CLR_LFXTIFG__1 (0x00000001)
2698 #define CS_CLRIFG_CLR_PLLLOSIFG (0x00002000)
2699 #define CS_CLRIFG_CLR_PLLLOSIFG__0 (0x00000000)
2700 #define CS_CLRIFG_CLR_PLLLOSIFG__0_NO_EFFECT (0x00000000)
2701 #define CS_CLRIFG_CLR_PLLLOSIFG__1 (0x00002000)
2702 #define CS_CLRIFG_CLR_PLLOOLIFG (0x00001000)
2703 #define CS_CLRIFG_CLR_PLLOOLIFG__0 (0x00000000)
2704 #define CS_CLRIFG_CLR_PLLOOLIFG__0_NO_EFFECT (0x00000000)
2705 #define CS_CLRIFG_CLR_PLLOOLIFG__1 (0x00001000)
2706 #define CS_CLRIFG_CLR_PLLOORIFG (0x00004000)
2707 #define CS_CLRIFG_CLR_PLLOORIFG__0 (0x00000000)
2708 #define CS_CLRIFG_CLR_PLLOORIFG__0_NO_EFFECT (0x00000000)
2709 #define CS_CLRIFG_CLR_PLLOORIFG__1 (0x00004000)
2710 #define CS_CTL0 (HWREG32(0x40010404))
2711 #define CS_CTL0_DCOEN (0x00800000)
2712 #define CS_CTL0_DCOEN__0 (0x00000000)
2713 #define CS_CTL0_DCOEN__1 (0x00800000)
2714 #define CS_CTL0_DCOEN__1_DCO_IS_ON (0x00800000)
2715 #define CS_CTL0_DCORES (0x00400000)
2716 #define CS_CTL0_DCORES__0 (0x00000000)
2717 #define CS_CTL0_DCORES__1 (0x00400000)
2718 #define CS_CTL0_DCORSEL__0 (0x00000000)
2719 #define CS_CTL0_DCORSEL__1 (0x00010000)
2720 #define CS_CTL0_DCORSEL__2 (0x00020000)
2721 #define CS_CTL0_DCORSEL__3 (0x00030000)
2722 #define CS_CTL0_DCORSEL__4 (0x00040000)
2723 #define CS_CTL0_DCORSEL__5 (0x00050000)
2724 #define CS_CTL0_DCORSEL__M (0x00070000)
2725 #define CS_CTL0_DCOTUNE__M (0x00001fff)
2726 #define CS_CTL0_DIS_DCO_DELAY_CNT (0x01000000)
2727 #define CS_CTL1 (HWREG32(0x40010408))
2728 #define CS_CTL1_DIVA__0 (0x00000000)
2729 #define CS_CTL1_DIVA__0_F_ACLK__1 (0x00000000)
2730 #define CS_CTL1_DIVA__1 (0x01000000)
2731 #define CS_CTL1_DIVA__1_F_ACLK__2 (0x01000000)
2732 #define CS_CTL1_DIVA__2 (0x02000000)
2733 #define CS_CTL1_DIVA__2_F_ACLK__4 (0x02000000)
2734 #define CS_CTL1_DIVA__3 (0x03000000)
2735 #define CS_CTL1_DIVA__3_F_ACLK__8 (0x03000000)
2736 #define CS_CTL1_DIVA__4 (0x04000000)
2737 #define CS_CTL1_DIVA__4_F_ACLK__16 (0x04000000)
2738 #define CS_CTL1_DIVA__5 (0x05000000)
2739 #define CS_CTL1_DIVA__5_F_ACLK__32 (0x05000000)
2740 #define CS_CTL1_DIVA__6 (0x06000000)
2741 #define CS_CTL1_DIVA__6_F_ACLK__64 (0x06000000)
2742 #define CS_CTL1_DIVA__7 (0x07000000)
2743 #define CS_CTL1_DIVA__7_F_ACLK__128 (0x07000000)
2744 #define CS_CTL1_DIVA__M (0x07000000)
2745 #define CS_CTL1_DIVHS__0 (0x00000000)
2746 #define CS_CTL1_DIVHS__0_F_HSMCLK__1 (0x00000000)
2747 #define CS_CTL1_DIVHS__1 (0x00100000)
2748 #define CS_CTL1_DIVHS__1_F_HSMCLK__2 (0x00100000)
2749 #define CS_CTL1_DIVHS__2 (0x00200000)
2750 #define CS_CTL1_DIVHS__2_F_HSMCLK__4 (0x00200000)
2751 #define CS_CTL1_DIVHS__3 (0x00300000)
2752 #define CS_CTL1_DIVHS__3_F_HSMCLK__8 (0x00300000)
2753 #define CS_CTL1_DIVHS__4 (0x00400000)
2754 #define CS_CTL1_DIVHS__4_F_HSMCLK__16 (0x00400000)
2755 #define CS_CTL1_DIVHS__5 (0x00500000)
2756 #define CS_CTL1_DIVHS__5_F_HSMCLK__32 (0x00500000)
2757 #define CS_CTL1_DIVHS__6 (0x00600000)
2758 #define CS_CTL1_DIVHS__6_F_HSMCLK__64 (0x00600000)
2759 #define CS_CTL1_DIVHS__7 (0x00700000)
2760 #define CS_CTL1_DIVHS__7_F_HSMCLK__128 (0x00700000)
2761 #define CS_CTL1_DIVHS__M (0x00700000)
2762 #define CS_CTL1_DIVM__0 (0x00000000)
2763 #define CS_CTL1_DIVM__0_F_MCLK__1 (0x00000000)
2764 #define CS_CTL1_DIVM__1 (0x00010000)
2765 #define CS_CTL1_DIVM__1_F_MCLK__2 (0x00010000)
2766 #define CS_CTL1_DIVM__2 (0x00020000)
2767 #define CS_CTL1_DIVM__2_F_MCLK__4 (0x00020000)
2768 #define CS_CTL1_DIVM__3 (0x00030000)
2769 #define CS_CTL1_DIVM__3_F_MCLK__8 (0x00030000)
2770 #define CS_CTL1_DIVM__4 (0x00040000)
2771 #define CS_CTL1_DIVM__4_F_MCLK__16 (0x00040000)
2772 #define CS_CTL1_DIVM__5 (0x00050000)
2773 #define CS_CTL1_DIVM__5_F_MCLK__32 (0x00050000)
2774 #define CS_CTL1_DIVM__6 (0x00060000)
2775 #define CS_CTL1_DIVM__6_F_MCLK__64 (0x00060000)
2776 #define CS_CTL1_DIVM__7 (0x00070000)
2777 #define CS_CTL1_DIVM__7_F_MCLK__128 (0x00070000)
2778 #define CS_CTL1_DIVM__M (0x00070000)
2779 #define CS_CTL1_DIVS__0 (0x00000000)
2780 #define CS_CTL1_DIVS__0_F_SMCLK__1 (0x00000000)
2781 #define CS_CTL1_DIVS__1 (0x10000000)
2782 #define CS_CTL1_DIVS__1_F_SMCLK__2 (0x10000000)
2783 #define CS_CTL1_DIVS__2 (0x20000000)
2784 #define CS_CTL1_DIVS__2_F_SMCLK__4 (0x20000000)
2785 #define CS_CTL1_DIVS__3 (0x30000000)
2786 #define CS_CTL1_DIVS__3_F_SMCLK__8 (0x30000000)
2787 #define CS_CTL1_DIVS__4 (0x40000000)
2788 #define CS_CTL1_DIVS__4_F_SMCLK__16 (0x40000000)
2789 #define CS_CTL1_DIVS__5 (0x50000000)
2790 #define CS_CTL1_DIVS__5_F_SMCLK__32 (0x50000000)
2791 #define CS_CTL1_DIVS__6 (0x60000000)
2792 #define CS_CTL1_DIVS__6_F_SMCLK__64 (0x60000000)
2793 #define CS_CTL1_DIVS__7 (0x70000000)
2794 #define CS_CTL1_DIVS__7_F_SMCLK__128 (0x70000000)
2795 #define CS_CTL1_DIVS__M (0x70000000)
2796 #define CS_CTL1_SELA__0 (0x00000000)
2797 #define CS_CTL1_SELA__1 (0x00000100)
2798 #define CS_CTL1_SELA__1_VLOCLK (0x00000100)
2799 #define CS_CTL1_SELA__2 (0x00000200)
2800 #define CS_CTL1_SELA__2_REFOCLK (0x00000200)
2801 #define CS_CTL1_SELA__M (0x00000700)
2802 #define CS_CTL1_SELB (0x00001000)
2803 #define CS_CTL1_SELB__0 (0x00000000)
2804 #define CS_CTL1_SELB__0_LFXTCLK (0x00000000)
2805 #define CS_CTL1_SELB__1 (0x00001000)
2806 #define CS_CTL1_SELB__1_REFOCLK (0x00001000)
2807 #define CS_CTL1_SELM__0 (0x00000000)
2808 #define CS_CTL1_SELM__1 (0x00000001)
2809 #define CS_CTL1_SELM__1_VLOCLK (0x00000001)
2810 #define CS_CTL1_SELM__2 (0x00000002)
2811 #define CS_CTL1_SELM__2_REFOCLK (0x00000002)
2812 #define CS_CTL1_SELM__3 (0x00000003)
2813 #define CS_CTL1_SELM__3_DCOCLK (0x00000003)
2814 #define CS_CTL1_SELM__4 (0x00000004)
2815 #define CS_CTL1_SELM__4_MODOSC (0x00000004)
2816 #define CS_CTL1_SELM__5 (0x00000005)
2817 #define CS_CTL1_SELM__6 (0x00000006)
2818 #define CS_CTL1_SELM__7 (0x00000007)
2819 #define CS_CTL1_SELM__M (0x00000007)
2820 #define CS_CTL1_SELS__0 (0x00000000)
2821 #define CS_CTL1_SELS__1 (0x00000010)
2822 #define CS_CTL1_SELS__1_VLOCLK (0x00000010)
2823 #define CS_CTL1_SELS__2 (0x00000020)
2824 #define CS_CTL1_SELS__2_REFOCLK (0x00000020)
2825 #define CS_CTL1_SELS__3 (0x00000030)
2826 #define CS_CTL1_SELS__3_DCOCLK (0x00000030)
2827 #define CS_CTL1_SELS__4 (0x00000040)
2828 #define CS_CTL1_SELS__4_MODOSC (0x00000040)
2829 #define CS_CTL1_SELS__5 (0x00000050)
2830 #define CS_CTL1_SELS__6 (0x00000060)
2831 #define CS_CTL1_SELS__7 (0x00000070)
2832 #define CS_CTL1_SELS__M (0x00000070)
2833 #define CS_CTL2 (HWREG32(0x4001040C))
2834 #define CS_CTL2_HFXTBYPASS (0x02000000)
2835 #define CS_CTL2_HFXTBYPASS__0 (0x00000000)
2836 #define CS_CTL2_HFXTBYPASS__1 (0x02000000)
2837 #define CS_CTL2_HFXTDRIVE (0x00010000)
2838 #define CS_CTL2_HFXTFREQ__0 (0x00000000)
2839 #define CS_CTL2_HFXTFREQ__0_1_MHZ_TO_4_MHZ (0x00000000)
2840 #define CS_CTL2_HFXTFREQ__1 (0x00100000)
2841 #define CS_CTL2_HFXTFREQ__1__4_MHZ_TO_8_MHZ (0x00100000)
2842 #define CS_CTL2_HFXTFREQ__2 (0x00200000)
2843 #define CS_CTL2_HFXTFREQ__2_8_MHZ_TO_16_MHZ (0x00200000)
2844 #define CS_CTL2_HFXTFREQ__3 (0x00300000)
2845 #define CS_CTL2_HFXTFREQ__4 (0x00400000)
2846 #define CS_CTL2_HFXTFREQ__5 (0x00500000)
2847 #define CS_CTL2_HFXTFREQ__6 (0x00600000)
2848 #define CS_CTL2_HFXTFREQ__7 (0x00700000)
2849 #define CS_CTL2_HFXTFREQ__M (0x00700000)
2850 #define CS_CTL2_HFXT_EN (0x01000000)
2851 #define CS_CTL2_HFXT_EN__0 (0x00000000)
2852 #define CS_CTL2_HFXT_EN__1 (0x01000000)
2853 #define CS_CTL2_LFXTAGCOFF (0x00000080)
2854 #define CS_CTL2_LFXTAGCOFF__0 (0x00000000)
2855 #define CS_CTL2_LFXTAGCOFF__0_AGC_ENABLED (0x00000000)
2856 #define CS_CTL2_LFXTAGCOFF__1 (0x00000080)
2857 #define CS_CTL2_LFXTAGCOFF__1_AGC_DISABLED (0x00000080)
2858 #define CS_CTL2_LFXTBYPASS (0x00000200)
2859 #define CS_CTL2_LFXTBYPASS__0 (0x00000000)
2860 #define CS_CTL2_LFXTBYPASS__1 (0x00000200)
2861 #define CS_CTL2_LFXTDRIVE__0 (0x00000000)
2862 #define CS_CTL2_LFXTDRIVE__1 (0x00000001)
2863 #define CS_CTL2_LFXTDRIVE__2 (0x00000002)
2864 #define CS_CTL2_LFXTDRIVE__3 (0x00000003)
2865 #define CS_CTL2_LFXTDRIVE__4 (0x00000004)
2866 #define CS_CTL2_LFXTDRIVE__5 (0x00000005)
2867 #define CS_CTL2_LFXTDRIVE__6 (0x00000006)
2868 #define CS_CTL2_LFXTDRIVE__7 (0x00000007)
2869 #define CS_CTL2_LFXTDRIVE__M (0x00000007)
2870 #define CS_CTL2_LFXT_EN (0x00000100)
2871 #define CS_CTL2_LFXT_EN__0 (0x00000000)
2872 #define CS_CTL2_LFXT_EN__1 (0x00000100)
2873 #define CS_CTL3 (HWREG32(0x40010410))
2874 #define CS_CTL3_FCNTHF2_EN (0x00000800)
2875 #define CS_CTL3_FCNTHF2_EN__0 (0x00000000)
2876 #define CS_CTL3_FCNTHF2_EN__1 (0x00000800)
2877 #define CS_CTL3_FCNTHF2__0 (0x00000000)
2878 #define CS_CTL3_FCNTHF2__0_2048_CYCLES (0x00000000)
2879 #define CS_CTL3_FCNTHF2__1 (0x00000100)
2880 #define CS_CTL3_FCNTHF2__1_4096_CYCLES (0x00000100)
2881 #define CS_CTL3_FCNTHF2__2 (0x00000200)
2882 #define CS_CTL3_FCNTHF2__2_8192_CYCLES (0x00000200)
2883 #define CS_CTL3_FCNTHF2__3 (0x00000300)
2884 #define CS_CTL3_FCNTHF2__3_16384_CYCLES (0x00000300)
2885 #define CS_CTL3_FCNTHF2__M (0x00000300)
2886 #define CS_CTL3_FCNTHF_EN (0x00000080)
2887 #define CS_CTL3_FCNTHF_EN__0 (0x00000000)
2888 #define CS_CTL3_FCNTHF_EN__1 (0x00000080)
2889 #define CS_CTL3_FCNTHF__0 (0x00000000)
2890 #define CS_CTL3_FCNTHF__0_2048_CYCLES (0x00000000)
2891 #define CS_CTL3_FCNTHF__1 (0x00000010)
2892 #define CS_CTL3_FCNTHF__1_4096_CYCLES (0x00000010)
2893 #define CS_CTL3_FCNTHF__2 (0x00000020)
2894 #define CS_CTL3_FCNTHF__2_8192_CYCLES (0x00000020)
2895 #define CS_CTL3_FCNTHF__3 (0x00000030)
2896 #define CS_CTL3_FCNTHF__3_16384_CYCLES (0x00000030)
2897 #define CS_CTL3_FCNTHF__M (0x00000030)
2898 #define CS_CTL3_FCNTLF_EN (0x00000008)
2899 #define CS_CTL3_FCNTLF_EN__0 (0x00000000)
2900 #define CS_CTL3_FCNTLF_EN__1 (0x00000008)
2901 #define CS_CTL3_FCNTLF__0 (0x00000000)
2902 #define CS_CTL3_FCNTLF__0_4096_CYCLES (0x00000000)
2903 #define CS_CTL3_FCNTLF__1 (0x00000001)
2904 #define CS_CTL3_FCNTLF__1_8192_CYCLES (0x00000001)
2905 #define CS_CTL3_FCNTLF__2 (0x00000002)
2906 #define CS_CTL3_FCNTLF__2_16384_CYCLES (0x00000002)
2907 #define CS_CTL3_FCNTLF__3 (0x00000003)
2908 #define CS_CTL3_FCNTLF__3_32768_CYCLES (0x00000003)
2909 #define CS_CTL3_FCNTLF__M (0x00000003)
2910 #define CS_CTL3_RFCNTHF (0x00000040)
2911 #define CS_CTL3_RFCNTHF2 (0x00000400)
2912 #define CS_CTL3_RFCNTHF2__0 (0x00000000)
2913 #define CS_CTL3_RFCNTHF2__1 (0x00000400)
2914 #define CS_CTL3_RFCNTHF__0 (0x00000000)
2915 #define CS_CTL3_RFCNTHF__1 (0x00000040)
2916 #define CS_CTL3_RFCNTLF (0x00000004)
2917 #define CS_CTL3_RFCNTLF__0 (0x00000000)
2918 #define CS_CTL3_RFCNTLF__1 (0x00000004)
2919 #define CS_CTL4 (HWREG32(0x40010414))
2920 #define CS_CTL4_HFXT2BYPASS (0x00000200)
2921 #define CS_CTL4_HFXT2BYPASS__0 (0x00000000)
2922 #define CS_CTL4_HFXT2BYPASS__1 (0x00000200)
2923 #define CS_CTL4_HFXT2DRIVE (0x00000001)
2924 #define CS_CTL4_HFXT2FREQ__0 (0x00000000)
2925 #define CS_CTL4_HFXT2FREQ__0_1_MHZ_TO_4_MHZ (0x00000000)
2926 #define CS_CTL4_HFXT2FREQ__1 (0x00000010)
2927 #define CS_CTL4_HFXT2FREQ__1__4_MHZ_TO_8_MHZ (0x00000010)
2928 #define CS_CTL4_HFXT2FREQ__2 (0x00000020)
2929 #define CS_CTL4_HFXT2FREQ__3 (0x00000030)
2930 #define CS_CTL4_HFXT2FREQ__4 (0x00000040)
2931 #define CS_CTL4_HFXT2FREQ__5 (0x00000050)
2932 #define CS_CTL4_HFXT2FREQ__6 (0x00000060)
2933 #define CS_CTL4_HFXT2FREQ__7 (0x00000070)
2934 #define CS_CTL4_HFXT2FREQ__M (0x00000070)
2935 #define CS_CTL4_HFXT2_EN (0x00000100)
2936 #define CS_CTL4_HFXT2_EN__0 (0x00000000)
2937 #define CS_CTL4_HFXT2_EN__1 (0x00000100)
2938 #define CS_CTL5 (HWREG32(0x40010418))
2939 #define CS_CTL5_CALSTART (0x00000080)
2940 #define CS_CTL5_CALSTART__0 (0x00000000)
2941 #define CS_CTL5_CALSTART__1 (0x00000080)
2942 #define CS_CTL5_PERCNTSEL__0 (0x00000000)
2943 #define CS_CTL5_PERCNTSEL__0_DCOCLK (0x00000000)
2944 #define CS_CTL5_PERCNTSEL__1 (0x00000100)
2945 #define CS_CTL5_PERCNTSEL__1_REFOCLK (0x00000100)
2946 #define CS_CTL5_PERCNTSEL__M (0x00000700)
2947 #define CS_CTL5_REFCNTPS__0 (0x00000000)
2948 #define CS_CTL5_REFCNTPS__0__1 (0x00000000)
2949 #define CS_CTL5_REFCNTPS__1 (0x00000008)
2950 #define CS_CTL5_REFCNTPS__1__16 (0x00000008)
2951 #define CS_CTL5_REFCNTPS__2 (0x00000010)
2952 #define CS_CTL5_REFCNTPS__2__32 (0x00000010)
2953 #define CS_CTL5_REFCNTPS__3 (0x00000018)
2954 #define CS_CTL5_REFCNTPS__3__64 (0x00000018)
2955 #define CS_CTL5_REFCNTPS__4 (0x00000020)
2956 #define CS_CTL5_REFCNTPS__4__128 (0x00000020)
2957 #define CS_CTL5_REFCNTPS__5 (0x00000028)
2958 #define CS_CTL5_REFCNTPS__5__256 (0x00000028)
2959 #define CS_CTL5_REFCNTPS__6 (0x00000030)
2960 #define CS_CTL5_REFCNTPS__6__512 (0x00000030)
2961 #define CS_CTL5_REFCNTPS__7 (0x00000038)
2962 #define CS_CTL5_REFCNTPS__7__1024 (0x00000038)
2963 #define CS_CTL5_REFCNTPS__M (0x00000038)
2964 #define CS_CTL5_REFCNTSEL__0 (0x00000000)
2965 #define CS_CTL5_REFCNTSEL__0_REFOCLK (0x00000000)
2966 #define CS_CTL5_REFCNTSEL__1 (0x00000001)
2967 #define CS_CTL5_REFCNTSEL__2 (0x00000002)
2968 #define CS_CTL5_REFCNTSEL__3 (0x00000003)
2969 #define CS_CTL5_REFCNTSEL__M (0x00000007)
2970 #define CS_CTL6 (HWREG32(0x4001041C))
2971 #define CS_CTL6_PERCNT__M (0x0000ffff)
2972 #define CS_CTL7 (HWREG32(0x40010420))
2973 #define CS_CTL7_REFCNT__M (0x0000ffff)
2974 #define CS_DCOERCAL (HWREG32(0x40010460))
2975 #define CS_DCOERCAL_DCO_FTRIM__M (0x07ff0000)
2976 #define CS_DCOERCAL_DCO_TCTRIM__M (0x00000003)
2977 #define CS_IE (HWREG32(0x40010440))
2978 #define CS_IE_CALIE (0x00008000)
2979 #define CS_IE_CALIE__0 (0x00000000)
2980 #define CS_IE_CALIE__1 (0x00008000)
2981 #define CS_IE_DCOMAXIE (0x00000020)
2982 #define CS_IE_DCOMAXIE__0 (0x00000000)
2983 #define CS_IE_DCOMAXIE__1 (0x00000020)
2984 #define CS_IE_DCOMINIE (0x00000010)
2985 #define CS_IE_DCOMINIE__0 (0x00000000)
2986 #define CS_IE_DCOMINIE__1 (0x00000010)
2987 #define CS_IE_DCORIE (0x00000040)
2988 #define CS_IE_DCORIE__0 (0x00000000)
2989 #define CS_IE_DCORIE__1 (0x00000040)
2990 #define CS_IE_FCNTHF2IE (0x00000400)
2991 #define CS_IE_FCNTHF2IE__0 (0x00000000)
2992 #define CS_IE_FCNTHF2IE__1 (0x00000400)
2993 #define CS_IE_FCNTHFIE (0x00000200)
2994 #define CS_IE_FCNTHFIE__0 (0x00000000)
2995 #define CS_IE_FCNTHFIE__1 (0x00000200)
2996 #define CS_IE_FCNTLFIE (0x00000100)
2997 #define CS_IE_FCNTLFIE__0 (0x00000000)
2998 #define CS_IE_FCNTLFIE__1 (0x00000100)
2999 #define CS_IE_HFXT2IE (0x00000004)
3000 #define CS_IE_HFXT2IE__0 (0x00000000)
3001 #define CS_IE_HFXT2IE__1 (0x00000004)
3002 #define CS_IE_HFXTIE (0x00000002)
3003 #define CS_IE_HFXTIE__0 (0x00000000)
3004 #define CS_IE_HFXTIE__1 (0x00000002)
3005 #define CS_IE_LFXTIE (0x00000001)
3006 #define CS_IE_LFXTIE__0 (0x00000000)
3007 #define CS_IE_LFXTIE__1 (0x00000001)
3008 #define CS_IE_PLLLOSIE (0x00002000)
3009 #define CS_IE_PLLLOSIE__0 (0x00000000)
3010 #define CS_IE_PLLLOSIE__1 (0x00002000)
3011 #define CS_IE_PLLOOLIE (0x00001000)
3012 #define CS_IE_PLLOOLIE__0 (0x00000000)
3013 #define CS_IE_PLLOOLIE__1 (0x00001000)
3014 #define CS_IE_PLLOORIE (0x00004000)
3015 #define CS_IE_PLLOORIE__0 (0x00000000)
3016 #define CS_IE_PLLOORIE__1 (0x00004000)
3017 #define CS_IFG (HWREG32(0x40010448))
3018 #define CS_IFG_CALIFG (0x00008000)
3019 #define CS_IFG_CALIFG__0 (0x00000000)
3020 #define CS_IFG_CALIFG__1 (0x00008000)
3021 #define CS_IFG_DCOMAXIFG (0x00000020)
3022 #define CS_IFG_DCOMAXIFG__0 (0x00000000)
3023 #define CS_IFG_DCOMAXIFG__1 (0x00000020)
3024 #define CS_IFG_DCOMINIFG (0x00000010)
3025 #define CS_IFG_DCOMINIFG__0 (0x00000000)
3026 #define CS_IFG_DCOMINIFG__1 (0x00000010)
3027 #define CS_IFG_DCORIFG (0x00000040)
3028 #define CS_IFG_DCORIFG__0 (0x00000000)
3029 #define CS_IFG_DCORIFG__1 (0x00000040)
3030 #define CS_IFG_FCNTHF2IFG (0x00000800)
3031 #define CS_IFG_FCNTHF2IFG__0 (0x00000000)
3032 #define CS_IFG_FCNTHF2IFG__1 (0x00000800)
3033 #define CS_IFG_FCNTHFIFG (0x00000200)
3034 #define CS_IFG_FCNTHFIFG__0 (0x00000000)
3035 #define CS_IFG_FCNTHFIFG__1 (0x00000200)
3036 #define CS_IFG_FCNTLFIFG (0x00000100)
3037 #define CS_IFG_FCNTLFIFG__0 (0x00000000)
3038 #define CS_IFG_FCNTLFIFG__1 (0x00000100)
3039 #define CS_IFG_HFXT2IFG (0x00000004)
3040 #define CS_IFG_HFXT2IFG__0 (0x00000000)
3041 #define CS_IFG_HFXT2IFG__1 (0x00000004)
3042 #define CS_IFG_HFXTIFG (0x00000002)
3043 #define CS_IFG_HFXTIFG__0 (0x00000000)
3044 #define CS_IFG_HFXTIFG__1 (0x00000002)
3045 #define CS_IFG_LFXTIFG (0x00000001)
3046 #define CS_IFG_LFXTIFG__0 (0x00000000)
3047 #define CS_IFG_LFXTIFG__1 (0x00000001)
3048 #define CS_IFG_PLLLOSIFG (0x00002000)
3049 #define CS_IFG_PLLLOSIFG__0 (0x00000000)
3050 #define CS_IFG_PLLLOSIFG__1 (0x00002000)
3051 #define CS_IFG_PLLOOLIFG (0x00001000)
3052 #define CS_IFG_PLLOOLIFG__0 (0x00000000)
3053 #define CS_IFG_PLLOOLIFG__1 (0x00001000)
3054 #define CS_IFG_PLLOORIFG (0x00004000)
3055 #define CS_IFG_PLLOORIFG__0 (0x00000000)
3056 #define CS_IFG_PLLOORIFG__1 (0x00004000)
3057 #define CS_SETIFG (HWREG32(0x40010458))
3058 #define CS_SETIFG_SET_CALIFG (0x00000080)
3059 #define CS_SETIFG_SET_CALIFG__0 (0x00000000)
3060 #define CS_SETIFG_SET_CALIFG__0_NO_EFFECT (0x00000000)
3061 #define CS_SETIFG_SET_CALIFG__1 (0x00000080)
3062 #define CS_SETIFG_SET_DCOMAXIFG (0x00000020)
3063 #define CS_SETIFG_SET_DCOMAXIFG__0 (0x00000000)
3064 #define CS_SETIFG_SET_DCOMAXIFG__0_NO_EFFECT (0x00000000)
3065 #define CS_SETIFG_SET_DCOMAXIFG__1 (0x00000020)
3066 #define CS_SETIFG_SET_DCOMINIFG (0x00000010)
3067 #define CS_SETIFG_SET_DCOMINIFG__0 (0x00000000)
3068 #define CS_SETIFG_SET_DCOMINIFG__0_NO_EFFECT (0x00000000)
3069 #define CS_SETIFG_SET_DCOMINIFG__1 (0x00000010)
3070 #define CS_SETIFG_SET_DCORIFG (0x00000040)
3071 #define CS_SETIFG_SET_DCORIFG__0 (0x00000000)
3072 #define CS_SETIFG_SET_DCORIFG__0_NO_EFFECT (0x00000000)
3073 #define CS_SETIFG_SET_DCORIFG__1 (0x00000040)
3074 #define CS_SETIFG_SET_FCNTHF2IFG (0x00000400)
3075 #define CS_SETIFG_SET_FCNTHF2IFG__0 (0x00000000)
3076 #define CS_SETIFG_SET_FCNTHF2IFG__0_NO_EFFECT (0x00000000)
3077 #define CS_SETIFG_SET_FCNTHF2IFG__1 (0x00000400)
3078 #define CS_SETIFG_SET_FCNTHFIFG (0x00000200)
3079 #define CS_SETIFG_SET_FCNTHFIFG__0 (0x00000000)
3080 #define CS_SETIFG_SET_FCNTHFIFG__0_NO_EFFECT (0x00000000)
3081 #define CS_SETIFG_SET_FCNTHFIFG__1 (0x00000200)
3082 #define CS_SETIFG_SET_FCNTLFIFG (0x00000100)
3083 #define CS_SETIFG_SET_FCNTLFIFG__0 (0x00000000)
3084 #define CS_SETIFG_SET_FCNTLFIFG__0_NO_EFFECT (0x00000000)
3085 #define CS_SETIFG_SET_FCNTLFIFG__1 (0x00000100)
3086 #define CS_SETIFG_SET_HFXT2IFG (0x00000004)
3087 #define CS_SETIFG_SET_HFXT2IFG__0 (0x00000000)
3088 #define CS_SETIFG_SET_HFXT2IFG__0_NO_EFFECT (0x00000000)
3089 #define CS_SETIFG_SET_HFXT2IFG__1 (0x00000004)
3090 #define CS_SETIFG_SET_HFXTIFG (0x00000002)
3091 #define CS_SETIFG_SET_HFXTIFG__0 (0x00000000)
3092 #define CS_SETIFG_SET_HFXTIFG__0_NO_EFFECT (0x00000000)
3093 #define CS_SETIFG_SET_HFXTIFG__1 (0x00000002)
3094 #define CS_SETIFG_SET_LFXTIFG (0x00000001)
3095 #define CS_SETIFG_SET_LFXTIFG__0 (0x00000000)
3096 #define CS_SETIFG_SET_LFXTIFG__0_NO_EFFECT (0x00000000)
3097 #define CS_SETIFG_SET_LFXTIFG__1 (0x00000001)
3098 #define CS_SETIFG_SET_PLLLOSIFG (0x00002000)
3099 #define CS_SETIFG_SET_PLLLOSIFG__0 (0x00000000)
3100 #define CS_SETIFG_SET_PLLLOSIFG__0_NO_EFFECT (0x00000000)
3101 #define CS_SETIFG_SET_PLLLOSIFG__1 (0x00002000)
3102 #define CS_SETIFG_SET_PLLOOLIFG (0x00001000)
3103 #define CS_SETIFG_SET_PLLOOLIFG__0 (0x00000000)
3104 #define CS_SETIFG_SET_PLLOOLIFG__0_NO_EFFECT (0x00000000)
3105 #define CS_SETIFG_SET_PLLOOLIFG__1 (0x00001000)
3106 #define CS_SETIFG_SET_PLLOORIFG (0x00004000)
3107 #define CS_SETIFG_SET_PLLOORIFG__0 (0x00000000)
3108 #define CS_SETIFG_SET_PLLOORIFG__0_NO_EFFECT (0x00000000)
3109 #define CS_SETIFG_SET_PLLOORIFG__1 (0x00004000)
3110 #define CS_STAT (HWREG32(0x40010434))
3111 #define CS_STAT_ACLK_ON (0x00010000)
3112 #define CS_STAT_ACLK_ON__0 (0x00000000)
3113 #define CS_STAT_ACLK_ON__0_INACTIVE (0x00000000)
3114 #define CS_STAT_ACLK_ON__1 (0x00010000)
3115 #define CS_STAT_ACLK_ON__1_ACTIVE (0x00010000)
3116 #define CS_STAT_ACLK_READY (0x01000000)
3117 #define CS_STAT_BCLK_READY (0x10000000)
3118 #define CS_STAT_DCOBIAS_ON (0x00000002)
3119 #define CS_STAT_DCOBIAS_ON__0 (0x00000000)
3120 #define CS_STAT_DCOBIAS_ON__0_INACTIVE (0x00000000)
3121 #define CS_STAT_DCOBIAS_ON__1 (0x00000002)
3122 #define CS_STAT_DCOBIAS_ON__1_ACTIVE (0x00000002)
3123 #define CS_STAT_DCO_ON (0x00000001)
3124 #define CS_STAT_DCO_ON__0 (0x00000000)
3125 #define CS_STAT_DCO_ON__0_INACTIVE (0x00000000)
3126 #define CS_STAT_DCO_ON__1 (0x00000001)
3127 #define CS_STAT_DCO_ON__1_ACTIVE (0x00000001)
3128 #define CS_STAT_HFXT2_ON (0x00000008)
3129 #define CS_STAT_HFXT2_ON__0 (0x00000000)
3130 #define CS_STAT_HFXT2_ON__0_INACTIVE (0x00000000)
3131 #define CS_STAT_HFXT2_ON__1 (0x00000008)
3132 #define CS_STAT_HFXT2_ON__1_ACTIVE (0x00000008)
3133 #define CS_STAT_HFXT_ON (0x00000004)
3134 #define CS_STAT_HFXT_ON__0 (0x00000000)
3135 #define CS_STAT_HFXT_ON__0_INACTIVE (0x00000000)
3136 #define CS_STAT_HFXT_ON__1 (0x00000004)
3137 #define CS_STAT_HFXT_ON__1_ACTIVE (0x00000004)
3138 #define CS_STAT_HSMCLK_ON (0x00040000)
3139 #define CS_STAT_HSMCLK_ON__0 (0x00000000)
3140 #define CS_STAT_HSMCLK_ON__0_INACTIVE (0x00000000)
3141 #define CS_STAT_HSMCLK_ON__1 (0x00040000)
3142 #define CS_STAT_HSMCLK_ON__1_ACTIVE (0x00040000)
3143 #define CS_STAT_HSMCLK_READY (0x04000000)
3144 #define CS_STAT_LFXTCLK_ON (0x00400000)
3145 #define CS_STAT_LFXTCLK_ON__0 (0x00000000)
3146 #define CS_STAT_LFXTCLK_ON__0_INACTIVE (0x00000000)
3147 #define CS_STAT_LFXTCLK_ON__1 (0x00400000)
3148 #define CS_STAT_LFXTCLK_ON__1_ACTIVE (0x00400000)
3149 #define CS_STAT_LFXT_ON (0x00000040)
3150 #define CS_STAT_LFXT_ON__0 (0x00000000)
3151 #define CS_STAT_LFXT_ON__0_INACTIVE (0x00000000)
3152 #define CS_STAT_LFXT_ON__1 (0x00000040)
3153 #define CS_STAT_LFXT_ON__1_ACTIVE (0x00000040)
3154 #define CS_STAT_MCLK_ON (0x00020000)
3155 #define CS_STAT_MCLK_ON__0 (0x00000000)
3156 #define CS_STAT_MCLK_ON__0_INACTIVE (0x00000000)
3157 #define CS_STAT_MCLK_ON__1 (0x00020000)
3158 #define CS_STAT_MCLK_ON__1_ACTIVE (0x00020000)
3159 #define CS_STAT_MCLK_READY (0x02000000)
3160 #define CS_STAT_MODCLK_ON (0x00100000)
3161 #define CS_STAT_MODCLK_ON__0 (0x00000000)
3162 #define CS_STAT_MODCLK_ON__0_INACTIVE (0x00000000)
3163 #define CS_STAT_MODCLK_ON__1 (0x00100000)
3164 #define CS_STAT_MODCLK_ON__1_ACTIVE (0x00100000)
3165 #define CS_STAT_MODOSC_ON (0x00000010)
3166 #define CS_STAT_MODOSC_ON__0 (0x00000000)
3167 #define CS_STAT_MODOSC_ON__0_INACTIVE (0x00000000)
3168 #define CS_STAT_MODOSC_ON__1 (0x00000010)
3169 #define CS_STAT_MODOSC_ON__1_ACTIVE (0x00000010)
3170 #define CS_STAT_REFOCLK_ON (0x00800000)
3171 #define CS_STAT_REFOCLK_ON__0 (0x00000000)
3172 #define CS_STAT_REFOCLK_ON__0_INACTIVE (0x00000000)
3173 #define CS_STAT_REFOCLK_ON__1 (0x00800000)
3174 #define CS_STAT_REFOCLK_ON__1_ACTIVE (0x00800000)
3175 #define CS_STAT_REFO_ON (0x00000080)
3176 #define CS_STAT_REFO_ON__0 (0x00000000)
3177 #define CS_STAT_REFO_ON__0_INACTIVE (0x00000000)
3178 #define CS_STAT_REFO_ON__1 (0x00000080)
3179 #define CS_STAT_REFO_ON__1_ACTIVE (0x00000080)
3180 #define CS_STAT_SMCLK_ON (0x00080000)
3181 #define CS_STAT_SMCLK_ON__0 (0x00000000)
3182 #define CS_STAT_SMCLK_ON__0_INACTIVE (0x00000000)
3183 #define CS_STAT_SMCLK_ON__1 (0x00080000)
3184 #define CS_STAT_SMCLK_ON__1_ACTIVE (0x00080000)
3185 #define CS_STAT_SMCLK_READY (0x08000000)
3186 #define CS_STAT_VLOCLK_ON (0x00200000)
3187 #define CS_STAT_VLOCLK_ON__0 (0x00000000)
3188 #define CS_STAT_VLOCLK_ON__0_INACTIVE (0x00000000)
3189 #define CS_STAT_VLOCLK_ON__1 (0x00200000)
3190 #define CS_STAT_VLOCLK_ON__1_ACTIVE (0x00200000)
3191 #define CS_STAT_VLO_ON (0x00000020)
3192 #define CS_STAT_VLO_ON__0 (0x00000000)
3193 #define CS_STAT_VLO_ON__0_INACTIVE (0x00000000)
3194 #define CS_STAT_VLO_ON__1 (0x00000020)
3195 #define CS_STAT_VLO_ON__1_ACTIVE (0x00000020)
3196 #define DCORSEL__0 (0x00000000)
3197 #define DCORSEL__1 (0x00010000)
3198 #define DCORSEL__2 (0x00020000)
3199 #define DCORSEL__3 (0x00030000)
3200 #define DCORSEL__4 (0x00040000)
3201 #define DCORSEL__5 (0x00050000)
3202 #define DDDS_ADC14_PARAM0 (HWREG32(0x00203038))
3203 #define DDDS_ADC14_REFTEMP0 (HWREG32(0x0020303C))
3204 #define DDDS_ADC14_REFTEMP1 (HWREG32(0x00203040))
3205 #define DDDS_ADC14_REFTEMP2 (HWREG32(0x00203044))
3206 #define DDDS_ADC14_REFTEMP3 (HWREG32(0x00203048))
3207 #define DDDS_BCREV (HWREG32(0x00203010))
3208 #define DDDS_CSDCOCONST (HWREG32(0x00203030))
3209 #define DDDS_CSDCOERCAL (HWREG32(0x0020302C))
3210 #define DDDS_CSDCOIRCAL (HWREG32(0x00203028))
3211 #define DDDS_DDDS_CHECKSUM (HWREG32(0x00203000))
3212 #define DDDS_DDDS_ENDWORD (HWREG32(0x0020306C))
3213 #define DDDS_DEVID (HWREG32(0x00203008))
3214 #define DDDS_DIE_POSITION (HWREG32(0x0020301C))
3215 #define DDDS_HWREV (HWREG32(0x0020300C))
3216 #define DDDS_LOT_ID (HWREG32(0x00203018))
3217 #define DDDS_MODID_ADC14 (HWREG32(0x00203034))
3218 #define DDDS_MODID_CS (HWREG32(0x00203024))
3219 #define DDDS_MODID_DEVINFO (HWREG32(0x00203004))
3220 #define DDDS_MODID_DIEREC (HWREG32(0x00203014))
3221 #define DDDS_MODID_RANDNUM (HWREG32(0x00203058))
3222 #define DDDS_MODID_REF (HWREG32(0x0020304C))
3223 #define DDDS_RAND0 (HWREG32(0x0020305C))
3224 #define DDDS_RAND1 (HWREG32(0x00203060))
3225 #define DDDS_RAND2 (HWREG32(0x00203064))
3226 #define DDDS_RAND3 (HWREG32(0x00203068))
3227 #define DDDS_REF_PARAM0 (HWREG32(0x00203050))
3228 #define DDDS_REF_PARAM1 (HWREG32(0x00203054))
3229 #define DDDS_TEST_RESULTS (HWREG32(0x00203020))
3230 #define DIVA__0 (0x00000000)
3231 #define DIVA__3 (0x03000000)
3232 #define DIVA__5 (0x05000000)
3233 #define DIVA__6 (0x06000000)
3234 #define DIVA__7 (0x07000000)
3235 #define DIVA__M (0x07000000)
3236 #define DIVHS__0 (0x00000000)
3237 #define DIVHS__3 (0x00300000)
3238 #define DIVHS__5 (0x00500000)
3239 #define DIVHS__6 (0x00600000)
3240 #define DIVHS__7 (0x00700000)
3241 #define DIVHS__M (0x00700000)
3242 #define DIVM__0 (0x00000000)
3243 #define DIVM__3 (0x00030000)
3244 #define DIVM__5 (0x00050000)
3245 #define DIVM__6 (0x00060000)
3246 #define DIVM__7 (0x00070000)
3247 #define DIVM__M (0x00070000)
3248 #define DIVS__0 (0x00000000)
3249 #define DIVS__3 (0x30000000)
3250 #define DIVS__5 (0x50000000)
3251 #define DIVS__6 (0x60000000)
3252 #define DIVS__7 (0x70000000)
3253 #define DIVS__M (0x70000000)
3254 #define DMA_CH0_SRCCFG (HWREG32(0x4000E010))
3255 #define DMA_CH0_SRCCFG_SRC__M (0x000000ff)
3256 #define DMA_CH10_SRCCFG (HWREG32(0x4000E038))
3257 #define DMA_CH10_SRCCFG_SRC__M (0x000000ff)
3258 #define DMA_CH11_SRCCFG (HWREG32(0x4000E03C))
3259 #define DMA_CH11_SRCCFG_SRC__M (0x000000ff)
3260 #define DMA_CH12_SRCCFG (HWREG32(0x4000E040))
3261 #define DMA_CH12_SRCCFG_SRC__M (0x000000ff)
3262 #define DMA_CH13_SRCCFG (HWREG32(0x4000E044))
3263 #define DMA_CH13_SRCCFG_SRC__M (0x000000ff)
3264 #define DMA_CH14_SRCCFG (HWREG32(0x4000E048))
3265 #define DMA_CH14_SRCCFG_SRC__M (0x000000ff)
3266 #define DMA_CH15_SRCCFG (HWREG32(0x4000E04C))
3267 #define DMA_CH15_SRCCFG_SRC__M (0x000000ff)
3268 #define DMA_CH16_SRCCFG (HWREG32(0x4000E050))
3269 #define DMA_CH16_SRCCFG_SRC__M (0x000000ff)
3270 #define DMA_CH17_SRCCFG (HWREG32(0x4000E054))
3271 #define DMA_CH17_SRCCFG_SRC__M (0x000000ff)
3272 #define DMA_CH18_SRCCFG (HWREG32(0x4000E058))
3273 #define DMA_CH18_SRCCFG_SRC__M (0x000000ff)
3274 #define DMA_CH19_SRCCFG (HWREG32(0x4000E05C))
3275 #define DMA_CH19_SRCCFG_SRC__M (0x000000ff)
3276 #define DMA_CH1_SRCCFG (HWREG32(0x4000E014))
3277 #define DMA_CH1_SRCCFG_SRC__M (0x000000ff)
3278 #define DMA_CH20_SRCCFG (HWREG32(0x4000E060))
3279 #define DMA_CH20_SRCCFG_SRC__M (0x000000ff)
3280 #define DMA_CH21_SRCCFG (HWREG32(0x4000E064))
3281 #define DMA_CH21_SRCCFG_SRC__M (0x000000ff)
3282 #define DMA_CH22_SRCCFG (HWREG32(0x4000E068))
3283 #define DMA_CH22_SRCCFG_SRC__M (0x000000ff)
3284 #define DMA_CH23_SRCCFG (HWREG32(0x4000E06C))
3285 #define DMA_CH23_SRCCFG_SRC__M (0x000000ff)
3286 #define DMA_CH24_SRCCFG (HWREG32(0x4000E070))
3287 #define DMA_CH24_SRCCFG_SRC__M (0x000000ff)
3288 #define DMA_CH25_SRCCFG (HWREG32(0x4000E074))
3289 #define DMA_CH25_SRCCFG_SRC__M (0x000000ff)
3290 #define DMA_CH26_SRCCFG (HWREG32(0x4000E078))
3291 #define DMA_CH26_SRCCFG_SRC__M (0x000000ff)
3292 #define DMA_CH27_SRCCFG (HWREG32(0x4000E07C))
3293 #define DMA_CH27_SRCCFG_SRC__M (0x000000ff)
3294 #define DMA_CH28_SRCCFG (HWREG32(0x4000E080))
3295 #define DMA_CH28_SRCCFG_SRC__M (0x000000ff)
3296 #define DMA_CH29_SRCCFG (HWREG32(0x4000E084))
3297 #define DMA_CH29_SRCCFG_SRC__M (0x000000ff)
3298 #define DMA_CH2_SRCCFG (HWREG32(0x4000E018))
3299 #define DMA_CH2_SRCCFG_SRC__M (0x000000ff)
3300 #define DMA_CH30_SRCCFG (HWREG32(0x4000E088))
3301 #define DMA_CH30_SRCCFG_SRC__M (0x000000ff)
3302 #define DMA_CH31_SRCCFG (HWREG32(0x4000E08C))
3303 #define DMA_CH31_SRCCFG_SRC__M (0x000000ff)
3304 #define DMA_CH3_SRCCFG (HWREG32(0x4000E01C))
3305 #define DMA_CH3_SRCCFG_SRC__M (0x000000ff)
3306 #define DMA_CH4_SRCCFG (HWREG32(0x4000E020))
3307 #define DMA_CH4_SRCCFG_SRC__M (0x000000ff)
3308 #define DMA_CH5_SRCCFG (HWREG32(0x4000E024))
3309 #define DMA_CH5_SRCCFG_SRC__M (0x000000ff)
3310 #define DMA_CH6_SRCCFG (HWREG32(0x4000E028))
3311 #define DMA_CH6_SRCCFG_SRC__M (0x000000ff)
3312 #define DMA_CH7_SRCCFG (HWREG32(0x4000E02C))
3313 #define DMA_CH7_SRCCFG_SRC__M (0x000000ff)
3314 #define DMA_CH8_SRCCFG (HWREG32(0x4000E030))
3315 #define DMA_CH8_SRCCFG_SRC__M (0x000000ff)
3316 #define DMA_CH9_SRCCFG (HWREG32(0x4000E034))
3317 #define DMA_CH9_SRCCFG_SRC__M (0x000000ff)
3318 #define DMA_DEVCONFIG_NUM_DMA_CHANNELS__M (0x000000ff)
3319 #define DMA_DEVCONFIG_NUM_SRC_PER_CHANNEL__M (0x0000ff00)
3320 #define DMA_INT0_CLRFLG (HWREG32(0x4000E114))
3321 #define DMA_INT0_CLRFLG_CH0 (0x00000001)
3322 #define DMA_INT0_CLRFLG_CH1 (0x00000002)
3323 #define DMA_INT0_CLRFLG_CH10 (0x00000400)
3324 #define DMA_INT0_CLRFLG_CH11 (0x00000800)
3325 #define DMA_INT0_CLRFLG_CH12 (0x00001000)
3326 #define DMA_INT0_CLRFLG_CH13 (0x00002000)
3327 #define DMA_INT0_CLRFLG_CH14 (0x00004000)
3328 #define DMA_INT0_CLRFLG_CH15 (0x00008000)
3329 #define DMA_INT0_CLRFLG_CH16 (0x00010000)
3330 #define DMA_INT0_CLRFLG_CH17 (0x00020000)
3331 #define DMA_INT0_CLRFLG_CH18 (0x00040000)
3332 #define DMA_INT0_CLRFLG_CH19 (0x00080000)
3333 #define DMA_INT0_CLRFLG_CH2 (0x00000004)
3334 #define DMA_INT0_CLRFLG_CH20 (0x00100000)
3335 #define DMA_INT0_CLRFLG_CH21 (0x00200000)
3336 #define DMA_INT0_CLRFLG_CH22 (0x00400000)
3337 #define DMA_INT0_CLRFLG_CH23 (0x00800000)
3338 #define DMA_INT0_CLRFLG_CH24 (0x01000000)
3339 #define DMA_INT0_CLRFLG_CH25 (0x02000000)
3340 #define DMA_INT0_CLRFLG_CH26 (0x04000000)
3341 #define DMA_INT0_CLRFLG_CH27 (0x08000000)
3342 #define DMA_INT0_CLRFLG_CH28 (0x10000000)
3343 #define DMA_INT0_CLRFLG_CH29 (0x20000000)
3344 #define DMA_INT0_CLRFLG_CH3 (0x00000008)
3345 #define DMA_INT0_CLRFLG_CH30 (0x40000000)
3346 #define DMA_INT0_CLRFLG_CH31 (0x80000000)
3347 #define DMA_INT0_CLRFLG_CH4 (0x00000010)
3348 #define DMA_INT0_CLRFLG_CH5 (0x00000020)
3349 #define DMA_INT0_CLRFLG_CH6 (0x00000040)
3350 #define DMA_INT0_CLRFLG_CH7 (0x00000080)
3351 #define DMA_INT0_CLRFLG_CH8 (0x00000100)
3352 #define DMA_INT0_CLRFLG_CH9 (0x00000200)
3353 #define DMA_INT0_SRCFLG (HWREG32(0x4000E110))
3354 #define DMA_INT0_SRCFLG_CH0 (0x00000001)
3355 #define DMA_INT0_SRCFLG_CH1 (0x00000002)
3356 #define DMA_INT0_SRCFLG_CH10 (0x00000400)
3357 #define DMA_INT0_SRCFLG_CH11 (0x00000800)
3358 #define DMA_INT0_SRCFLG_CH12 (0x00001000)
3359 #define DMA_INT0_SRCFLG_CH13 (0x00002000)
3360 #define DMA_INT0_SRCFLG_CH14 (0x00004000)
3361 #define DMA_INT0_SRCFLG_CH15 (0x00008000)
3362 #define DMA_INT0_SRCFLG_CH16 (0x00010000)
3363 #define DMA_INT0_SRCFLG_CH17 (0x00020000)
3364 #define DMA_INT0_SRCFLG_CH18 (0x00040000)
3365 #define DMA_INT0_SRCFLG_CH19 (0x00080000)
3366 #define DMA_INT0_SRCFLG_CH2 (0x00000004)
3367 #define DMA_INT0_SRCFLG_CH20 (0x00100000)
3368 #define DMA_INT0_SRCFLG_CH21 (0x00200000)
3369 #define DMA_INT0_SRCFLG_CH22 (0x00400000)
3370 #define DMA_INT0_SRCFLG_CH23 (0x00800000)
3371 #define DMA_INT0_SRCFLG_CH24 (0x01000000)
3372 #define DMA_INT0_SRCFLG_CH25 (0x02000000)
3373 #define DMA_INT0_SRCFLG_CH26 (0x04000000)
3374 #define DMA_INT0_SRCFLG_CH27 (0x08000000)
3375 #define DMA_INT0_SRCFLG_CH28 (0x10000000)
3376 #define DMA_INT0_SRCFLG_CH29 (0x20000000)
3377 #define DMA_INT0_SRCFLG_CH3 (0x00000008)
3378 #define DMA_INT0_SRCFLG_CH30 (0x40000000)
3379 #define DMA_INT0_SRCFLG_CH31 (0x80000000)
3380 #define DMA_INT0_SRCFLG_CH4 (0x00000010)
3381 #define DMA_INT0_SRCFLG_CH5 (0x00000020)
3382 #define DMA_INT0_SRCFLG_CH6 (0x00000040)
3383 #define DMA_INT0_SRCFLG_CH7 (0x00000080)
3384 #define DMA_INT0_SRCFLG_CH8 (0x00000100)
3385 #define DMA_INT0_SRCFLG_CH9 (0x00000200)
3386 #define DMA_INT1_SRCCFG (HWREG32(0x4000E100))
3387 #define DMA_INT1_SRCCFG_EN (0x00000020)
3388 #define DMA_INT1_SRCCFG_INT_SRC__M (0x0000001f)
3389 #define DMA_INT2_SRCCFG (HWREG32(0x4000E104))
3390 #define DMA_INT2_SRCCFG_EN (0x00000020)
3391 #define DMA_INT2_SRCCFG_INT_SRC__M (0x0000001f)
3392 #define DMA_INT3_SRCCFG (HWREG32(0x4000E108))
3393 #define DMA_INT3_SRCCFG_EN (0x00000020)
3394 #define DMA_INT3_SRCCFG_INT_SRC__M (0x0000001f)
3395 #define DMA_SW_CHTRIG (HWREG32(0x4000E004))
3396 #define DMA_SW_CHTRIG_CH0 (0x00000001)
3397 #define DMA_SW_CHTRIG_CH1 (0x00000002)
3398 #define DMA_SW_CHTRIG_CH10 (0x00000400)
3399 #define DMA_SW_CHTRIG_CH11 (0x00000800)
3400 #define DMA_SW_CHTRIG_CH12 (0x00001000)
3401 #define DMA_SW_CHTRIG_CH13 (0x00002000)
3402 #define DMA_SW_CHTRIG_CH14 (0x00004000)
3403 #define DMA_SW_CHTRIG_CH15 (0x00008000)
3404 #define DMA_SW_CHTRIG_CH16 (0x00010000)
3405 #define DMA_SW_CHTRIG_CH17 (0x00020000)
3406 #define DMA_SW_CHTRIG_CH18 (0x00040000)
3407 #define DMA_SW_CHTRIG_CH19 (0x00080000)
3408 #define DMA_SW_CHTRIG_CH2 (0x00000004)
3409 #define DMA_SW_CHTRIG_CH20 (0x00100000)
3410 #define DMA_SW_CHTRIG_CH21 (0x00200000)
3411 #define DMA_SW_CHTRIG_CH22 (0x00400000)
3412 #define DMA_SW_CHTRIG_CH23 (0x00800000)
3413 #define DMA_SW_CHTRIG_CH24 (0x01000000)
3414 #define DMA_SW_CHTRIG_CH25 (0x02000000)
3415 #define DMA_SW_CHTRIG_CH26 (0x04000000)
3416 #define DMA_SW_CHTRIG_CH27 (0x08000000)
3417 #define DMA_SW_CHTRIG_CH28 (0x10000000)
3418 #define DMA_SW_CHTRIG_CH29 (0x20000000)
3419 #define DMA_SW_CHTRIG_CH3 (0x00000008)
3420 #define DMA_SW_CHTRIG_CH30 (0x40000000)
3421 #define DMA_SW_CHTRIG_CH31 (0x80000000)
3422 #define DMA_SW_CHTRIG_CH4 (0x00000010)
3423 #define DMA_SW_CHTRIG_CH5 (0x00000020)
3424 #define DMA_SW_CHTRIG_CH6 (0x00000040)
3425 #define DMA_SW_CHTRIG_CH7 (0x00000080)
3426 #define DMA_SW_CHTRIG_CH8 (0x00000100)
3427 #define DMA_SW_CHTRIG_CH9 (0x00000200)
3428 #define DWT_CPICNT_CPICNT__M (0x000000ff)
3429 #define DWT_CTRL_CPIEVTENA__0 (0x00000000)
3430 #define DWT_CTRL_CPIEVTENA__1 (0x00020000)
3431 #define DWT_CTRL_CYCEVTENA__0 (0x00000000)
3432 #define DWT_CTRL_CYCEVTENA__1 (0x00400000)
3433 #define DWT_CTRL_CYCTAP__0 (0x00000000)
3434 #define DWT_CTRL_CYCTAP__1 (0x00000200)
3435 #define DWT_CTRL_EXCEVTENA__0 (0x00000000)
3436 #define DWT_CTRL_EXCEVTENA__1 (0x00040000)
3437 #define DWT_CTRL_EXCTRCENA__0 (0x00000000)
3438 #define DWT_CTRL_EXCTRCENA__1 (0x00010000)
3439 #define DWT_CTRL_FOLDEVTENA__0 (0x00000000)
3440 #define DWT_CTRL_FOLDEVTENA__1 (0x00200000)
3441 #define DWT_CTRL_LSUEVTENA__0 (0x00000000)
3442 #define DWT_CTRL_LSUEVTENA__1 (0x00100000)
3443 #define DWT_CTRL_PCSAMPLEENA__0 (0x00000000)
3444 #define DWT_CTRL_PCSAMPLEENA__1 (0x00001000)
3445 #define DWT_CTRL_POSTCNT__M (0x000001e0)
3446 #define DWT_CTRL_POSTPRESET__M (0x0000001e)
3447 #define DWT_CTRL_SLEEPEVTENA__0 (0x00000000)
3448 #define DWT_CTRL_SLEEPEVTENA__1 (0x00080000)
3449 #define DWT_CTRL_SYNCTAP__0 (0x00000000)
3450 #define DWT_CTRL_SYNCTAP__1 (0x00000400)
3451 #define DWT_CTRL_SYNCTAP__2 (0x00000800)
3452 #define DWT_CTRL_SYNCTAP__3 (0x00000c00)
3453 #define DWT_CTRL_SYNCTAP__M (0x00000c00)
3454 #define DWT_EXCCNT_EXCCNT__M (0x000000ff)
3455 #define DWT_FOLDCNT_FOLDCNT__M (0x000000ff)
3456 #define DWT_FUNCTION0_DATAVADDR0__M (0x0000f000)
3457 #define DWT_FUNCTION0_DATAVADDR1__M (0x000f0000)
3458 #define DWT_FUNCTION0_DATAVSIZE__0 (0x00000000)
3459 #define DWT_FUNCTION0_DATAVSIZE__0_BYTE (0x00000000)
3460 #define DWT_FUNCTION0_DATAVSIZE__1 (0x00000400)
3461 #define DWT_FUNCTION0_DATAVSIZE__1_HALFWORD (0x00000400)
3462 #define DWT_FUNCTION0_DATAVSIZE__2 (0x00000800)
3463 #define DWT_FUNCTION0_DATAVSIZE__2_WORD (0x00000800)
3464 #define DWT_FUNCTION0_DATAVSIZE__3 (0x00000c00)
3465 #define DWT_FUNCTION0_DATAVSIZE__3_UNPREDICTABLE (0x00000c00)
3466 #define DWT_FUNCTION0_DATAVSIZE__M (0x00000c00)
3467 #define DWT_FUNCTION0_FUNCTION__0 (0x00000000)
3468 #define DWT_FUNCTION0_FUNCTION__0_DISABLED (0x00000000)
3469 #define DWT_FUNCTION0_FUNCTION__1 (0x00000001)
3470 #define DWT_FUNCTION0_FUNCTION__10 (0x0000000a)
3471 #define DWT_FUNCTION0_FUNCTION__11 (0x0000000b)
3472 #define DWT_FUNCTION0_FUNCTION__12 (0x0000000c)
3473 #define DWT_FUNCTION0_FUNCTION__13 (0x0000000d)
3474 #define DWT_FUNCTION0_FUNCTION__14 (0x0000000e)
3475 #define DWT_FUNCTION0_FUNCTION__15 (0x0000000f)
3476 #define DWT_FUNCTION0_FUNCTION__2 (0x00000002)
3477 #define DWT_FUNCTION0_FUNCTION__3 (0x00000003)
3478 #define DWT_FUNCTION0_FUNCTION__4 (0x00000004)
3479 #define DWT_FUNCTION0_FUNCTION__5 (0x00000005)
3480 #define DWT_FUNCTION0_FUNCTION__6 (0x00000006)
3481 #define DWT_FUNCTION0_FUNCTION__7 (0x00000007)
3482 #define DWT_FUNCTION0_FUNCTION__8 (0x00000008)
3483 #define DWT_FUNCTION0_FUNCTION__9 (0x00000009)
3484 #define DWT_FUNCTION0_FUNCTION__M (0x0000000f)
3485 #define DWT_FUNCTION0_LNK1ENA__0 (0x00000000)
3486 #define DWT_FUNCTION0_LNK1ENA__1 (0x00000200)
3487 #define DWT_FUNCTION1_DATAVADDR0__M (0x0000f000)
3488 #define DWT_FUNCTION1_DATAVADDR1__M (0x000f0000)
3489 #define DWT_FUNCTION1_DATAVSIZE__0 (0x00000000)
3490 #define DWT_FUNCTION1_DATAVSIZE__0_BYTE (0x00000000)
3491 #define DWT_FUNCTION1_DATAVSIZE__1 (0x00000400)
3492 #define DWT_FUNCTION1_DATAVSIZE__1_HALFWORD (0x00000400)
3493 #define DWT_FUNCTION1_DATAVSIZE__2 (0x00000800)
3494 #define DWT_FUNCTION1_DATAVSIZE__2_WORD (0x00000800)
3495 #define DWT_FUNCTION1_DATAVSIZE__3 (0x00000c00)
3496 #define DWT_FUNCTION1_DATAVSIZE__3_UNPREDICTABLE (0x00000c00)
3497 #define DWT_FUNCTION1_DATAVSIZE__M (0x00000c00)
3498 #define DWT_FUNCTION1_FUNCTION__0 (0x00000000)
3499 #define DWT_FUNCTION1_FUNCTION__0_DISABLED (0x00000000)
3500 #define DWT_FUNCTION1_FUNCTION__1 (0x00000001)
3501 #define DWT_FUNCTION1_FUNCTION__10 (0x0000000a)
3502 #define DWT_FUNCTION1_FUNCTION__11 (0x0000000b)
3503 #define DWT_FUNCTION1_FUNCTION__12 (0x0000000c)
3504 #define DWT_FUNCTION1_FUNCTION__13 (0x0000000d)
3505 #define DWT_FUNCTION1_FUNCTION__14 (0x0000000e)
3506 #define DWT_FUNCTION1_FUNCTION__15 (0x0000000f)
3507 #define DWT_FUNCTION1_FUNCTION__2 (0x00000002)
3508 #define DWT_FUNCTION1_FUNCTION__3 (0x00000003)
3509 #define DWT_FUNCTION1_FUNCTION__4 (0x00000004)
3510 #define DWT_FUNCTION1_FUNCTION__5 (0x00000005)
3511 #define DWT_FUNCTION1_FUNCTION__6 (0x00000006)
3512 #define DWT_FUNCTION1_FUNCTION__7 (0x00000007)
3513 #define DWT_FUNCTION1_FUNCTION__8 (0x00000008)
3514 #define DWT_FUNCTION1_FUNCTION__9 (0x00000009)
3515 #define DWT_FUNCTION1_FUNCTION__M (0x0000000f)
3516 #define DWT_FUNCTION1_LNK1ENA__0 (0x00000000)
3517 #define DWT_FUNCTION1_LNK1ENA__1 (0x00000200)
3518 #define DWT_FUNCTION2_DATAVADDR0__M (0x0000f000)
3519 #define DWT_FUNCTION2_DATAVADDR1__M (0x000f0000)
3520 #define DWT_FUNCTION2_DATAVSIZE__0 (0x00000000)
3521 #define DWT_FUNCTION2_DATAVSIZE__0_BYTE (0x00000000)
3522 #define DWT_FUNCTION2_DATAVSIZE__1 (0x00000400)
3523 #define DWT_FUNCTION2_DATAVSIZE__1_HALFWORD (0x00000400)
3524 #define DWT_FUNCTION2_DATAVSIZE__2 (0x00000800)
3525 #define DWT_FUNCTION2_DATAVSIZE__2_WORD (0x00000800)
3526 #define DWT_FUNCTION2_DATAVSIZE__3 (0x00000c00)
3527 #define DWT_FUNCTION2_DATAVSIZE__3_UNPREDICTABLE (0x00000c00)
3528 #define DWT_FUNCTION2_DATAVSIZE__M (0x00000c00)
3529 #define DWT_FUNCTION2_FUNCTION__0 (0x00000000)
3530 #define DWT_FUNCTION2_FUNCTION__0_DISABLED (0x00000000)
3531 #define DWT_FUNCTION2_FUNCTION__1 (0x00000001)
3532 #define DWT_FUNCTION2_FUNCTION__10 (0x0000000a)
3533 #define DWT_FUNCTION2_FUNCTION__11 (0x0000000b)
3534 #define DWT_FUNCTION2_FUNCTION__12 (0x0000000c)
3535 #define DWT_FUNCTION2_FUNCTION__13 (0x0000000d)
3536 #define DWT_FUNCTION2_FUNCTION__14 (0x0000000e)
3537 #define DWT_FUNCTION2_FUNCTION__15 (0x0000000f)
3538 #define DWT_FUNCTION2_FUNCTION__2 (0x00000002)
3539 #define DWT_FUNCTION2_FUNCTION__3 (0x00000003)
3540 #define DWT_FUNCTION2_FUNCTION__4 (0x00000004)
3541 #define DWT_FUNCTION2_FUNCTION__5 (0x00000005)
3542 #define DWT_FUNCTION2_FUNCTION__6 (0x00000006)
3543 #define DWT_FUNCTION2_FUNCTION__7 (0x00000007)
3544 #define DWT_FUNCTION2_FUNCTION__8 (0x00000008)
3545 #define DWT_FUNCTION2_FUNCTION__9 (0x00000009)
3546 #define DWT_FUNCTION2_FUNCTION__M (0x0000000f)
3547 #define DWT_FUNCTION2_LNK1ENA__0 (0x00000000)
3548 #define DWT_FUNCTION2_LNK1ENA__1 (0x00000200)
3549 #define DWT_FUNCTION3_DATAVADDR0__M (0x0000f000)
3550 #define DWT_FUNCTION3_DATAVADDR1__M (0x000f0000)
3551 #define DWT_FUNCTION3_DATAVSIZE__0 (0x00000000)
3552 #define DWT_FUNCTION3_DATAVSIZE__0_BYTE (0x00000000)
3553 #define DWT_FUNCTION3_DATAVSIZE__1 (0x00000400)
3554 #define DWT_FUNCTION3_DATAVSIZE__1_HALFWORD (0x00000400)
3555 #define DWT_FUNCTION3_DATAVSIZE__2 (0x00000800)
3556 #define DWT_FUNCTION3_DATAVSIZE__2_WORD (0x00000800)
3557 #define DWT_FUNCTION3_DATAVSIZE__3 (0x00000c00)
3558 #define DWT_FUNCTION3_DATAVSIZE__3_UNPREDICTABLE (0x00000c00)
3559 #define DWT_FUNCTION3_DATAVSIZE__M (0x00000c00)
3560 #define DWT_FUNCTION3_FUNCTION__0 (0x00000000)
3561 #define DWT_FUNCTION3_FUNCTION__0_DISABLED (0x00000000)
3562 #define DWT_FUNCTION3_FUNCTION__1 (0x00000001)
3563 #define DWT_FUNCTION3_FUNCTION__10 (0x0000000a)
3564 #define DWT_FUNCTION3_FUNCTION__11 (0x0000000b)
3565 #define DWT_FUNCTION3_FUNCTION__12 (0x0000000c)
3566 #define DWT_FUNCTION3_FUNCTION__13 (0x0000000d)
3567 #define DWT_FUNCTION3_FUNCTION__14 (0x0000000e)
3568 #define DWT_FUNCTION3_FUNCTION__15 (0x0000000f)
3569 #define DWT_FUNCTION3_FUNCTION__2 (0x00000002)
3570 #define DWT_FUNCTION3_FUNCTION__3 (0x00000003)
3571 #define DWT_FUNCTION3_FUNCTION__4 (0x00000004)
3572 #define DWT_FUNCTION3_FUNCTION__5 (0x00000005)
3573 #define DWT_FUNCTION3_FUNCTION__6 (0x00000006)
3574 #define DWT_FUNCTION3_FUNCTION__7 (0x00000007)
3575 #define DWT_FUNCTION3_FUNCTION__8 (0x00000008)
3576 #define DWT_FUNCTION3_FUNCTION__9 (0x00000009)
3577 #define DWT_FUNCTION3_FUNCTION__M (0x0000000f)
3578 #define DWT_FUNCTION3_LNK1ENA__0 (0x00000000)
3579 #define DWT_FUNCTION3_LNK1ENA__1 (0x00000200)
3580 #define DWT_LSUCNT_LSUCNT__M (0x000000ff)
3581 #define DWT_MASK0_MASK__M (0x0000000f)
3582 #define DWT_MASK1_MASK__M (0x0000000f)
3583 #define DWT_MASK2_MASK__M (0x0000000f)
3584 #define DWT_MASK3_MASK__M (0x0000000f)
3585 #define DWT_SLEEPCNT_SLEEPCNT__M (0x000000ff)
3586 #define EUSCI_A0_SPI_BRW (HWREG16(0x40001006))
3587 #define EUSCI_A0_SPI_CTLW0 (HWREG16(0x40001000))
3588 #define EUSCI_A0_SPI_CTLW0_UC7BIT (0x1000)
3589 #define EUSCI_A0_SPI_CTLW0_UC7BIT__0 (0x0000)
3590 #define EUSCI_A0_SPI_CTLW0_UC7BIT__0_8_BIT_DATA (0x0000)
3591 #define EUSCI_A0_SPI_CTLW0_UC7BIT__1 (0x1000)
3592 #define EUSCI_A0_SPI_CTLW0_UC7BIT__1_7_BIT_DATA (0x1000)
3593 #define EUSCI_A0_SPI_CTLW0_UCCKPH (0x8000)
3594 #define EUSCI_A0_SPI_CTLW0_UCCKPH__0 (0x0000)
3595 #define EUSCI_A0_SPI_CTLW0_UCCKPH__1 (0x8000)
3596 #define EUSCI_A0_SPI_CTLW0_UCCKPL (0x4000)
3597 #define EUSCI_A0_SPI_CTLW0_UCCKPL__0 (0x0000)
3598 #define EUSCI_A0_SPI_CTLW0_UCCKPL__1 (0x4000)
3599 #define EUSCI_A0_SPI_CTLW0_UCMODE__0 (0x0000)
3600 #define EUSCI_A0_SPI_CTLW0_UCMODE__0_3_PIN_SPI (0x0000)
3601 #define EUSCI_A0_SPI_CTLW0_UCMODE__1 (0x0200)
3602 #define EUSCI_A0_SPI_CTLW0_UCMODE__2 (0x0400)
3603 #define EUSCI_A0_SPI_CTLW0_UCMODE__3 (0x0600)
3604 #define EUSCI_A0_SPI_CTLW0_UCMODE__3_I2C_MODE (0x0600)
3605 #define EUSCI_A0_SPI_CTLW0_UCMODE__M (0x0600)
3606 #define EUSCI_A0_SPI_CTLW0_UCMSB (0x2000)
3607 #define EUSCI_A0_SPI_CTLW0_UCMSB__0 (0x0000)
3608 #define EUSCI_A0_SPI_CTLW0_UCMSB__0_LSB_FIRST (0x0000)
3609 #define EUSCI_A0_SPI_CTLW0_UCMSB__1 (0x2000)
3610 #define EUSCI_A0_SPI_CTLW0_UCMSB__1_MSB_FIRST (0x2000)
3611 #define EUSCI_A0_SPI_CTLW0_UCMST (0x0800)
3612 #define EUSCI_A0_SPI_CTLW0_UCMST__0 (0x0000)
3613 #define EUSCI_A0_SPI_CTLW0_UCMST__0_SLAVE_MODE (0x0000)
3614 #define EUSCI_A0_SPI_CTLW0_UCMST__1 (0x0800)
3615 #define EUSCI_A0_SPI_CTLW0_UCMST__1_MASTER_MODE (0x0800)
3616 #define EUSCI_A0_SPI_CTLW0_UCSSEL__1 (0x0040)
3617 #define EUSCI_A0_SPI_CTLW0_UCSSEL__1_ACLK (0x0040)
3618 #define EUSCI_A0_SPI_CTLW0_UCSSEL__2 (0x0080)
3619 #define EUSCI_A0_SPI_CTLW0_UCSSEL__2_SMCLK (0x0080)
3620 #define EUSCI_A0_SPI_CTLW0_UCSSEL__3 (0x00c0)
3621 #define EUSCI_A0_SPI_CTLW0_UCSSEL__3_SMCLK (0x00c0)
3622 #define EUSCI_A0_SPI_CTLW0_UCSSEL__M (0x00c0)
3623 #define EUSCI_A0_SPI_CTLW0_UCSTEM (0x0002)
3624 #define EUSCI_A0_SPI_CTLW0_UCSTEM__0 (0x0000)
3625 #define EUSCI_A0_SPI_CTLW0_UCSTEM__1 (0x0002)
3626 #define EUSCI_A0_SPI_CTLW0_UCSWRST (0x0001)
3627 #define EUSCI_A0_SPI_CTLW0_UCSWRST__0 (0x0000)
3628 #define EUSCI_A0_SPI_CTLW0_UCSWRST__1 (0x0001)
3629 #define EUSCI_A0_SPI_CTLW0_UCSYNC (0x0100)
3630 #define EUSCI_A0_SPI_CTLW0_UCSYNC__0 (0x0000)
3631 #define EUSCI_A0_SPI_CTLW0_UCSYNC__1 (0x0100)
3632 #define EUSCI_A0_SPI_IE (HWREG16(0x4000101A))
3633 #define EUSCI_A0_SPI_IE_UCRXIE (0x0001)
3634 #define EUSCI_A0_SPI_IE_UCRXIE__0 (0x0000)
3635 #define EUSCI_A0_SPI_IE_UCRXIE__1 (0x0001)
3636 #define EUSCI_A0_SPI_IE_UCTXIE (0x0002)
3637 #define EUSCI_A0_SPI_IE_UCTXIE__0 (0x0000)
3638 #define EUSCI_A0_SPI_IE_UCTXIE__1 (0x0002)
3639 #define EUSCI_A0_SPI_IFG (HWREG16(0x4000101C))
3640 #define EUSCI_A0_SPI_IFG_UCRXIFG (0x0001)
3641 #define EUSCI_A0_SPI_IFG_UCRXIFG__0 (0x0000)
3642 #define EUSCI_A0_SPI_IFG_UCRXIFG__1 (0x0001)
3643 #define EUSCI_A0_SPI_IFG_UCTXIFG (0x0002)
3644 #define EUSCI_A0_SPI_IFG_UCTXIFG__0 (0x0000)
3645 #define EUSCI_A0_SPI_IFG_UCTXIFG__1 (0x0002)
3646 #define EUSCI_A0_SPI_IV (HWREG16(0x4000101E))
3647 #define EUSCI_A0_SPI_RXBUF (HWREG16(0x4000100C))
3648 #define EUSCI_A0_SPI_RXBUF_UCRXBUF__M (0x00ff)
3649 #define EUSCI_A0_SPI_STATW (HWREG16(0x4000100A))
3650 #define EUSCI_A0_SPI_STATW_UCBUSY (0x0001)
3651 #define EUSCI_A0_SPI_STATW_UCBUSY__0 (0x0000)
3652 #define EUSCI_A0_SPI_STATW_UCBUSY__0_EUSCI_INACTIVE (0x0000)
3653 #define EUSCI_A0_SPI_STATW_UCBUSY__1 (0x0001)
3654 #define EUSCI_A0_SPI_STATW_UCFE (0x0040)
3655 #define EUSCI_A0_SPI_STATW_UCFE__0 (0x0000)
3656 #define EUSCI_A0_SPI_STATW_UCFE__0_NO_ERROR (0x0000)
3657 #define EUSCI_A0_SPI_STATW_UCFE__1 (0x0040)
3658 #define EUSCI_A0_SPI_STATW_UCLISTEN (0x0080)
3659 #define EUSCI_A0_SPI_STATW_UCLISTEN__0 (0x0000)
3660 #define EUSCI_A0_SPI_STATW_UCLISTEN__0_DISABLED (0x0000)
3661 #define EUSCI_A0_SPI_STATW_UCLISTEN__1 (0x0080)
3662 #define EUSCI_A0_SPI_STATW_UCOE (0x0020)
3663 #define EUSCI_A0_SPI_STATW_UCOE__0 (0x0000)
3664 #define EUSCI_A0_SPI_STATW_UCOE__0_NO_ERROR (0x0000)
3665 #define EUSCI_A0_SPI_STATW_UCOE__1 (0x0020)
3666 #define EUSCI_A0_SPI_TXBUF (HWREG16(0x4000100E))
3667 #define EUSCI_A0_SPI_TXBUF_UCTXBUF__M (0x00ff)
3668 #define EUSCI_A0_UART_ABCTL (HWREG16(0x40001010))
3669 #define EUSCI_A0_UART_ABCTL_UCABDEN (0x0001)
3670 #define EUSCI_A0_UART_ABCTL_UCABDEN__0 (0x0000)
3671 #define EUSCI_A0_UART_ABCTL_UCABDEN__1 (0x0001)
3672 #define EUSCI_A0_UART_ABCTL_UCBTOE (0x0004)
3673 #define EUSCI_A0_UART_ABCTL_UCBTOE__0 (0x0000)
3674 #define EUSCI_A0_UART_ABCTL_UCBTOE__0_NO_ERROR (0x0000)
3675 #define EUSCI_A0_UART_ABCTL_UCBTOE__1 (0x0004)
3676 #define EUSCI_A0_UART_ABCTL_UCDELIM__0 (0x0000)
3677 #define EUSCI_A0_UART_ABCTL_UCDELIM__0_1_BIT_TIME (0x0000)
3678 #define EUSCI_A0_UART_ABCTL_UCDELIM__1 (0x0010)
3679 #define EUSCI_A0_UART_ABCTL_UCDELIM__1_2_BIT_TIMES (0x0010)
3680 #define EUSCI_A0_UART_ABCTL_UCDELIM__2 (0x0020)
3681 #define EUSCI_A0_UART_ABCTL_UCDELIM__2_3_BIT_TIMES (0x0020)
3682 #define EUSCI_A0_UART_ABCTL_UCDELIM__3 (0x0030)
3683 #define EUSCI_A0_UART_ABCTL_UCDELIM__3_4_BIT_TIMES (0x0030)
3684 #define EUSCI_A0_UART_ABCTL_UCDELIM__M (0x0030)
3685 #define EUSCI_A0_UART_ABCTL_UCSTOE (0x0008)
3686 #define EUSCI_A0_UART_ABCTL_UCSTOE__0 (0x0000)
3687 #define EUSCI_A0_UART_ABCTL_UCSTOE__0_NO_ERROR (0x0000)
3688 #define EUSCI_A0_UART_ABCTL_UCSTOE__1 (0x0008)
3689 #define EUSCI_A0_UART_BRW (HWREG16(0x40001006))
3690 #define EUSCI_A0_UART_CTLW0 (HWREG16(0x40001000))
3691 #define EUSCI_A0_UART_CTLW0_UC7BIT (0x1000)
3692 #define EUSCI_A0_UART_CTLW0_UC7BIT__0 (0x0000)
3693 #define EUSCI_A0_UART_CTLW0_UC7BIT__0_8_BIT_DATA (0x0000)
3694 #define EUSCI_A0_UART_CTLW0_UC7BIT__1 (0x1000)
3695 #define EUSCI_A0_UART_CTLW0_UC7BIT__1_7_BIT_DATA (0x1000)
3696 #define EUSCI_A0_UART_CTLW0_UCBRKIE (0x0010)
3697 #define EUSCI_A0_UART_CTLW0_UCBRKIE__0 (0x0000)
3698 #define EUSCI_A0_UART_CTLW0_UCBRKIE__1 (0x0010)
3699 #define EUSCI_A0_UART_CTLW0_UCDORM (0x0008)
3700 #define EUSCI_A0_UART_CTLW0_UCDORM__0 (0x0000)
3701 #define EUSCI_A0_UART_CTLW0_UCDORM__1 (0x0008)
3702 #define EUSCI_A0_UART_CTLW0_UCMODE__0 (0x0000)
3703 #define EUSCI_A0_UART_CTLW0_UCMODE__0_UART_MODE (0x0000)
3704 #define EUSCI_A0_UART_CTLW0_UCMODE__1 (0x0200)
3705 #define EUSCI_A0_UART_CTLW0_UCMODE__2 (0x0400)
3706 #define EUSCI_A0_UART_CTLW0_UCMODE__3 (0x0600)
3707 #define EUSCI_A0_UART_CTLW0_UCMODE__M (0x0600)
3708 #define EUSCI_A0_UART_CTLW0_UCMSB (0x2000)
3709 #define EUSCI_A0_UART_CTLW0_UCMSB__0 (0x0000)
3710 #define EUSCI_A0_UART_CTLW0_UCMSB__0_LSB_FIRST (0x0000)
3711 #define EUSCI_A0_UART_CTLW0_UCMSB__1 (0x2000)
3712 #define EUSCI_A0_UART_CTLW0_UCMSB__1_MSB_FIRST (0x2000)
3713 #define EUSCI_A0_UART_CTLW0_UCPAR (0x4000)
3714 #define EUSCI_A0_UART_CTLW0_UCPAR__0 (0x0000)
3715 #define EUSCI_A0_UART_CTLW0_UCPAR__0_ODD_PARITY (0x0000)
3716 #define EUSCI_A0_UART_CTLW0_UCPAR__1 (0x4000)
3717 #define EUSCI_A0_UART_CTLW0_UCPAR__1_EVEN_PARITY (0x4000)
3718 #define EUSCI_A0_UART_CTLW0_UCPEN (0x8000)
3719 #define EUSCI_A0_UART_CTLW0_UCPEN__0 (0x0000)
3720 #define EUSCI_A0_UART_CTLW0_UCPEN__0_PARITY_DISABLED (0x0000)
3721 #define EUSCI_A0_UART_CTLW0_UCPEN__1 (0x8000)
3722 #define EUSCI_A0_UART_CTLW0_UCRXEIE (0x0020)
3723 #define EUSCI_A0_UART_CTLW0_UCRXEIE__0 (0x0000)
3724 #define EUSCI_A0_UART_CTLW0_UCRXEIE__1 (0x0020)
3725 #define EUSCI_A0_UART_CTLW0_UCSPB (0x0800)
3726 #define EUSCI_A0_UART_CTLW0_UCSPB__0 (0x0000)
3727 #define EUSCI_A0_UART_CTLW0_UCSPB__0_ONE_STOP_BIT (0x0000)
3728 #define EUSCI_A0_UART_CTLW0_UCSPB__1 (0x0800)
3729 #define EUSCI_A0_UART_CTLW0_UCSPB__1_TWO_STOP_BITS (0x0800)
3730 #define EUSCI_A0_UART_CTLW0_UCSSEL__0 (0x0000)
3731 #define EUSCI_A0_UART_CTLW0_UCSSEL__0_UCLK (0x0000)
3732 #define EUSCI_A0_UART_CTLW0_UCSSEL__1 (0x0040)
3733 #define EUSCI_A0_UART_CTLW0_UCSSEL__1_ACLK (0x0040)
3734 #define EUSCI_A0_UART_CTLW0_UCSSEL__2 (0x0080)
3735 #define EUSCI_A0_UART_CTLW0_UCSSEL__2_SMCLK (0x0080)
3736 #define EUSCI_A0_UART_CTLW0_UCSSEL__3 (0x00c0)
3737 #define EUSCI_A0_UART_CTLW0_UCSSEL__3_SMCLK (0x00c0)
3738 #define EUSCI_A0_UART_CTLW0_UCSSEL__M (0x00c0)
3739 #define EUSCI_A0_UART_CTLW0_UCSWRST (0x0001)
3740 #define EUSCI_A0_UART_CTLW0_UCSWRST__0 (0x0000)
3741 #define EUSCI_A0_UART_CTLW0_UCSWRST__1 (0x0001)
3742 #define EUSCI_A0_UART_CTLW0_UCSYNC (0x0100)
3743 #define EUSCI_A0_UART_CTLW0_UCSYNC__0 (0x0000)
3744 #define EUSCI_A0_UART_CTLW0_UCSYNC__1 (0x0100)
3745 #define EUSCI_A0_UART_CTLW0_UCTXADDR (0x0004)
3746 #define EUSCI_A0_UART_CTLW0_UCTXADDR__0 (0x0000)
3747 #define EUSCI_A0_UART_CTLW0_UCTXADDR__1 (0x0004)
3748 #define EUSCI_A0_UART_CTLW0_UCTXBRK (0x0002)
3749 #define EUSCI_A0_UART_CTLW0_UCTXBRK__0 (0x0000)
3750 #define EUSCI_A0_UART_CTLW0_UCTXBRK__1 (0x0002)
3751 #define EUSCI_A0_UART_CTLW1 (HWREG16(0x40001002))
3752 #define EUSCI_A0_UART_CTLW1_UCGLIT__0 (0x0000)
3753 #define EUSCI_A0_UART_CTLW1_UCGLIT__0__2_NS (0x0000)
3754 #define EUSCI_A0_UART_CTLW1_UCGLIT__1 (0x0001)
3755 #define EUSCI_A0_UART_CTLW1_UCGLIT__1__50_NS (0x0001)
3756 #define EUSCI_A0_UART_CTLW1_UCGLIT__2 (0x0002)
3757 #define EUSCI_A0_UART_CTLW1_UCGLIT__2__100_NS (0x0002)
3758 #define EUSCI_A0_UART_CTLW1_UCGLIT__3 (0x0003)
3759 #define EUSCI_A0_UART_CTLW1_UCGLIT__3__200_NS (0x0003)
3760 #define EUSCI_A0_UART_CTLW1_UCGLIT__M (0x0003)
3761 #define EUSCI_A0_UART_IE (HWREG16(0x4000101A))
3762 #define EUSCI_A0_UART_IE_UCRXIE (0x0001)
3763 #define EUSCI_A0_UART_IE_UCRXIE__0 (0x0000)
3764 #define EUSCI_A0_UART_IE_UCRXIE__1 (0x0001)
3765 #define EUSCI_A0_UART_IE_UCSTTIE (0x0004)
3766 #define EUSCI_A0_UART_IE_UCSTTIE__0 (0x0000)
3767 #define EUSCI_A0_UART_IE_UCSTTIE__1 (0x0004)
3768 #define EUSCI_A0_UART_IE_UCTXCPTIE (0x0008)
3769 #define EUSCI_A0_UART_IE_UCTXCPTIE__0 (0x0000)
3770 #define EUSCI_A0_UART_IE_UCTXCPTIE__1 (0x0008)
3771 #define EUSCI_A0_UART_IE_UCTXIE (0x0002)
3772 #define EUSCI_A0_UART_IE_UCTXIE__0 (0x0000)
3773 #define EUSCI_A0_UART_IE_UCTXIE__1 (0x0002)
3774 #define EUSCI_A0_UART_IFG (HWREG16(0x4000101C))
3775 #define EUSCI_A0_UART_IFG_UCRXIFG (0x0001)
3776 #define EUSCI_A0_UART_IFG_UCRXIFG__0 (0x0000)
3777 #define EUSCI_A0_UART_IFG_UCRXIFG__1 (0x0001)
3778 #define EUSCI_A0_UART_IFG_UCSTTIFG (0x0004)
3779 #define EUSCI_A0_UART_IFG_UCSTTIFG__0 (0x0000)
3780 #define EUSCI_A0_UART_IFG_UCSTTIFG__1 (0x0004)
3781 #define EUSCI_A0_UART_IFG_UCTXCPTIFG (0x0008)
3782 #define EUSCI_A0_UART_IFG_UCTXCPTIFG__0 (0x0000)
3783 #define EUSCI_A0_UART_IFG_UCTXCPTIFG__1 (0x0008)
3784 #define EUSCI_A0_UART_IFG_UCTXIFG (0x0002)
3785 #define EUSCI_A0_UART_IFG_UCTXIFG__0 (0x0000)
3786 #define EUSCI_A0_UART_IFG_UCTXIFG__1 (0x0002)
3787 #define EUSCI_A0_UART_IRCTL (HWREG16(0x40001012))
3788 #define EUSCI_A0_UART_IRCTL_UCIREN (0x0001)
3789 #define EUSCI_A0_UART_IRCTL_UCIREN__0 (0x0000)
3790 #define EUSCI_A0_UART_IRCTL_UCIREN__1 (0x0001)
3791 #define EUSCI_A0_UART_IRCTL_UCIRRXFE (0x0100)
3792 #define EUSCI_A0_UART_IRCTL_UCIRRXFE__0 (0x0000)
3793 #define EUSCI_A0_UART_IRCTL_UCIRRXFE__1 (0x0100)
3794 #define EUSCI_A0_UART_IRCTL_UCIRRXFL__M (0xfc00)
3795 #define EUSCI_A0_UART_IRCTL_UCIRRXPL (0x0200)
3796 #define EUSCI_A0_UART_IRCTL_UCIRRXPL__0 (0x0000)
3797 #define EUSCI_A0_UART_IRCTL_UCIRRXPL__1 (0x0200)
3798 #define EUSCI_A0_UART_IRCTL_UCIRTXCLK (0x0002)
3799 #define EUSCI_A0_UART_IRCTL_UCIRTXCLK__0 (0x0000)
3800 #define EUSCI_A0_UART_IRCTL_UCIRTXCLK__0_BRCLK (0x0000)
3801 #define EUSCI_A0_UART_IRCTL_UCIRTXCLK__1 (0x0002)
3802 #define EUSCI_A0_UART_IRCTL_UCIRTXPL__M (0x00fc)
3803 #define EUSCI_A0_UART_IV (HWREG16(0x4000101E))
3804 #define EUSCI_A0_UART_MCTLW (HWREG16(0x40001008))
3805 #define EUSCI_A0_UART_MCTLW_UCBRF__M (0x00f0)
3806 #define EUSCI_A0_UART_MCTLW_UCBRS__M (0xff00)
3807 #define EUSCI_A0_UART_MCTLW_UCOS16 (0x0001)
3808 #define EUSCI_A0_UART_MCTLW_UCOS16__0 (0x0000)
3809 #define EUSCI_A0_UART_MCTLW_UCOS16__0_DISABLED (0x0000)
3810 #define EUSCI_A0_UART_MCTLW_UCOS16__1 (0x0001)
3811 #define EUSCI_A0_UART_MCTLW_UCOS16__1_ENABLED (0x0001)
3812 #define EUSCI_A0_UART_RXBUF (HWREG16(0x4000100C))
3813 #define EUSCI_A0_UART_RXBUF_UCRXBUF__M (0x00ff)
3814 #define EUSCI_A0_UART_STATW (HWREG16(0x4000100A))
3815 #define EUSCI_A0_UART_STATW_UCADDR_UCIDLE (0x0002)
3816 #define EUSCI_A0_UART_STATW_UCADDR_UCIDLE__0 (0x0000)
3817 #define EUSCI_A0_UART_STATW_UCADDR_UCIDLE__1 (0x0002)
3818 #define EUSCI_A0_UART_STATW_UCBRK (0x0008)
3819 #define EUSCI_A0_UART_STATW_UCBRK__0 (0x0000)
3820 #define EUSCI_A0_UART_STATW_UCBRK__1 (0x0008)
3821 #define EUSCI_A0_UART_STATW_UCBUSY (0x0001)
3822 #define EUSCI_A0_UART_STATW_UCBUSY__0 (0x0000)
3823 #define EUSCI_A0_UART_STATW_UCBUSY__1 (0x0001)
3824 #define EUSCI_A0_UART_STATW_UCFE (0x0040)
3825 #define EUSCI_A0_UART_STATW_UCFE__0 (0x0000)
3826 #define EUSCI_A0_UART_STATW_UCFE__0_NO_ERROR (0x0000)
3827 #define EUSCI_A0_UART_STATW_UCFE__1 (0x0040)
3828 #define EUSCI_A0_UART_STATW_UCLISTEN (0x0080)
3829 #define EUSCI_A0_UART_STATW_UCLISTEN__0 (0x0000)
3830 #define EUSCI_A0_UART_STATW_UCLISTEN__0_DISABLED (0x0000)
3831 #define EUSCI_A0_UART_STATW_UCLISTEN__1 (0x0080)
3832 #define EUSCI_A0_UART_STATW_UCOE (0x0020)
3833 #define EUSCI_A0_UART_STATW_UCOE__0 (0x0000)
3834 #define EUSCI_A0_UART_STATW_UCOE__0_NO_ERROR (0x0000)
3835 #define EUSCI_A0_UART_STATW_UCOE__1 (0x0020)
3836 #define EUSCI_A0_UART_STATW_UCPE (0x0010)
3837 #define EUSCI_A0_UART_STATW_UCPE__0 (0x0000)
3838 #define EUSCI_A0_UART_STATW_UCPE__0_NO_ERROR (0x0000)
3839 #define EUSCI_A0_UART_STATW_UCPE__1 (0x0010)
3840 #define EUSCI_A0_UART_STATW_UCRXERR (0x0004)
3841 #define EUSCI_A0_UART_STATW_UCRXERR__0 (0x0000)
3842 #define EUSCI_A0_UART_STATW_UCRXERR__1 (0x0004)
3843 #define EUSCI_A0_UART_TXBUF (HWREG16(0x4000100E))
3844 #define EUSCI_A0_UART_TXBUF_UCTXBUF__M (0x00ff)
3845 #define EUSCI_A1_SPI_BRW (HWREG16(0x40001406))
3846 #define EUSCI_A1_SPI_CTLW0 (HWREG16(0x40001400))
3847 #define EUSCI_A1_SPI_CTLW0_UC7BIT (0x1000)
3848 #define EUSCI_A1_SPI_CTLW0_UC7BIT__0 (0x0000)
3849 #define EUSCI_A1_SPI_CTLW0_UC7BIT__0_8_BIT_DATA (0x0000)
3850 #define EUSCI_A1_SPI_CTLW0_UC7BIT__1 (0x1000)
3851 #define EUSCI_A1_SPI_CTLW0_UC7BIT__1_7_BIT_DATA (0x1000)
3852 #define EUSCI_A1_SPI_CTLW0_UCCKPH (0x8000)
3853 #define EUSCI_A1_SPI_CTLW0_UCCKPH__0 (0x0000)
3854 #define EUSCI_A1_SPI_CTLW0_UCCKPH__1 (0x8000)
3855 #define EUSCI_A1_SPI_CTLW0_UCCKPL (0x4000)
3856 #define EUSCI_A1_SPI_CTLW0_UCCKPL__0 (0x0000)
3857 #define EUSCI_A1_SPI_CTLW0_UCCKPL__1 (0x4000)
3858 #define EUSCI_A1_SPI_CTLW0_UCMODE__0 (0x0000)
3859 #define EUSCI_A1_SPI_CTLW0_UCMODE__0_3_PIN_SPI (0x0000)
3860 #define EUSCI_A1_SPI_CTLW0_UCMODE__1 (0x0200)
3861 #define EUSCI_A1_SPI_CTLW0_UCMODE__2 (0x0400)
3862 #define EUSCI_A1_SPI_CTLW0_UCMODE__3 (0x0600)
3863 #define EUSCI_A1_SPI_CTLW0_UCMODE__3_I2C_MODE (0x0600)
3864 #define EUSCI_A1_SPI_CTLW0_UCMODE__M (0x0600)
3865 #define EUSCI_A1_SPI_CTLW0_UCMSB (0x2000)
3866 #define EUSCI_A1_SPI_CTLW0_UCMSB__0 (0x0000)
3867 #define EUSCI_A1_SPI_CTLW0_UCMSB__0_LSB_FIRST (0x0000)
3868 #define EUSCI_A1_SPI_CTLW0_UCMSB__1 (0x2000)
3869 #define EUSCI_A1_SPI_CTLW0_UCMSB__1_MSB_FIRST (0x2000)
3870 #define EUSCI_A1_SPI_CTLW0_UCMST (0x0800)
3871 #define EUSCI_A1_SPI_CTLW0_UCMST__0 (0x0000)
3872 #define EUSCI_A1_SPI_CTLW0_UCMST__0_SLAVE_MODE (0x0000)
3873 #define EUSCI_A1_SPI_CTLW0_UCMST__1 (0x0800)
3874 #define EUSCI_A1_SPI_CTLW0_UCMST__1_MASTER_MODE (0x0800)
3875 #define EUSCI_A1_SPI_CTLW0_UCSSEL__1 (0x0040)
3876 #define EUSCI_A1_SPI_CTLW0_UCSSEL__1_ACLK (0x0040)
3877 #define EUSCI_A1_SPI_CTLW0_UCSSEL__2 (0x0080)
3878 #define EUSCI_A1_SPI_CTLW0_UCSSEL__2_SMCLK (0x0080)
3879 #define EUSCI_A1_SPI_CTLW0_UCSSEL__3 (0x00c0)
3880 #define EUSCI_A1_SPI_CTLW0_UCSSEL__3_SMCLK (0x00c0)
3881 #define EUSCI_A1_SPI_CTLW0_UCSSEL__M (0x00c0)
3882 #define EUSCI_A1_SPI_CTLW0_UCSTEM (0x0002)
3883 #define EUSCI_A1_SPI_CTLW0_UCSTEM__0 (0x0000)
3884 #define EUSCI_A1_SPI_CTLW0_UCSTEM__1 (0x0002)
3885 #define EUSCI_A1_SPI_CTLW0_UCSWRST (0x0001)
3886 #define EUSCI_A1_SPI_CTLW0_UCSWRST__0 (0x0000)
3887 #define EUSCI_A1_SPI_CTLW0_UCSWRST__1 (0x0001)
3888 #define EUSCI_A1_SPI_CTLW0_UCSYNC (0x0100)
3889 #define EUSCI_A1_SPI_CTLW0_UCSYNC__0 (0x0000)
3890 #define EUSCI_A1_SPI_CTLW0_UCSYNC__1 (0x0100)
3891 #define EUSCI_A1_SPI_IE (HWREG16(0x4000141A))
3892 #define EUSCI_A1_SPI_IE_UCRXIE (0x0001)
3893 #define EUSCI_A1_SPI_IE_UCRXIE__0 (0x0000)
3894 #define EUSCI_A1_SPI_IE_UCRXIE__1 (0x0001)
3895 #define EUSCI_A1_SPI_IE_UCTXIE (0x0002)
3896 #define EUSCI_A1_SPI_IE_UCTXIE__0 (0x0000)
3897 #define EUSCI_A1_SPI_IE_UCTXIE__1 (0x0002)
3898 #define EUSCI_A1_SPI_IFG (HWREG16(0x4000141C))
3899 #define EUSCI_A1_SPI_IFG_UCRXIFG (0x0001)
3900 #define EUSCI_A1_SPI_IFG_UCRXIFG__0 (0x0000)
3901 #define EUSCI_A1_SPI_IFG_UCRXIFG__1 (0x0001)
3902 #define EUSCI_A1_SPI_IFG_UCTXIFG (0x0002)
3903 #define EUSCI_A1_SPI_IFG_UCTXIFG__0 (0x0000)
3904 #define EUSCI_A1_SPI_IFG_UCTXIFG__1 (0x0002)
3905 #define EUSCI_A1_SPI_IV (HWREG16(0x4000141E))
3906 #define EUSCI_A1_SPI_RXBUF (HWREG16(0x4000140C))
3907 #define EUSCI_A1_SPI_RXBUF_UCRXBUF__M (0x00ff)
3908 #define EUSCI_A1_SPI_STATW (HWREG16(0x4000140A))
3909 #define EUSCI_A1_SPI_STATW_UCBUSY (0x0001)
3910 #define EUSCI_A1_SPI_STATW_UCBUSY__0 (0x0000)
3911 #define EUSCI_A1_SPI_STATW_UCBUSY__0_EUSCI_INACTIVE (0x0000)
3912 #define EUSCI_A1_SPI_STATW_UCBUSY__1 (0x0001)
3913 #define EUSCI_A1_SPI_STATW_UCFE (0x0040)
3914 #define EUSCI_A1_SPI_STATW_UCFE__0 (0x0000)
3915 #define EUSCI_A1_SPI_STATW_UCFE__0_NO_ERROR (0x0000)
3916 #define EUSCI_A1_SPI_STATW_UCFE__1 (0x0040)
3917 #define EUSCI_A1_SPI_STATW_UCLISTEN (0x0080)
3918 #define EUSCI_A1_SPI_STATW_UCLISTEN__0 (0x0000)
3919 #define EUSCI_A1_SPI_STATW_UCLISTEN__0_DISABLED (0x0000)
3920 #define EUSCI_A1_SPI_STATW_UCLISTEN__1 (0x0080)
3921 #define EUSCI_A1_SPI_STATW_UCOE (0x0020)
3922 #define EUSCI_A1_SPI_STATW_UCOE__0 (0x0000)
3923 #define EUSCI_A1_SPI_STATW_UCOE__0_NO_ERROR (0x0000)
3924 #define EUSCI_A1_SPI_STATW_UCOE__1 (0x0020)
3925 #define EUSCI_A1_SPI_TXBUF (HWREG16(0x4000140E))
3926 #define EUSCI_A1_SPI_TXBUF_UCTXBUF__M (0x00ff)
3927 #define EUSCI_A1_UART_ABCTL (HWREG16(0x40001410))
3928 #define EUSCI_A1_UART_ABCTL_UCABDEN (0x0001)
3929 #define EUSCI_A1_UART_ABCTL_UCABDEN__0 (0x0000)
3930 #define EUSCI_A1_UART_ABCTL_UCABDEN__1 (0x0001)
3931 #define EUSCI_A1_UART_ABCTL_UCBTOE (0x0004)
3932 #define EUSCI_A1_UART_ABCTL_UCBTOE__0 (0x0000)
3933 #define EUSCI_A1_UART_ABCTL_UCBTOE__0_NO_ERROR (0x0000)
3934 #define EUSCI_A1_UART_ABCTL_UCBTOE__1 (0x0004)
3935 #define EUSCI_A1_UART_ABCTL_UCDELIM__0 (0x0000)
3936 #define EUSCI_A1_UART_ABCTL_UCDELIM__0_1_BIT_TIME (0x0000)
3937 #define EUSCI_A1_UART_ABCTL_UCDELIM__1 (0x0010)
3938 #define EUSCI_A1_UART_ABCTL_UCDELIM__1_2_BIT_TIMES (0x0010)
3939 #define EUSCI_A1_UART_ABCTL_UCDELIM__2 (0x0020)
3940 #define EUSCI_A1_UART_ABCTL_UCDELIM__2_3_BIT_TIMES (0x0020)
3941 #define EUSCI_A1_UART_ABCTL_UCDELIM__3 (0x0030)
3942 #define EUSCI_A1_UART_ABCTL_UCDELIM__3_4_BIT_TIMES (0x0030)
3943 #define EUSCI_A1_UART_ABCTL_UCDELIM__M (0x0030)
3944 #define EUSCI_A1_UART_ABCTL_UCSTOE (0x0008)
3945 #define EUSCI_A1_UART_ABCTL_UCSTOE__0 (0x0000)
3946 #define EUSCI_A1_UART_ABCTL_UCSTOE__0_NO_ERROR (0x0000)
3947 #define EUSCI_A1_UART_ABCTL_UCSTOE__1 (0x0008)
3948 #define EUSCI_A1_UART_BRW (HWREG16(0x40001406))
3949 #define EUSCI_A1_UART_CTLW0 (HWREG16(0x40001400))
3950 #define EUSCI_A1_UART_CTLW0_UC7BIT (0x1000)
3951 #define EUSCI_A1_UART_CTLW0_UC7BIT__0 (0x0000)
3952 #define EUSCI_A1_UART_CTLW0_UC7BIT__0_8_BIT_DATA (0x0000)
3953 #define EUSCI_A1_UART_CTLW0_UC7BIT__1 (0x1000)
3954 #define EUSCI_A1_UART_CTLW0_UC7BIT__1_7_BIT_DATA (0x1000)
3955 #define EUSCI_A1_UART_CTLW0_UCBRKIE (0x0010)
3956 #define EUSCI_A1_UART_CTLW0_UCBRKIE__0 (0x0000)
3957 #define EUSCI_A1_UART_CTLW0_UCBRKIE__1 (0x0010)
3958 #define EUSCI_A1_UART_CTLW0_UCDORM (0x0008)
3959 #define EUSCI_A1_UART_CTLW0_UCDORM__0 (0x0000)
3960 #define EUSCI_A1_UART_CTLW0_UCDORM__1 (0x0008)
3961 #define EUSCI_A1_UART_CTLW0_UCMODE__0 (0x0000)
3962 #define EUSCI_A1_UART_CTLW0_UCMODE__0_UART_MODE (0x0000)
3963 #define EUSCI_A1_UART_CTLW0_UCMODE__1 (0x0200)
3964 #define EUSCI_A1_UART_CTLW0_UCMODE__2 (0x0400)
3965 #define EUSCI_A1_UART_CTLW0_UCMODE__3 (0x0600)
3966 #define EUSCI_A1_UART_CTLW0_UCMODE__M (0x0600)
3967 #define EUSCI_A1_UART_CTLW0_UCMSB (0x2000)
3968 #define EUSCI_A1_UART_CTLW0_UCMSB__0 (0x0000)
3969 #define EUSCI_A1_UART_CTLW0_UCMSB__0_LSB_FIRST (0x0000)
3970 #define EUSCI_A1_UART_CTLW0_UCMSB__1 (0x2000)
3971 #define EUSCI_A1_UART_CTLW0_UCMSB__1_MSB_FIRST (0x2000)
3972 #define EUSCI_A1_UART_CTLW0_UCPAR (0x4000)
3973 #define EUSCI_A1_UART_CTLW0_UCPAR__0 (0x0000)
3974 #define EUSCI_A1_UART_CTLW0_UCPAR__0_ODD_PARITY (0x0000)
3975 #define EUSCI_A1_UART_CTLW0_UCPAR__1 (0x4000)
3976 #define EUSCI_A1_UART_CTLW0_UCPAR__1_EVEN_PARITY (0x4000)
3977 #define EUSCI_A1_UART_CTLW0_UCPEN (0x8000)
3978 #define EUSCI_A1_UART_CTLW0_UCPEN__0 (0x0000)
3979 #define EUSCI_A1_UART_CTLW0_UCPEN__0_PARITY_DISABLED (0x0000)
3980 #define EUSCI_A1_UART_CTLW0_UCPEN__1 (0x8000)
3981 #define EUSCI_A1_UART_CTLW0_UCRXEIE (0x0020)
3982 #define EUSCI_A1_UART_CTLW0_UCRXEIE__0 (0x0000)
3983 #define EUSCI_A1_UART_CTLW0_UCRXEIE__1 (0x0020)
3984 #define EUSCI_A1_UART_CTLW0_UCSPB (0x0800)
3985 #define EUSCI_A1_UART_CTLW0_UCSPB__0 (0x0000)
3986 #define EUSCI_A1_UART_CTLW0_UCSPB__0_ONE_STOP_BIT (0x0000)
3987 #define EUSCI_A1_UART_CTLW0_UCSPB__1 (0x0800)
3988 #define EUSCI_A1_UART_CTLW0_UCSPB__1_TWO_STOP_BITS (0x0800)
3989 #define EUSCI_A1_UART_CTLW0_UCSSEL__0 (0x0000)
3990 #define EUSCI_A1_UART_CTLW0_UCSSEL__0_UCLK (0x0000)
3991 #define EUSCI_A1_UART_CTLW0_UCSSEL__1 (0x0040)
3992 #define EUSCI_A1_UART_CTLW0_UCSSEL__1_ACLK (0x0040)
3993 #define EUSCI_A1_UART_CTLW0_UCSSEL__2 (0x0080)
3994 #define EUSCI_A1_UART_CTLW0_UCSSEL__2_SMCLK (0x0080)
3995 #define EUSCI_A1_UART_CTLW0_UCSSEL__3 (0x00c0)
3996 #define EUSCI_A1_UART_CTLW0_UCSSEL__3_SMCLK (0x00c0)
3997 #define EUSCI_A1_UART_CTLW0_UCSSEL__M (0x00c0)
3998 #define EUSCI_A1_UART_CTLW0_UCSWRST (0x0001)
3999 #define EUSCI_A1_UART_CTLW0_UCSWRST__0 (0x0000)
4000 #define EUSCI_A1_UART_CTLW0_UCSWRST__1 (0x0001)
4001 #define EUSCI_A1_UART_CTLW0_UCSYNC (0x0100)
4002 #define EUSCI_A1_UART_CTLW0_UCSYNC__0 (0x0000)
4003 #define EUSCI_A1_UART_CTLW0_UCSYNC__1 (0x0100)
4004 #define EUSCI_A1_UART_CTLW0_UCTXADDR (0x0004)
4005 #define EUSCI_A1_UART_CTLW0_UCTXADDR__0 (0x0000)
4006 #define EUSCI_A1_UART_CTLW0_UCTXADDR__1 (0x0004)
4007 #define EUSCI_A1_UART_CTLW0_UCTXBRK (0x0002)
4008 #define EUSCI_A1_UART_CTLW0_UCTXBRK__0 (0x0000)
4009 #define EUSCI_A1_UART_CTLW0_UCTXBRK__1 (0x0002)
4010 #define EUSCI_A1_UART_CTLW1 (HWREG16(0x40001402))
4011 #define EUSCI_A1_UART_CTLW1_UCGLIT__0 (0x0000)
4012 #define EUSCI_A1_UART_CTLW1_UCGLIT__0__2_NS (0x0000)
4013 #define EUSCI_A1_UART_CTLW1_UCGLIT__1 (0x0001)
4014 #define EUSCI_A1_UART_CTLW1_UCGLIT__1__50_NS (0x0001)
4015 #define EUSCI_A1_UART_CTLW1_UCGLIT__2 (0x0002)
4016 #define EUSCI_A1_UART_CTLW1_UCGLIT__2__100_NS (0x0002)
4017 #define EUSCI_A1_UART_CTLW1_UCGLIT__3 (0x0003)
4018 #define EUSCI_A1_UART_CTLW1_UCGLIT__3__200_NS (0x0003)
4019 #define EUSCI_A1_UART_CTLW1_UCGLIT__M (0x0003)
4020 #define EUSCI_A1_UART_IE (HWREG16(0x4000141A))
4021 #define EUSCI_A1_UART_IE_UCRXIE (0x0001)
4022 #define EUSCI_A1_UART_IE_UCRXIE__0 (0x0000)
4023 #define EUSCI_A1_UART_IE_UCRXIE__1 (0x0001)
4024 #define EUSCI_A1_UART_IE_UCSTTIE (0x0004)
4025 #define EUSCI_A1_UART_IE_UCSTTIE__0 (0x0000)
4026 #define EUSCI_A1_UART_IE_UCSTTIE__1 (0x0004)
4027 #define EUSCI_A1_UART_IE_UCTXCPTIE (0x0008)
4028 #define EUSCI_A1_UART_IE_UCTXCPTIE__0 (0x0000)
4029 #define EUSCI_A1_UART_IE_UCTXCPTIE__1 (0x0008)
4030 #define EUSCI_A1_UART_IE_UCTXIE (0x0002)
4031 #define EUSCI_A1_UART_IE_UCTXIE__0 (0x0000)
4032 #define EUSCI_A1_UART_IE_UCTXIE__1 (0x0002)
4033 #define EUSCI_A1_UART_IFG (HWREG16(0x4000141C))
4034 #define EUSCI_A1_UART_IFG_UCRXIFG (0x0001)
4035 #define EUSCI_A1_UART_IFG_UCRXIFG__0 (0x0000)
4036 #define EUSCI_A1_UART_IFG_UCRXIFG__1 (0x0001)
4037 #define EUSCI_A1_UART_IFG_UCSTTIFG (0x0004)
4038 #define EUSCI_A1_UART_IFG_UCSTTIFG__0 (0x0000)
4039 #define EUSCI_A1_UART_IFG_UCSTTIFG__1 (0x0004)
4040 #define EUSCI_A1_UART_IFG_UCTXCPTIFG (0x0008)
4041 #define EUSCI_A1_UART_IFG_UCTXCPTIFG__0 (0x0000)
4042 #define EUSCI_A1_UART_IFG_UCTXCPTIFG__1 (0x0008)
4043 #define EUSCI_A1_UART_IFG_UCTXIFG (0x0002)
4044 #define EUSCI_A1_UART_IFG_UCTXIFG__0 (0x0000)
4045 #define EUSCI_A1_UART_IFG_UCTXIFG__1 (0x0002)
4046 #define EUSCI_A1_UART_IRCTL (HWREG16(0x40001412))
4047 #define EUSCI_A1_UART_IRCTL_UCIREN (0x0001)
4048 #define EUSCI_A1_UART_IRCTL_UCIREN__0 (0x0000)
4049 #define EUSCI_A1_UART_IRCTL_UCIREN__1 (0x0001)
4050 #define EUSCI_A1_UART_IRCTL_UCIRRXFE (0x0100)
4051 #define EUSCI_A1_UART_IRCTL_UCIRRXFE__0 (0x0000)
4052 #define EUSCI_A1_UART_IRCTL_UCIRRXFE__1 (0x0100)
4053 #define EUSCI_A1_UART_IRCTL_UCIRRXFL__M (0xfc00)
4054 #define EUSCI_A1_UART_IRCTL_UCIRRXPL (0x0200)
4055 #define EUSCI_A1_UART_IRCTL_UCIRRXPL__0 (0x0000)
4056 #define EUSCI_A1_UART_IRCTL_UCIRRXPL__1 (0x0200)
4057 #define EUSCI_A1_UART_IRCTL_UCIRTXCLK (0x0002)
4058 #define EUSCI_A1_UART_IRCTL_UCIRTXCLK__0 (0x0000)
4059 #define EUSCI_A1_UART_IRCTL_UCIRTXCLK__0_BRCLK (0x0000)
4060 #define EUSCI_A1_UART_IRCTL_UCIRTXCLK__1 (0x0002)
4061 #define EUSCI_A1_UART_IRCTL_UCIRTXPL__M (0x00fc)
4062 #define EUSCI_A1_UART_IV (HWREG16(0x4000141E))
4063 #define EUSCI_A1_UART_MCTLW (HWREG16(0x40001408))
4064 #define EUSCI_A1_UART_MCTLW_UCBRF__M (0x00f0)
4065 #define EUSCI_A1_UART_MCTLW_UCBRS__M (0xff00)
4066 #define EUSCI_A1_UART_MCTLW_UCOS16 (0x0001)
4067 #define EUSCI_A1_UART_MCTLW_UCOS16__0 (0x0000)
4068 #define EUSCI_A1_UART_MCTLW_UCOS16__0_DISABLED (0x0000)
4069 #define EUSCI_A1_UART_MCTLW_UCOS16__1 (0x0001)
4070 #define EUSCI_A1_UART_MCTLW_UCOS16__1_ENABLED (0x0001)
4071 #define EUSCI_A1_UART_RXBUF (HWREG16(0x4000140C))
4072 #define EUSCI_A1_UART_RXBUF_UCRXBUF__M (0x00ff)
4073 #define EUSCI_A1_UART_STATW (HWREG16(0x4000140A))
4074 #define EUSCI_A1_UART_STATW_UCADDR_UCIDLE (0x0002)
4075 #define EUSCI_A1_UART_STATW_UCADDR_UCIDLE__0 (0x0000)
4076 #define EUSCI_A1_UART_STATW_UCADDR_UCIDLE__1 (0x0002)
4077 #define EUSCI_A1_UART_STATW_UCBRK (0x0008)
4078 #define EUSCI_A1_UART_STATW_UCBRK__0 (0x0000)
4079 #define EUSCI_A1_UART_STATW_UCBRK__1 (0x0008)
4080 #define EUSCI_A1_UART_STATW_UCBUSY (0x0001)
4081 #define EUSCI_A1_UART_STATW_UCBUSY__0 (0x0000)
4082 #define EUSCI_A1_UART_STATW_UCBUSY__1 (0x0001)
4083 #define EUSCI_A1_UART_STATW_UCFE (0x0040)
4084 #define EUSCI_A1_UART_STATW_UCFE__0 (0x0000)
4085 #define EUSCI_A1_UART_STATW_UCFE__0_NO_ERROR (0x0000)
4086 #define EUSCI_A1_UART_STATW_UCFE__1 (0x0040)
4087 #define EUSCI_A1_UART_STATW_UCLISTEN (0x0080)
4088 #define EUSCI_A1_UART_STATW_UCLISTEN__0 (0x0000)
4089 #define EUSCI_A1_UART_STATW_UCLISTEN__0_DISABLED (0x0000)
4090 #define EUSCI_A1_UART_STATW_UCLISTEN__1 (0x0080)
4091 #define EUSCI_A1_UART_STATW_UCOE (0x0020)
4092 #define EUSCI_A1_UART_STATW_UCOE__0 (0x0000)
4093 #define EUSCI_A1_UART_STATW_UCOE__0_NO_ERROR (0x0000)
4094 #define EUSCI_A1_UART_STATW_UCOE__1 (0x0020)
4095 #define EUSCI_A1_UART_STATW_UCPE (0x0010)
4096 #define EUSCI_A1_UART_STATW_UCPE__0 (0x0000)
4097 #define EUSCI_A1_UART_STATW_UCPE__0_NO_ERROR (0x0000)
4098 #define EUSCI_A1_UART_STATW_UCPE__1 (0x0010)
4099 #define EUSCI_A1_UART_STATW_UCRXERR (0x0004)
4100 #define EUSCI_A1_UART_STATW_UCRXERR__0 (0x0000)
4101 #define EUSCI_A1_UART_STATW_UCRXERR__1 (0x0004)
4102 #define EUSCI_A1_UART_TXBUF (HWREG16(0x4000140E))
4103 #define EUSCI_A1_UART_TXBUF_UCTXBUF__M (0x00ff)
4104 #define EUSCI_A2_SPI_BRW (HWREG16(0x40001806))
4105 #define EUSCI_A2_SPI_CTLW0 (HWREG16(0x40001800))
4106 #define EUSCI_A2_SPI_CTLW0_UC7BIT (0x1000)
4107 #define EUSCI_A2_SPI_CTLW0_UC7BIT__0 (0x0000)
4108 #define EUSCI_A2_SPI_CTLW0_UC7BIT__0_8_BIT_DATA (0x0000)
4109 #define EUSCI_A2_SPI_CTLW0_UC7BIT__1 (0x1000)
4110 #define EUSCI_A2_SPI_CTLW0_UC7BIT__1_7_BIT_DATA (0x1000)
4111 #define EUSCI_A2_SPI_CTLW0_UCCKPH (0x8000)
4112 #define EUSCI_A2_SPI_CTLW0_UCCKPH__0 (0x0000)
4113 #define EUSCI_A2_SPI_CTLW0_UCCKPH__1 (0x8000)
4114 #define EUSCI_A2_SPI_CTLW0_UCCKPL (0x4000)
4115 #define EUSCI_A2_SPI_CTLW0_UCCKPL__0 (0x0000)
4116 #define EUSCI_A2_SPI_CTLW0_UCCKPL__1 (0x4000)
4117 #define EUSCI_A2_SPI_CTLW0_UCMODE__0 (0x0000)
4118 #define EUSCI_A2_SPI_CTLW0_UCMODE__0_3_PIN_SPI (0x0000)
4119 #define EUSCI_A2_SPI_CTLW0_UCMODE__1 (0x0200)
4120 #define EUSCI_A2_SPI_CTLW0_UCMODE__2 (0x0400)
4121 #define EUSCI_A2_SPI_CTLW0_UCMODE__3 (0x0600)
4122 #define EUSCI_A2_SPI_CTLW0_UCMODE__3_I2C_MODE (0x0600)
4123 #define EUSCI_A2_SPI_CTLW0_UCMODE__M (0x0600)
4124 #define EUSCI_A2_SPI_CTLW0_UCMSB (0x2000)
4125 #define EUSCI_A2_SPI_CTLW0_UCMSB__0 (0x0000)
4126 #define EUSCI_A2_SPI_CTLW0_UCMSB__0_LSB_FIRST (0x0000)
4127 #define EUSCI_A2_SPI_CTLW0_UCMSB__1 (0x2000)
4128 #define EUSCI_A2_SPI_CTLW0_UCMSB__1_MSB_FIRST (0x2000)
4129 #define EUSCI_A2_SPI_CTLW0_UCMST (0x0800)
4130 #define EUSCI_A2_SPI_CTLW0_UCMST__0 (0x0000)
4131 #define EUSCI_A2_SPI_CTLW0_UCMST__0_SLAVE_MODE (0x0000)
4132 #define EUSCI_A2_SPI_CTLW0_UCMST__1 (0x0800)
4133 #define EUSCI_A2_SPI_CTLW0_UCMST__1_MASTER_MODE (0x0800)
4134 #define EUSCI_A2_SPI_CTLW0_UCSSEL__1 (0x0040)
4135 #define EUSCI_A2_SPI_CTLW0_UCSSEL__1_ACLK (0x0040)
4136 #define EUSCI_A2_SPI_CTLW0_UCSSEL__2 (0x0080)
4137 #define EUSCI_A2_SPI_CTLW0_UCSSEL__2_SMCLK (0x0080)
4138 #define EUSCI_A2_SPI_CTLW0_UCSSEL__3 (0x00c0)
4139 #define EUSCI_A2_SPI_CTLW0_UCSSEL__3_SMCLK (0x00c0)
4140 #define EUSCI_A2_SPI_CTLW0_UCSSEL__M (0x00c0)
4141 #define EUSCI_A2_SPI_CTLW0_UCSTEM (0x0002)
4142 #define EUSCI_A2_SPI_CTLW0_UCSTEM__0 (0x0000)
4143 #define EUSCI_A2_SPI_CTLW0_UCSTEM__1 (0x0002)
4144 #define EUSCI_A2_SPI_CTLW0_UCSWRST (0x0001)
4145 #define EUSCI_A2_SPI_CTLW0_UCSWRST__0 (0x0000)
4146 #define EUSCI_A2_SPI_CTLW0_UCSWRST__1 (0x0001)
4147 #define EUSCI_A2_SPI_CTLW0_UCSYNC (0x0100)
4148 #define EUSCI_A2_SPI_CTLW0_UCSYNC__0 (0x0000)
4149 #define EUSCI_A2_SPI_CTLW0_UCSYNC__1 (0x0100)
4150 #define EUSCI_A2_SPI_IE (HWREG16(0x4000181A))
4151 #define EUSCI_A2_SPI_IE_UCRXIE (0x0001)
4152 #define EUSCI_A2_SPI_IE_UCRXIE__0 (0x0000)
4153 #define EUSCI_A2_SPI_IE_UCRXIE__1 (0x0001)
4154 #define EUSCI_A2_SPI_IE_UCTXIE (0x0002)
4155 #define EUSCI_A2_SPI_IE_UCTXIE__0 (0x0000)
4156 #define EUSCI_A2_SPI_IE_UCTXIE__1 (0x0002)
4157 #define EUSCI_A2_SPI_IFG (HWREG16(0x4000181C))
4158 #define EUSCI_A2_SPI_IFG_UCRXIFG (0x0001)
4159 #define EUSCI_A2_SPI_IFG_UCRXIFG__0 (0x0000)
4160 #define EUSCI_A2_SPI_IFG_UCRXIFG__1 (0x0001)
4161 #define EUSCI_A2_SPI_IFG_UCTXIFG (0x0002)
4162 #define EUSCI_A2_SPI_IFG_UCTXIFG__0 (0x0000)
4163 #define EUSCI_A2_SPI_IFG_UCTXIFG__1 (0x0002)
4164 #define EUSCI_A2_SPI_IV (HWREG16(0x4000181E))
4165 #define EUSCI_A2_SPI_RXBUF (HWREG16(0x4000180C))
4166 #define EUSCI_A2_SPI_RXBUF_UCRXBUF__M (0x00ff)
4167 #define EUSCI_A2_SPI_STATW (HWREG16(0x4000180A))
4168 #define EUSCI_A2_SPI_STATW_UCBUSY (0x0001)
4169 #define EUSCI_A2_SPI_STATW_UCBUSY__0 (0x0000)
4170 #define EUSCI_A2_SPI_STATW_UCBUSY__0_EUSCI_INACTIVE (0x0000)
4171 #define EUSCI_A2_SPI_STATW_UCBUSY__1 (0x0001)
4172 #define EUSCI_A2_SPI_STATW_UCFE (0x0040)
4173 #define EUSCI_A2_SPI_STATW_UCFE__0 (0x0000)
4174 #define EUSCI_A2_SPI_STATW_UCFE__0_NO_ERROR (0x0000)
4175 #define EUSCI_A2_SPI_STATW_UCFE__1 (0x0040)
4176 #define EUSCI_A2_SPI_STATW_UCLISTEN (0x0080)
4177 #define EUSCI_A2_SPI_STATW_UCLISTEN__0 (0x0000)
4178 #define EUSCI_A2_SPI_STATW_UCLISTEN__0_DISABLED (0x0000)
4179 #define EUSCI_A2_SPI_STATW_UCLISTEN__1 (0x0080)
4180 #define EUSCI_A2_SPI_STATW_UCOE (0x0020)
4181 #define EUSCI_A2_SPI_STATW_UCOE__0 (0x0000)
4182 #define EUSCI_A2_SPI_STATW_UCOE__0_NO_ERROR (0x0000)
4183 #define EUSCI_A2_SPI_STATW_UCOE__1 (0x0020)
4184 #define EUSCI_A2_SPI_TXBUF (HWREG16(0x4000180E))
4185 #define EUSCI_A2_SPI_TXBUF_UCTXBUF__M (0x00ff)
4186 #define EUSCI_A2_UART_ABCTL (HWREG16(0x40001810))
4187 #define EUSCI_A2_UART_ABCTL_UCABDEN (0x0001)
4188 #define EUSCI_A2_UART_ABCTL_UCABDEN__0 (0x0000)
4189 #define EUSCI_A2_UART_ABCTL_UCABDEN__1 (0x0001)
4190 #define EUSCI_A2_UART_ABCTL_UCBTOE (0x0004)
4191 #define EUSCI_A2_UART_ABCTL_UCBTOE__0 (0x0000)
4192 #define EUSCI_A2_UART_ABCTL_UCBTOE__0_NO_ERROR (0x0000)
4193 #define EUSCI_A2_UART_ABCTL_UCBTOE__1 (0x0004)
4194 #define EUSCI_A2_UART_ABCTL_UCDELIM__0 (0x0000)
4195 #define EUSCI_A2_UART_ABCTL_UCDELIM__0_1_BIT_TIME (0x0000)
4196 #define EUSCI_A2_UART_ABCTL_UCDELIM__1 (0x0010)
4197 #define EUSCI_A2_UART_ABCTL_UCDELIM__1_2_BIT_TIMES (0x0010)
4198 #define EUSCI_A2_UART_ABCTL_UCDELIM__2 (0x0020)
4199 #define EUSCI_A2_UART_ABCTL_UCDELIM__2_3_BIT_TIMES (0x0020)
4200 #define EUSCI_A2_UART_ABCTL_UCDELIM__3 (0x0030)
4201 #define EUSCI_A2_UART_ABCTL_UCDELIM__3_4_BIT_TIMES (0x0030)
4202 #define EUSCI_A2_UART_ABCTL_UCDELIM__M (0x0030)
4203 #define EUSCI_A2_UART_ABCTL_UCSTOE (0x0008)
4204 #define EUSCI_A2_UART_ABCTL_UCSTOE__0 (0x0000)
4205 #define EUSCI_A2_UART_ABCTL_UCSTOE__0_NO_ERROR (0x0000)
4206 #define EUSCI_A2_UART_ABCTL_UCSTOE__1 (0x0008)
4207 #define EUSCI_A2_UART_BRW (HWREG16(0x40001806))
4208 #define EUSCI_A2_UART_CTLW0 (HWREG16(0x40001800))
4209 #define EUSCI_A2_UART_CTLW0_UC7BIT (0x1000)
4210 #define EUSCI_A2_UART_CTLW0_UC7BIT__0 (0x0000)
4211 #define EUSCI_A2_UART_CTLW0_UC7BIT__0_8_BIT_DATA (0x0000)
4212 #define EUSCI_A2_UART_CTLW0_UC7BIT__1 (0x1000)
4213 #define EUSCI_A2_UART_CTLW0_UC7BIT__1_7_BIT_DATA (0x1000)
4214 #define EUSCI_A2_UART_CTLW0_UCBRKIE (0x0010)
4215 #define EUSCI_A2_UART_CTLW0_UCBRKIE__0 (0x0000)
4216 #define EUSCI_A2_UART_CTLW0_UCBRKIE__1 (0x0010)
4217 #define EUSCI_A2_UART_CTLW0_UCDORM (0x0008)
4218 #define EUSCI_A2_UART_CTLW0_UCDORM__0 (0x0000)
4219 #define EUSCI_A2_UART_CTLW0_UCDORM__1 (0x0008)
4220 #define EUSCI_A2_UART_CTLW0_UCMODE__0 (0x0000)
4221 #define EUSCI_A2_UART_CTLW0_UCMODE__0_UART_MODE (0x0000)
4222 #define EUSCI_A2_UART_CTLW0_UCMODE__1 (0x0200)
4223 #define EUSCI_A2_UART_CTLW0_UCMODE__2 (0x0400)
4224 #define EUSCI_A2_UART_CTLW0_UCMODE__3 (0x0600)
4225 #define EUSCI_A2_UART_CTLW0_UCMODE__M (0x0600)
4226 #define EUSCI_A2_UART_CTLW0_UCMSB (0x2000)
4227 #define EUSCI_A2_UART_CTLW0_UCMSB__0 (0x0000)
4228 #define EUSCI_A2_UART_CTLW0_UCMSB__0_LSB_FIRST (0x0000)
4229 #define EUSCI_A2_UART_CTLW0_UCMSB__1 (0x2000)
4230 #define EUSCI_A2_UART_CTLW0_UCMSB__1_MSB_FIRST (0x2000)
4231 #define EUSCI_A2_UART_CTLW0_UCPAR (0x4000)
4232 #define EUSCI_A2_UART_CTLW0_UCPAR__0 (0x0000)
4233 #define EUSCI_A2_UART_CTLW0_UCPAR__0_ODD_PARITY (0x0000)
4234 #define EUSCI_A2_UART_CTLW0_UCPAR__1 (0x4000)
4235 #define EUSCI_A2_UART_CTLW0_UCPAR__1_EVEN_PARITY (0x4000)
4236 #define EUSCI_A2_UART_CTLW0_UCPEN (0x8000)
4237 #define EUSCI_A2_UART_CTLW0_UCPEN__0 (0x0000)
4238 #define EUSCI_A2_UART_CTLW0_UCPEN__0_PARITY_DISABLED (0x0000)
4239 #define EUSCI_A2_UART_CTLW0_UCPEN__1 (0x8000)
4240 #define EUSCI_A2_UART_CTLW0_UCRXEIE (0x0020)
4241 #define EUSCI_A2_UART_CTLW0_UCRXEIE__0 (0x0000)
4242 #define EUSCI_A2_UART_CTLW0_UCRXEIE__1 (0x0020)
4243 #define EUSCI_A2_UART_CTLW0_UCSPB (0x0800)
4244 #define EUSCI_A2_UART_CTLW0_UCSPB__0 (0x0000)
4245 #define EUSCI_A2_UART_CTLW0_UCSPB__0_ONE_STOP_BIT (0x0000)
4246 #define EUSCI_A2_UART_CTLW0_UCSPB__1 (0x0800)
4247 #define EUSCI_A2_UART_CTLW0_UCSPB__1_TWO_STOP_BITS (0x0800)
4248 #define EUSCI_A2_UART_CTLW0_UCSSEL__0 (0x0000)
4249 #define EUSCI_A2_UART_CTLW0_UCSSEL__0_UCLK (0x0000)
4250 #define EUSCI_A2_UART_CTLW0_UCSSEL__1 (0x0040)
4251 #define EUSCI_A2_UART_CTLW0_UCSSEL__1_ACLK (0x0040)
4252 #define EUSCI_A2_UART_CTLW0_UCSSEL__2 (0x0080)
4253 #define EUSCI_A2_UART_CTLW0_UCSSEL__2_SMCLK (0x0080)
4254 #define EUSCI_A2_UART_CTLW0_UCSSEL__3 (0x00c0)
4255 #define EUSCI_A2_UART_CTLW0_UCSSEL__3_SMCLK (0x00c0)
4256 #define EUSCI_A2_UART_CTLW0_UCSSEL__M (0x00c0)
4257 #define EUSCI_A2_UART_CTLW0_UCSWRST (0x0001)
4258 #define EUSCI_A2_UART_CTLW0_UCSWRST__0 (0x0000)
4259 #define EUSCI_A2_UART_CTLW0_UCSWRST__1 (0x0001)
4260 #define EUSCI_A2_UART_CTLW0_UCSYNC (0x0100)
4261 #define EUSCI_A2_UART_CTLW0_UCSYNC__0 (0x0000)
4262 #define EUSCI_A2_UART_CTLW0_UCSYNC__1 (0x0100)
4263 #define EUSCI_A2_UART_CTLW0_UCTXADDR (0x0004)
4264 #define EUSCI_A2_UART_CTLW0_UCTXADDR__0 (0x0000)
4265 #define EUSCI_A2_UART_CTLW0_UCTXADDR__1 (0x0004)
4266 #define EUSCI_A2_UART_CTLW0_UCTXBRK (0x0002)
4267 #define EUSCI_A2_UART_CTLW0_UCTXBRK__0 (0x0000)
4268 #define EUSCI_A2_UART_CTLW0_UCTXBRK__1 (0x0002)
4269 #define EUSCI_A2_UART_CTLW1 (HWREG16(0x40001802))
4270 #define EUSCI_A2_UART_CTLW1_UCGLIT__0 (0x0000)
4271 #define EUSCI_A2_UART_CTLW1_UCGLIT__0__2_NS (0x0000)
4272 #define EUSCI_A2_UART_CTLW1_UCGLIT__1 (0x0001)
4273 #define EUSCI_A2_UART_CTLW1_UCGLIT__1__50_NS (0x0001)
4274 #define EUSCI_A2_UART_CTLW1_UCGLIT__2 (0x0002)
4275 #define EUSCI_A2_UART_CTLW1_UCGLIT__2__100_NS (0x0002)
4276 #define EUSCI_A2_UART_CTLW1_UCGLIT__3 (0x0003)
4277 #define EUSCI_A2_UART_CTLW1_UCGLIT__3__200_NS (0x0003)
4278 #define EUSCI_A2_UART_CTLW1_UCGLIT__M (0x0003)
4279 #define EUSCI_A2_UART_IE (HWREG16(0x4000181A))
4280 #define EUSCI_A2_UART_IE_UCRXIE (0x0001)
4281 #define EUSCI_A2_UART_IE_UCRXIE__0 (0x0000)
4282 #define EUSCI_A2_UART_IE_UCRXIE__1 (0x0001)
4283 #define EUSCI_A2_UART_IE_UCSTTIE (0x0004)
4284 #define EUSCI_A2_UART_IE_UCSTTIE__0 (0x0000)
4285 #define EUSCI_A2_UART_IE_UCSTTIE__1 (0x0004)
4286 #define EUSCI_A2_UART_IE_UCTXCPTIE (0x0008)
4287 #define EUSCI_A2_UART_IE_UCTXCPTIE__0 (0x0000)
4288 #define EUSCI_A2_UART_IE_UCTXCPTIE__1 (0x0008)
4289 #define EUSCI_A2_UART_IE_UCTXIE (0x0002)
4290 #define EUSCI_A2_UART_IE_UCTXIE__0 (0x0000)
4291 #define EUSCI_A2_UART_IE_UCTXIE__1 (0x0002)
4292 #define EUSCI_A2_UART_IFG (HWREG16(0x4000181C))
4293 #define EUSCI_A2_UART_IFG_UCRXIFG (0x0001)
4294 #define EUSCI_A2_UART_IFG_UCRXIFG__0 (0x0000)
4295 #define EUSCI_A2_UART_IFG_UCRXIFG__1 (0x0001)
4296 #define EUSCI_A2_UART_IFG_UCSTTIFG (0x0004)
4297 #define EUSCI_A2_UART_IFG_UCSTTIFG__0 (0x0000)
4298 #define EUSCI_A2_UART_IFG_UCSTTIFG__1 (0x0004)
4299 #define EUSCI_A2_UART_IFG_UCTXCPTIFG (0x0008)
4300 #define EUSCI_A2_UART_IFG_UCTXCPTIFG__0 (0x0000)
4301 #define EUSCI_A2_UART_IFG_UCTXCPTIFG__1 (0x0008)
4302 #define EUSCI_A2_UART_IFG_UCTXIFG (0x0002)
4303 #define EUSCI_A2_UART_IFG_UCTXIFG__0 (0x0000)
4304 #define EUSCI_A2_UART_IFG_UCTXIFG__1 (0x0002)
4305 #define EUSCI_A2_UART_IRCTL (HWREG16(0x40001812))
4306 #define EUSCI_A2_UART_IRCTL_UCIREN (0x0001)
4307 #define EUSCI_A2_UART_IRCTL_UCIREN__0 (0x0000)
4308 #define EUSCI_A2_UART_IRCTL_UCIREN__1 (0x0001)
4309 #define EUSCI_A2_UART_IRCTL_UCIRRXFE (0x0100)
4310 #define EUSCI_A2_UART_IRCTL_UCIRRXFE__0 (0x0000)
4311 #define EUSCI_A2_UART_IRCTL_UCIRRXFE__1 (0x0100)
4312 #define EUSCI_A2_UART_IRCTL_UCIRRXFL__M (0xfc00)
4313 #define EUSCI_A2_UART_IRCTL_UCIRRXPL (0x0200)
4314 #define EUSCI_A2_UART_IRCTL_UCIRRXPL__0 (0x0000)
4315 #define EUSCI_A2_UART_IRCTL_UCIRRXPL__1 (0x0200)
4316 #define EUSCI_A2_UART_IRCTL_UCIRTXCLK (0x0002)
4317 #define EUSCI_A2_UART_IRCTL_UCIRTXCLK__0 (0x0000)
4318 #define EUSCI_A2_UART_IRCTL_UCIRTXCLK__0_BRCLK (0x0000)
4319 #define EUSCI_A2_UART_IRCTL_UCIRTXCLK__1 (0x0002)
4320 #define EUSCI_A2_UART_IRCTL_UCIRTXPL__M (0x00fc)
4321 #define EUSCI_A2_UART_IV (HWREG16(0x4000181E))
4322 #define EUSCI_A2_UART_MCTLW (HWREG16(0x40001808))
4323 #define EUSCI_A2_UART_MCTLW_UCBRF__M (0x00f0)
4324 #define EUSCI_A2_UART_MCTLW_UCBRS__M (0xff00)
4325 #define EUSCI_A2_UART_MCTLW_UCOS16 (0x0001)
4326 #define EUSCI_A2_UART_MCTLW_UCOS16__0 (0x0000)
4327 #define EUSCI_A2_UART_MCTLW_UCOS16__0_DISABLED (0x0000)
4328 #define EUSCI_A2_UART_MCTLW_UCOS16__1 (0x0001)
4329 #define EUSCI_A2_UART_MCTLW_UCOS16__1_ENABLED (0x0001)
4330 #define EUSCI_A2_UART_RXBUF (HWREG16(0x4000180C))
4331 #define EUSCI_A2_UART_RXBUF_UCRXBUF__M (0x00ff)
4332 #define EUSCI_A2_UART_STATW (HWREG16(0x4000180A))
4333 #define EUSCI_A2_UART_STATW_UCADDR_UCIDLE (0x0002)
4334 #define EUSCI_A2_UART_STATW_UCADDR_UCIDLE__0 (0x0000)
4335 #define EUSCI_A2_UART_STATW_UCADDR_UCIDLE__1 (0x0002)
4336 #define EUSCI_A2_UART_STATW_UCBRK (0x0008)
4337 #define EUSCI_A2_UART_STATW_UCBRK__0 (0x0000)
4338 #define EUSCI_A2_UART_STATW_UCBRK__1 (0x0008)
4339 #define EUSCI_A2_UART_STATW_UCBUSY (0x0001)
4340 #define EUSCI_A2_UART_STATW_UCBUSY__0 (0x0000)
4341 #define EUSCI_A2_UART_STATW_UCBUSY__1 (0x0001)
4342 #define EUSCI_A2_UART_STATW_UCFE (0x0040)
4343 #define EUSCI_A2_UART_STATW_UCFE__0 (0x0000)
4344 #define EUSCI_A2_UART_STATW_UCFE__0_NO_ERROR (0x0000)
4345 #define EUSCI_A2_UART_STATW_UCFE__1 (0x0040)
4346 #define EUSCI_A2_UART_STATW_UCLISTEN (0x0080)
4347 #define EUSCI_A2_UART_STATW_UCLISTEN__0 (0x0000)
4348 #define EUSCI_A2_UART_STATW_UCLISTEN__0_DISABLED (0x0000)
4349 #define EUSCI_A2_UART_STATW_UCLISTEN__1 (0x0080)
4350 #define EUSCI_A2_UART_STATW_UCOE (0x0020)
4351 #define EUSCI_A2_UART_STATW_UCOE__0 (0x0000)
4352 #define EUSCI_A2_UART_STATW_UCOE__0_NO_ERROR (0x0000)
4353 #define EUSCI_A2_UART_STATW_UCOE__1 (0x0020)
4354 #define EUSCI_A2_UART_STATW_UCPE (0x0010)
4355 #define EUSCI_A2_UART_STATW_UCPE__0 (0x0000)
4356 #define EUSCI_A2_UART_STATW_UCPE__0_NO_ERROR (0x0000)
4357 #define EUSCI_A2_UART_STATW_UCPE__1 (0x0010)
4358 #define EUSCI_A2_UART_STATW_UCRXERR (0x0004)
4359 #define EUSCI_A2_UART_STATW_UCRXERR__0 (0x0000)
4360 #define EUSCI_A2_UART_STATW_UCRXERR__1 (0x0004)
4361 #define EUSCI_A2_UART_TXBUF (HWREG16(0x4000180E))
4362 #define EUSCI_A2_UART_TXBUF_UCTXBUF__M (0x00ff)
4363 #define EUSCI_A3_SPI_BRW (HWREG16(0x40001C06))
4364 #define EUSCI_A3_SPI_CTLW0 (HWREG16(0x40001C00))
4365 #define EUSCI_A3_SPI_CTLW0_UC7BIT (0x1000)
4366 #define EUSCI_A3_SPI_CTLW0_UC7BIT__0 (0x0000)
4367 #define EUSCI_A3_SPI_CTLW0_UC7BIT__0_8_BIT_DATA (0x0000)
4368 #define EUSCI_A3_SPI_CTLW0_UC7BIT__1 (0x1000)
4369 #define EUSCI_A3_SPI_CTLW0_UC7BIT__1_7_BIT_DATA (0x1000)
4370 #define EUSCI_A3_SPI_CTLW0_UCCKPH (0x8000)
4371 #define EUSCI_A3_SPI_CTLW0_UCCKPH__0 (0x0000)
4372 #define EUSCI_A3_SPI_CTLW0_UCCKPH__1 (0x8000)
4373 #define EUSCI_A3_SPI_CTLW0_UCCKPL (0x4000)
4374 #define EUSCI_A3_SPI_CTLW0_UCCKPL__0 (0x0000)
4375 #define EUSCI_A3_SPI_CTLW0_UCCKPL__1 (0x4000)
4376 #define EUSCI_A3_SPI_CTLW0_UCMODE__0 (0x0000)
4377 #define EUSCI_A3_SPI_CTLW0_UCMODE__0_3_PIN_SPI (0x0000)
4378 #define EUSCI_A3_SPI_CTLW0_UCMODE__1 (0x0200)
4379 #define EUSCI_A3_SPI_CTLW0_UCMODE__2 (0x0400)
4380 #define EUSCI_A3_SPI_CTLW0_UCMODE__3 (0x0600)
4381 #define EUSCI_A3_SPI_CTLW0_UCMODE__3_I2C_MODE (0x0600)
4382 #define EUSCI_A3_SPI_CTLW0_UCMODE__M (0x0600)
4383 #define EUSCI_A3_SPI_CTLW0_UCMSB (0x2000)
4384 #define EUSCI_A3_SPI_CTLW0_UCMSB__0 (0x0000)
4385 #define EUSCI_A3_SPI_CTLW0_UCMSB__0_LSB_FIRST (0x0000)
4386 #define EUSCI_A3_SPI_CTLW0_UCMSB__1 (0x2000)
4387 #define EUSCI_A3_SPI_CTLW0_UCMSB__1_MSB_FIRST (0x2000)
4388 #define EUSCI_A3_SPI_CTLW0_UCMST (0x0800)
4389 #define EUSCI_A3_SPI_CTLW0_UCMST__0 (0x0000)
4390 #define EUSCI_A3_SPI_CTLW0_UCMST__0_SLAVE_MODE (0x0000)
4391 #define EUSCI_A3_SPI_CTLW0_UCMST__1 (0x0800)
4392 #define EUSCI_A3_SPI_CTLW0_UCMST__1_MASTER_MODE (0x0800)
4393 #define EUSCI_A3_SPI_CTLW0_UCSSEL__1 (0x0040)
4394 #define EUSCI_A3_SPI_CTLW0_UCSSEL__1_ACLK (0x0040)
4395 #define EUSCI_A3_SPI_CTLW0_UCSSEL__2 (0x0080)
4396 #define EUSCI_A3_SPI_CTLW0_UCSSEL__2_SMCLK (0x0080)
4397 #define EUSCI_A3_SPI_CTLW0_UCSSEL__3 (0x00c0)
4398 #define EUSCI_A3_SPI_CTLW0_UCSSEL__3_SMCLK (0x00c0)
4399 #define EUSCI_A3_SPI_CTLW0_UCSSEL__M (0x00c0)
4400 #define EUSCI_A3_SPI_CTLW0_UCSTEM (0x0002)
4401 #define EUSCI_A3_SPI_CTLW0_UCSTEM__0 (0x0000)
4402 #define EUSCI_A3_SPI_CTLW0_UCSTEM__1 (0x0002)
4403 #define EUSCI_A3_SPI_CTLW0_UCSWRST (0x0001)
4404 #define EUSCI_A3_SPI_CTLW0_UCSWRST__0 (0x0000)
4405 #define EUSCI_A3_SPI_CTLW0_UCSWRST__1 (0x0001)
4406 #define EUSCI_A3_SPI_CTLW0_UCSYNC (0x0100)
4407 #define EUSCI_A3_SPI_CTLW0_UCSYNC__0 (0x0000)
4408 #define EUSCI_A3_SPI_CTLW0_UCSYNC__1 (0x0100)
4409 #define EUSCI_A3_SPI_IE (HWREG16(0x40001C1A))
4410 #define EUSCI_A3_SPI_IE_UCRXIE (0x0001)
4411 #define EUSCI_A3_SPI_IE_UCRXIE__0 (0x0000)
4412 #define EUSCI_A3_SPI_IE_UCRXIE__1 (0x0001)
4413 #define EUSCI_A3_SPI_IE_UCTXIE (0x0002)
4414 #define EUSCI_A3_SPI_IE_UCTXIE__0 (0x0000)
4415 #define EUSCI_A3_SPI_IE_UCTXIE__1 (0x0002)
4416 #define EUSCI_A3_SPI_IFG (HWREG16(0x40001C1C))
4417 #define EUSCI_A3_SPI_IFG_UCRXIFG (0x0001)
4418 #define EUSCI_A3_SPI_IFG_UCRXIFG__0 (0x0000)
4419 #define EUSCI_A3_SPI_IFG_UCRXIFG__1 (0x0001)
4420 #define EUSCI_A3_SPI_IFG_UCTXIFG (0x0002)
4421 #define EUSCI_A3_SPI_IFG_UCTXIFG__0 (0x0000)
4422 #define EUSCI_A3_SPI_IFG_UCTXIFG__1 (0x0002)
4423 #define EUSCI_A3_SPI_IV (HWREG16(0x40001C1E))
4424 #define EUSCI_A3_SPI_RXBUF (HWREG16(0x40001C0C))
4425 #define EUSCI_A3_SPI_RXBUF_UCRXBUF__M (0x00ff)
4426 #define EUSCI_A3_SPI_STATW (HWREG16(0x40001C0A))
4427 #define EUSCI_A3_SPI_STATW_UCBUSY (0x0001)
4428 #define EUSCI_A3_SPI_STATW_UCBUSY__0 (0x0000)
4429 #define EUSCI_A3_SPI_STATW_UCBUSY__0_EUSCI_INACTIVE (0x0000)
4430 #define EUSCI_A3_SPI_STATW_UCBUSY__1 (0x0001)
4431 #define EUSCI_A3_SPI_STATW_UCFE (0x0040)
4432 #define EUSCI_A3_SPI_STATW_UCFE__0 (0x0000)
4433 #define EUSCI_A3_SPI_STATW_UCFE__0_NO_ERROR (0x0000)
4434 #define EUSCI_A3_SPI_STATW_UCFE__1 (0x0040)
4435 #define EUSCI_A3_SPI_STATW_UCLISTEN (0x0080)
4436 #define EUSCI_A3_SPI_STATW_UCLISTEN__0 (0x0000)
4437 #define EUSCI_A3_SPI_STATW_UCLISTEN__0_DISABLED (0x0000)
4438 #define EUSCI_A3_SPI_STATW_UCLISTEN__1 (0x0080)
4439 #define EUSCI_A3_SPI_STATW_UCOE (0x0020)
4440 #define EUSCI_A3_SPI_STATW_UCOE__0 (0x0000)
4441 #define EUSCI_A3_SPI_STATW_UCOE__0_NO_ERROR (0x0000)
4442 #define EUSCI_A3_SPI_STATW_UCOE__1 (0x0020)
4443 #define EUSCI_A3_SPI_TXBUF (HWREG16(0x40001C0E))
4444 #define EUSCI_A3_SPI_TXBUF_UCTXBUF__M (0x00ff)
4445 #define EUSCI_A3_UART_ABCTL (HWREG16(0x40001C10))
4446 #define EUSCI_A3_UART_ABCTL_UCABDEN (0x0001)
4447 #define EUSCI_A3_UART_ABCTL_UCABDEN__0 (0x0000)
4448 #define EUSCI_A3_UART_ABCTL_UCABDEN__1 (0x0001)
4449 #define EUSCI_A3_UART_ABCTL_UCBTOE (0x0004)
4450 #define EUSCI_A3_UART_ABCTL_UCBTOE__0 (0x0000)
4451 #define EUSCI_A3_UART_ABCTL_UCBTOE__0_NO_ERROR (0x0000)
4452 #define EUSCI_A3_UART_ABCTL_UCBTOE__1 (0x0004)
4453 #define EUSCI_A3_UART_ABCTL_UCDELIM__0 (0x0000)
4454 #define EUSCI_A3_UART_ABCTL_UCDELIM__0_1_BIT_TIME (0x0000)
4455 #define EUSCI_A3_UART_ABCTL_UCDELIM__1 (0x0010)
4456 #define EUSCI_A3_UART_ABCTL_UCDELIM__1_2_BIT_TIMES (0x0010)
4457 #define EUSCI_A3_UART_ABCTL_UCDELIM__2 (0x0020)
4458 #define EUSCI_A3_UART_ABCTL_UCDELIM__2_3_BIT_TIMES (0x0020)
4459 #define EUSCI_A3_UART_ABCTL_UCDELIM__3 (0x0030)
4460 #define EUSCI_A3_UART_ABCTL_UCDELIM__3_4_BIT_TIMES (0x0030)
4461 #define EUSCI_A3_UART_ABCTL_UCDELIM__M (0x0030)
4462 #define EUSCI_A3_UART_ABCTL_UCSTOE (0x0008)
4463 #define EUSCI_A3_UART_ABCTL_UCSTOE__0 (0x0000)
4464 #define EUSCI_A3_UART_ABCTL_UCSTOE__0_NO_ERROR (0x0000)
4465 #define EUSCI_A3_UART_ABCTL_UCSTOE__1 (0x0008)
4466 #define EUSCI_A3_UART_BRW (HWREG16(0x40001C06))
4467 #define EUSCI_A3_UART_CTLW0 (HWREG16(0x40001C00))
4468 #define EUSCI_A3_UART_CTLW0_UC7BIT (0x1000)
4469 #define EUSCI_A3_UART_CTLW0_UC7BIT__0 (0x0000)
4470 #define EUSCI_A3_UART_CTLW0_UC7BIT__0_8_BIT_DATA (0x0000)
4471 #define EUSCI_A3_UART_CTLW0_UC7BIT__1 (0x1000)
4472 #define EUSCI_A3_UART_CTLW0_UC7BIT__1_7_BIT_DATA (0x1000)
4473 #define EUSCI_A3_UART_CTLW0_UCBRKIE (0x0010)
4474 #define EUSCI_A3_UART_CTLW0_UCBRKIE__0 (0x0000)
4475 #define EUSCI_A3_UART_CTLW0_UCBRKIE__1 (0x0010)
4476 #define EUSCI_A3_UART_CTLW0_UCDORM (0x0008)
4477 #define EUSCI_A3_UART_CTLW0_UCDORM__0 (0x0000)
4478 #define EUSCI_A3_UART_CTLW0_UCDORM__1 (0x0008)
4479 #define EUSCI_A3_UART_CTLW0_UCMODE__0 (0x0000)
4480 #define EUSCI_A3_UART_CTLW0_UCMODE__0_UART_MODE (0x0000)
4481 #define EUSCI_A3_UART_CTLW0_UCMODE__1 (0x0200)
4482 #define EUSCI_A3_UART_CTLW0_UCMODE__2 (0x0400)
4483 #define EUSCI_A3_UART_CTLW0_UCMODE__3 (0x0600)
4484 #define EUSCI_A3_UART_CTLW0_UCMODE__M (0x0600)
4485 #define EUSCI_A3_UART_CTLW0_UCMSB (0x2000)
4486 #define EUSCI_A3_UART_CTLW0_UCMSB__0 (0x0000)
4487 #define EUSCI_A3_UART_CTLW0_UCMSB__0_LSB_FIRST (0x0000)
4488 #define EUSCI_A3_UART_CTLW0_UCMSB__1 (0x2000)
4489 #define EUSCI_A3_UART_CTLW0_UCMSB__1_MSB_FIRST (0x2000)
4490 #define EUSCI_A3_UART_CTLW0_UCPAR (0x4000)
4491 #define EUSCI_A3_UART_CTLW0_UCPAR__0 (0x0000)
4492 #define EUSCI_A3_UART_CTLW0_UCPAR__0_ODD_PARITY (0x0000)
4493 #define EUSCI_A3_UART_CTLW0_UCPAR__1 (0x4000)
4494 #define EUSCI_A3_UART_CTLW0_UCPAR__1_EVEN_PARITY (0x4000)
4495 #define EUSCI_A3_UART_CTLW0_UCPEN (0x8000)
4496 #define EUSCI_A3_UART_CTLW0_UCPEN__0 (0x0000)
4497 #define EUSCI_A3_UART_CTLW0_UCPEN__0_PARITY_DISABLED (0x0000)
4498 #define EUSCI_A3_UART_CTLW0_UCPEN__1 (0x8000)
4499 #define EUSCI_A3_UART_CTLW0_UCRXEIE (0x0020)
4500 #define EUSCI_A3_UART_CTLW0_UCRXEIE__0 (0x0000)
4501 #define EUSCI_A3_UART_CTLW0_UCRXEIE__1 (0x0020)
4502 #define EUSCI_A3_UART_CTLW0_UCSPB (0x0800)
4503 #define EUSCI_A3_UART_CTLW0_UCSPB__0 (0x0000)
4504 #define EUSCI_A3_UART_CTLW0_UCSPB__0_ONE_STOP_BIT (0x0000)
4505 #define EUSCI_A3_UART_CTLW0_UCSPB__1 (0x0800)
4506 #define EUSCI_A3_UART_CTLW0_UCSPB__1_TWO_STOP_BITS (0x0800)
4507 #define EUSCI_A3_UART_CTLW0_UCSSEL__0 (0x0000)
4508 #define EUSCI_A3_UART_CTLW0_UCSSEL__0_UCLK (0x0000)
4509 #define EUSCI_A3_UART_CTLW0_UCSSEL__1 (0x0040)
4510 #define EUSCI_A3_UART_CTLW0_UCSSEL__1_ACLK (0x0040)
4511 #define EUSCI_A3_UART_CTLW0_UCSSEL__2 (0x0080)
4512 #define EUSCI_A3_UART_CTLW0_UCSSEL__2_SMCLK (0x0080)
4513 #define EUSCI_A3_UART_CTLW0_UCSSEL__3 (0x00c0)
4514 #define EUSCI_A3_UART_CTLW0_UCSSEL__3_SMCLK (0x00c0)
4515 #define EUSCI_A3_UART_CTLW0_UCSSEL__M (0x00c0)
4516 #define EUSCI_A3_UART_CTLW0_UCSWRST (0x0001)
4517 #define EUSCI_A3_UART_CTLW0_UCSWRST__0 (0x0000)
4518 #define EUSCI_A3_UART_CTLW0_UCSWRST__1 (0x0001)
4519 #define EUSCI_A3_UART_CTLW0_UCSYNC (0x0100)
4520 #define EUSCI_A3_UART_CTLW0_UCSYNC__0 (0x0000)
4521 #define EUSCI_A3_UART_CTLW0_UCSYNC__1 (0x0100)
4522 #define EUSCI_A3_UART_CTLW0_UCTXADDR (0x0004)
4523 #define EUSCI_A3_UART_CTLW0_UCTXADDR__0 (0x0000)
4524 #define EUSCI_A3_UART_CTLW0_UCTXADDR__1 (0x0004)
4525 #define EUSCI_A3_UART_CTLW0_UCTXBRK (0x0002)
4526 #define EUSCI_A3_UART_CTLW0_UCTXBRK__0 (0x0000)
4527 #define EUSCI_A3_UART_CTLW0_UCTXBRK__1 (0x0002)
4528 #define EUSCI_A3_UART_CTLW1 (HWREG16(0x40001C02))
4529 #define EUSCI_A3_UART_CTLW1_UCGLIT__0 (0x0000)
4530 #define EUSCI_A3_UART_CTLW1_UCGLIT__0__2_NS (0x0000)
4531 #define EUSCI_A3_UART_CTLW1_UCGLIT__1 (0x0001)
4532 #define EUSCI_A3_UART_CTLW1_UCGLIT__1__50_NS (0x0001)
4533 #define EUSCI_A3_UART_CTLW1_UCGLIT__2 (0x0002)
4534 #define EUSCI_A3_UART_CTLW1_UCGLIT__2__100_NS (0x0002)
4535 #define EUSCI_A3_UART_CTLW1_UCGLIT__3 (0x0003)
4536 #define EUSCI_A3_UART_CTLW1_UCGLIT__3__200_NS (0x0003)
4537 #define EUSCI_A3_UART_CTLW1_UCGLIT__M (0x0003)
4538 #define EUSCI_A3_UART_IE (HWREG16(0x40001C1A))
4539 #define EUSCI_A3_UART_IE_UCRXIE (0x0001)
4540 #define EUSCI_A3_UART_IE_UCRXIE__0 (0x0000)
4541 #define EUSCI_A3_UART_IE_UCRXIE__1 (0x0001)
4542 #define EUSCI_A3_UART_IE_UCSTTIE (0x0004)
4543 #define EUSCI_A3_UART_IE_UCSTTIE__0 (0x0000)
4544 #define EUSCI_A3_UART_IE_UCSTTIE__1 (0x0004)
4545 #define EUSCI_A3_UART_IE_UCTXCPTIE (0x0008)
4546 #define EUSCI_A3_UART_IE_UCTXCPTIE__0 (0x0000)
4547 #define EUSCI_A3_UART_IE_UCTXCPTIE__1 (0x0008)
4548 #define EUSCI_A3_UART_IE_UCTXIE (0x0002)
4549 #define EUSCI_A3_UART_IE_UCTXIE__0 (0x0000)
4550 #define EUSCI_A3_UART_IE_UCTXIE__1 (0x0002)
4551 #define EUSCI_A3_UART_IFG (HWREG16(0x40001C1C))
4552 #define EUSCI_A3_UART_IFG_UCRXIFG (0x0001)
4553 #define EUSCI_A3_UART_IFG_UCRXIFG__0 (0x0000)
4554 #define EUSCI_A3_UART_IFG_UCRXIFG__1 (0x0001)
4555 #define EUSCI_A3_UART_IFG_UCSTTIFG (0x0004)
4556 #define EUSCI_A3_UART_IFG_UCSTTIFG__0 (0x0000)
4557 #define EUSCI_A3_UART_IFG_UCSTTIFG__1 (0x0004)
4558 #define EUSCI_A3_UART_IFG_UCTXCPTIFG (0x0008)
4559 #define EUSCI_A3_UART_IFG_UCTXCPTIFG__0 (0x0000)
4560 #define EUSCI_A3_UART_IFG_UCTXCPTIFG__1 (0x0008)
4561 #define EUSCI_A3_UART_IFG_UCTXIFG (0x0002)
4562 #define EUSCI_A3_UART_IFG_UCTXIFG__0 (0x0000)
4563 #define EUSCI_A3_UART_IFG_UCTXIFG__1 (0x0002)
4564 #define EUSCI_A3_UART_IRCTL (HWREG16(0x40001C12))
4565 #define EUSCI_A3_UART_IRCTL_UCIREN (0x0001)
4566 #define EUSCI_A3_UART_IRCTL_UCIREN__0 (0x0000)
4567 #define EUSCI_A3_UART_IRCTL_UCIREN__1 (0x0001)
4568 #define EUSCI_A3_UART_IRCTL_UCIRRXFE (0x0100)
4569 #define EUSCI_A3_UART_IRCTL_UCIRRXFE__0 (0x0000)
4570 #define EUSCI_A3_UART_IRCTL_UCIRRXFE__1 (0x0100)
4571 #define EUSCI_A3_UART_IRCTL_UCIRRXFL__M (0xfc00)
4572 #define EUSCI_A3_UART_IRCTL_UCIRRXPL (0x0200)
4573 #define EUSCI_A3_UART_IRCTL_UCIRRXPL__0 (0x0000)
4574 #define EUSCI_A3_UART_IRCTL_UCIRRXPL__1 (0x0200)
4575 #define EUSCI_A3_UART_IRCTL_UCIRTXCLK (0x0002)
4576 #define EUSCI_A3_UART_IRCTL_UCIRTXCLK__0 (0x0000)
4577 #define EUSCI_A3_UART_IRCTL_UCIRTXCLK__0_BRCLK (0x0000)
4578 #define EUSCI_A3_UART_IRCTL_UCIRTXCLK__1 (0x0002)
4579 #define EUSCI_A3_UART_IRCTL_UCIRTXPL__M (0x00fc)
4580 #define EUSCI_A3_UART_IV (HWREG16(0x40001C1E))
4581 #define EUSCI_A3_UART_MCTLW (HWREG16(0x40001C08))
4582 #define EUSCI_A3_UART_MCTLW_UCBRF__M (0x00f0)
4583 #define EUSCI_A3_UART_MCTLW_UCBRS__M (0xff00)
4584 #define EUSCI_A3_UART_MCTLW_UCOS16 (0x0001)
4585 #define EUSCI_A3_UART_MCTLW_UCOS16__0 (0x0000)
4586 #define EUSCI_A3_UART_MCTLW_UCOS16__0_DISABLED (0x0000)
4587 #define EUSCI_A3_UART_MCTLW_UCOS16__1 (0x0001)
4588 #define EUSCI_A3_UART_MCTLW_UCOS16__1_ENABLED (0x0001)
4589 #define EUSCI_A3_UART_RXBUF (HWREG16(0x40001C0C))
4590 #define EUSCI_A3_UART_RXBUF_UCRXBUF__M (0x00ff)
4591 #define EUSCI_A3_UART_STATW (HWREG16(0x40001C0A))
4592 #define EUSCI_A3_UART_STATW_UCADDR_UCIDLE (0x0002)
4593 #define EUSCI_A3_UART_STATW_UCADDR_UCIDLE__0 (0x0000)
4594 #define EUSCI_A3_UART_STATW_UCADDR_UCIDLE__1 (0x0002)
4595 #define EUSCI_A3_UART_STATW_UCBRK (0x0008)
4596 #define EUSCI_A3_UART_STATW_UCBRK__0 (0x0000)
4597 #define EUSCI_A3_UART_STATW_UCBRK__1 (0x0008)
4598 #define EUSCI_A3_UART_STATW_UCBUSY (0x0001)
4599 #define EUSCI_A3_UART_STATW_UCBUSY__0 (0x0000)
4600 #define EUSCI_A3_UART_STATW_UCBUSY__1 (0x0001)
4601 #define EUSCI_A3_UART_STATW_UCFE (0x0040)
4602 #define EUSCI_A3_UART_STATW_UCFE__0 (0x0000)
4603 #define EUSCI_A3_UART_STATW_UCFE__0_NO_ERROR (0x0000)
4604 #define EUSCI_A3_UART_STATW_UCFE__1 (0x0040)
4605 #define EUSCI_A3_UART_STATW_UCLISTEN (0x0080)
4606 #define EUSCI_A3_UART_STATW_UCLISTEN__0 (0x0000)
4607 #define EUSCI_A3_UART_STATW_UCLISTEN__0_DISABLED (0x0000)
4608 #define EUSCI_A3_UART_STATW_UCLISTEN__1 (0x0080)
4609 #define EUSCI_A3_UART_STATW_UCOE (0x0020)
4610 #define EUSCI_A3_UART_STATW_UCOE__0 (0x0000)
4611 #define EUSCI_A3_UART_STATW_UCOE__0_NO_ERROR (0x0000)
4612 #define EUSCI_A3_UART_STATW_UCOE__1 (0x0020)
4613 #define EUSCI_A3_UART_STATW_UCPE (0x0010)
4614 #define EUSCI_A3_UART_STATW_UCPE__0 (0x0000)
4615 #define EUSCI_A3_UART_STATW_UCPE__0_NO_ERROR (0x0000)
4616 #define EUSCI_A3_UART_STATW_UCPE__1 (0x0010)
4617 #define EUSCI_A3_UART_STATW_UCRXERR (0x0004)
4618 #define EUSCI_A3_UART_STATW_UCRXERR__0 (0x0000)
4619 #define EUSCI_A3_UART_STATW_UCRXERR__1 (0x0004)
4620 #define EUSCI_A3_UART_TXBUF (HWREG16(0x40001C0E))
4621 #define EUSCI_A3_UART_TXBUF_UCTXBUF__M (0x00ff)
4622 #define EUSCI_B0_I2C_ADDMASK (HWREG16(0x4000201E))
4623 #define EUSCI_B0_I2C_ADDMASK_ADDMASK__M (0x03ff)
4624 #define EUSCI_B0_I2C_ADDRX (HWREG16(0x4000201C))
4625 #define EUSCI_B0_I2C_ADDRX_ADDRX__M (0x03ff)
4626 #define EUSCI_B0_I2C_BRW (HWREG16(0x40002006))
4627 #define EUSCI_B0_I2C_CTLW0 (HWREG16(0x40002000))
4628 #define EUSCI_B0_I2C_CTLW0_UCA10 (0x8000)
4629 #define EUSCI_B0_I2C_CTLW0_UCA10__0 (0x0000)
4630 #define EUSCI_B0_I2C_CTLW0_UCA10__1 (0x8000)
4631 #define EUSCI_B0_I2C_CTLW0_UCMM (0x2000)
4632 #define EUSCI_B0_I2C_CTLW0_UCMM__0 (0x0000)
4633 #define EUSCI_B0_I2C_CTLW0_UCMM__1 (0x2000)
4634 #define EUSCI_B0_I2C_CTLW0_UCMODE__0 (0x0000)
4635 #define EUSCI_B0_I2C_CTLW0_UCMODE__0_3_PIN_SPI (0x0000)
4636 #define EUSCI_B0_I2C_CTLW0_UCMODE__1 (0x0200)
4637 #define EUSCI_B0_I2C_CTLW0_UCMODE__2 (0x0400)
4638 #define EUSCI_B0_I2C_CTLW0_UCMODE__3 (0x0600)
4639 #define EUSCI_B0_I2C_CTLW0_UCMODE__3_I2C_MODE (0x0600)
4640 #define EUSCI_B0_I2C_CTLW0_UCMODE__M (0x0600)
4641 #define EUSCI_B0_I2C_CTLW0_UCMST (0x0800)
4642 #define EUSCI_B0_I2C_CTLW0_UCMST__0 (0x0000)
4643 #define EUSCI_B0_I2C_CTLW0_UCMST__0_SLAVE_MODE (0x0000)
4644 #define EUSCI_B0_I2C_CTLW0_UCMST__1 (0x0800)
4645 #define EUSCI_B0_I2C_CTLW0_UCMST__1_MASTER_MODE (0x0800)
4646 #define EUSCI_B0_I2C_CTLW0_UCSLA10 (0x4000)
4647 #define EUSCI_B0_I2C_CTLW0_UCSLA10__0 (0x0000)
4648 #define EUSCI_B0_I2C_CTLW0_UCSLA10__1 (0x4000)
4649 #define EUSCI_B0_I2C_CTLW0_UCSSEL__0 (0x0000)
4650 #define EUSCI_B0_I2C_CTLW0_UCSSEL__0_UCLKI (0x0000)
4651 #define EUSCI_B0_I2C_CTLW0_UCSSEL__1 (0x0040)
4652 #define EUSCI_B0_I2C_CTLW0_UCSSEL__1_ACLK (0x0040)
4653 #define EUSCI_B0_I2C_CTLW0_UCSSEL__2 (0x0080)
4654 #define EUSCI_B0_I2C_CTLW0_UCSSEL__2_SMCLK (0x0080)
4655 #define EUSCI_B0_I2C_CTLW0_UCSSEL__3 (0x00c0)
4656 #define EUSCI_B0_I2C_CTLW0_UCSSEL__3_SMCLK (0x00c0)
4657 #define EUSCI_B0_I2C_CTLW0_UCSSEL__M (0x00c0)
4658 #define EUSCI_B0_I2C_CTLW0_UCSWRST (0x0001)
4659 #define EUSCI_B0_I2C_CTLW0_UCSWRST__0 (0x0000)
4660 #define EUSCI_B0_I2C_CTLW0_UCSWRST__1 (0x0001)
4661 #define EUSCI_B0_I2C_CTLW0_UCSYNC (0x0100)
4662 #define EUSCI_B0_I2C_CTLW0_UCTR (0x0010)
4663 #define EUSCI_B0_I2C_CTLW0_UCTR__0 (0x0000)
4664 #define EUSCI_B0_I2C_CTLW0_UCTR__0_RECEIVER (0x0000)
4665 #define EUSCI_B0_I2C_CTLW0_UCTR__1 (0x0010)
4666 #define EUSCI_B0_I2C_CTLW0_UCTR__1_TRANSMITTER (0x0010)
4667 #define EUSCI_B0_I2C_CTLW0_UCTXACK (0x0020)
4668 #define EUSCI_B0_I2C_CTLW0_UCTXACK__0 (0x0000)
4669 #define EUSCI_B0_I2C_CTLW0_UCTXACK__1 (0x0020)
4670 #define EUSCI_B0_I2C_CTLW0_UCTXNACK (0x0008)
4671 #define EUSCI_B0_I2C_CTLW0_UCTXNACK__0 (0x0000)
4672 #define EUSCI_B0_I2C_CTLW0_UCTXNACK__1 (0x0008)
4673 #define EUSCI_B0_I2C_CTLW0_UCTXNACK__1_GENERATE_NACK (0x0008)
4674 #define EUSCI_B0_I2C_CTLW0_UCTXSTP (0x0004)
4675 #define EUSCI_B0_I2C_CTLW0_UCTXSTP__0 (0x0000)
4676 #define EUSCI_B0_I2C_CTLW0_UCTXSTP__1 (0x0004)
4677 #define EUSCI_B0_I2C_CTLW0_UCTXSTP__1_GENERATE_STOP (0x0004)
4678 #define EUSCI_B0_I2C_CTLW0_UCTXSTT (0x0002)
4679 #define EUSCI_B0_I2C_CTLW0_UCTXSTT__0 (0x0000)
4680 #define EUSCI_B0_I2C_CTLW0_UCTXSTT__1 (0x0002)
4681 #define EUSCI_B0_I2C_CTLW1 (HWREG16(0x40002002))
4682 #define EUSCI_B0_I2C_CTLW1_UCASTP__0 (0x0000)
4683 #define EUSCI_B0_I2C_CTLW1_UCASTP__1 (0x0004)
4684 #define EUSCI_B0_I2C_CTLW1_UCASTP__2 (0x0008)
4685 #define EUSCI_B0_I2C_CTLW1_UCASTP__M (0x000c)
4686 #define EUSCI_B0_I2C_CTLW1_UCCLTO__0 (0x0000)
4687 #define EUSCI_B0_I2C_CTLW1_UCCLTO__1 (0x0040)
4688 #define EUSCI_B0_I2C_CTLW1_UCCLTO__2 (0x0080)
4689 #define EUSCI_B0_I2C_CTLW1_UCCLTO__3 (0x00c0)
4690 #define EUSCI_B0_I2C_CTLW1_UCCLTO__M (0x00c0)
4691 #define EUSCI_B0_I2C_CTLW1_UCETXINT (0x0100)
4692 #define EUSCI_B0_I2C_CTLW1_UCETXINT__0 (0x0000)
4693 #define EUSCI_B0_I2C_CTLW1_UCETXINT__1 (0x0100)
4694 #define EUSCI_B0_I2C_CTLW1_UCGLIT__0 (0x0000)
4695 #define EUSCI_B0_I2C_CTLW1_UCGLIT__0_50_NS (0x0000)
4696 #define EUSCI_B0_I2C_CTLW1_UCGLIT__1 (0x0001)
4697 #define EUSCI_B0_I2C_CTLW1_UCGLIT__1_25_NS (0x0001)
4698 #define EUSCI_B0_I2C_CTLW1_UCGLIT__2 (0x0002)
4699 #define EUSCI_B0_I2C_CTLW1_UCGLIT__2_12_5_NS (0x0002)
4700 #define EUSCI_B0_I2C_CTLW1_UCGLIT__3 (0x0003)
4701 #define EUSCI_B0_I2C_CTLW1_UCGLIT__3_6_25_NS (0x0003)
4702 #define EUSCI_B0_I2C_CTLW1_UCGLIT__M (0x0003)
4703 #define EUSCI_B0_I2C_CTLW1_UCSTPNACK (0x0020)
4704 #define EUSCI_B0_I2C_CTLW1_UCSTPNACK__0 (0x0000)
4705 #define EUSCI_B0_I2C_CTLW1_UCSTPNACK__1 (0x0020)
4706 #define EUSCI_B0_I2C_CTLW1_UCSWACK (0x0010)
4707 #define EUSCI_B0_I2C_CTLW1_UCSWACK__0 (0x0000)
4708 #define EUSCI_B0_I2C_CTLW1_UCSWACK__1 (0x0010)
4709 #define EUSCI_B0_I2C_I2COA0 (HWREG16(0x40002014))
4710 #define EUSCI_B0_I2C_I2COA0_I2COA__M (0x03ff)
4711 #define EUSCI_B0_I2C_I2COA0_UCGCEN (0x8000)
4712 #define EUSCI_B0_I2C_I2COA0_UCGCEN__0 (0x0000)
4713 #define EUSCI_B0_I2C_I2COA0_UCGCEN__1 (0x8000)
4714 #define EUSCI_B0_I2C_I2COA0_UCOAEN (0x0400)
4715 #define EUSCI_B0_I2C_I2COA0_UCOAEN__0 (0x0000)
4716 #define EUSCI_B0_I2C_I2COA0_UCOAEN__1 (0x0400)
4717 #define EUSCI_B0_I2C_I2COA1 (HWREG16(0x40002016))
4718 #define EUSCI_B0_I2C_I2COA1_I2COA1__M (0x03ff)
4719 #define EUSCI_B0_I2C_I2COA1_UCOAEN (0x0400)
4720 #define EUSCI_B0_I2C_I2COA1_UCOAEN__0 (0x0000)
4721 #define EUSCI_B0_I2C_I2COA1_UCOAEN__1 (0x0400)
4722 #define EUSCI_B0_I2C_I2COA2 (HWREG16(0x40002018))
4723 #define EUSCI_B0_I2C_I2COA2_I2COA2__M (0x03ff)
4724 #define EUSCI_B0_I2C_I2COA2_UCOAEN (0x0400)
4725 #define EUSCI_B0_I2C_I2COA2_UCOAEN__0 (0x0000)
4726 #define EUSCI_B0_I2C_I2COA2_UCOAEN__1 (0x0400)
4727 #define EUSCI_B0_I2C_I2COA3 (HWREG16(0x4000201A))
4728 #define EUSCI_B0_I2C_I2COA3_I2COA3__M (0x03ff)
4729 #define EUSCI_B0_I2C_I2COA3_UCOAEN (0x0400)
4730 #define EUSCI_B0_I2C_I2COA3_UCOAEN__0 (0x0000)
4731 #define EUSCI_B0_I2C_I2COA3_UCOAEN__1 (0x0400)
4732 #define EUSCI_B0_I2C_I2CSA (HWREG16(0x40002020))
4733 #define EUSCI_B0_I2C_I2CSA_I2CSA__M (0x03ff)
4734 #define EUSCI_B0_I2C_IE (HWREG16(0x4000202A))
4735 #define EUSCI_B0_I2C_IE_UCALIE (0x0010)
4736 #define EUSCI_B0_I2C_IE_UCALIE__0 (0x0000)
4737 #define EUSCI_B0_I2C_IE_UCALIE__1 (0x0010)
4738 #define EUSCI_B0_I2C_IE_UCBCNTIE (0x0040)
4739 #define EUSCI_B0_I2C_IE_UCBCNTIE__0 (0x0000)
4740 #define EUSCI_B0_I2C_IE_UCBCNTIE__1 (0x0040)
4741 #define EUSCI_B0_I2C_IE_UCBIT9IE (0x4000)
4742 #define EUSCI_B0_I2C_IE_UCBIT9IE__0 (0x0000)
4743 #define EUSCI_B0_I2C_IE_UCBIT9IE__1 (0x4000)
4744 #define EUSCI_B0_I2C_IE_UCCLTOIE (0x0080)
4745 #define EUSCI_B0_I2C_IE_UCCLTOIE__0 (0x0000)
4746 #define EUSCI_B0_I2C_IE_UCCLTOIE__1 (0x0080)
4747 #define EUSCI_B0_I2C_IE_UCNACKIE (0x0020)
4748 #define EUSCI_B0_I2C_IE_UCNACKIE__0 (0x0000)
4749 #define EUSCI_B0_I2C_IE_UCNACKIE__1 (0x0020)
4750 #define EUSCI_B0_I2C_IE_UCRXIE0 (0x0001)
4751 #define EUSCI_B0_I2C_IE_UCRXIE0__0 (0x0000)
4752 #define EUSCI_B0_I2C_IE_UCRXIE0__1 (0x0001)
4753 #define EUSCI_B0_I2C_IE_UCRXIE1 (0x0100)
4754 #define EUSCI_B0_I2C_IE_UCRXIE1__0 (0x0000)
4755 #define EUSCI_B0_I2C_IE_UCRXIE1__1 (0x0100)
4756 #define EUSCI_B0_I2C_IE_UCRXIE2 (0x0400)
4757 #define EUSCI_B0_I2C_IE_UCRXIE2__0 (0x0000)
4758 #define EUSCI_B0_I2C_IE_UCRXIE2__1 (0x0400)
4759 #define EUSCI_B0_I2C_IE_UCRXIE3 (0x1000)
4760 #define EUSCI_B0_I2C_IE_UCRXIE3__0 (0x0000)
4761 #define EUSCI_B0_I2C_IE_UCRXIE3__1 (0x1000)
4762 #define EUSCI_B0_I2C_IE_UCSTPIE (0x0008)
4763 #define EUSCI_B0_I2C_IE_UCSTPIE__0 (0x0000)
4764 #define EUSCI_B0_I2C_IE_UCSTPIE__1 (0x0008)
4765 #define EUSCI_B0_I2C_IE_UCSTTIE (0x0004)
4766 #define EUSCI_B0_I2C_IE_UCSTTIE__0 (0x0000)
4767 #define EUSCI_B0_I2C_IE_UCSTTIE__1 (0x0004)
4768 #define EUSCI_B0_I2C_IE_UCTXIE0 (0x0002)
4769 #define EUSCI_B0_I2C_IE_UCTXIE0__0 (0x0000)
4770 #define EUSCI_B0_I2C_IE_UCTXIE0__1 (0x0002)
4771 #define EUSCI_B0_I2C_IE_UCTXIE1 (0x0200)
4772 #define EUSCI_B0_I2C_IE_UCTXIE1__0 (0x0000)
4773 #define EUSCI_B0_I2C_IE_UCTXIE1__1 (0x0200)
4774 #define EUSCI_B0_I2C_IE_UCTXIE2 (0x0800)
4775 #define EUSCI_B0_I2C_IE_UCTXIE2__0 (0x0000)
4776 #define EUSCI_B0_I2C_IE_UCTXIE2__1 (0x0800)
4777 #define EUSCI_B0_I2C_IE_UCTXIE3 (0x2000)
4778 #define EUSCI_B0_I2C_IE_UCTXIE3__0 (0x0000)
4779 #define EUSCI_B0_I2C_IE_UCTXIE3__1 (0x2000)
4780 #define EUSCI_B0_I2C_IFG (HWREG16(0x4000202C))
4781 #define EUSCI_B0_I2C_IFG_UCALIFG (0x0010)
4782 #define EUSCI_B0_I2C_IFG_UCALIFG__0 (0x0000)
4783 #define EUSCI_B0_I2C_IFG_UCALIFG__1 (0x0010)
4784 #define EUSCI_B0_I2C_IFG_UCBCNTIFG (0x0040)
4785 #define EUSCI_B0_I2C_IFG_UCBCNTIFG__0 (0x0000)
4786 #define EUSCI_B0_I2C_IFG_UCBCNTIFG__1 (0x0040)
4787 #define EUSCI_B0_I2C_IFG_UCBIT9IFG (0x4000)
4788 #define EUSCI_B0_I2C_IFG_UCBIT9IFG__0 (0x0000)
4789 #define EUSCI_B0_I2C_IFG_UCBIT9IFG__1 (0x4000)
4790 #define EUSCI_B0_I2C_IFG_UCCLTOIFG (0x0080)
4791 #define EUSCI_B0_I2C_IFG_UCCLTOIFG__0 (0x0000)
4792 #define EUSCI_B0_I2C_IFG_UCCLTOIFG__1 (0x0080)
4793 #define EUSCI_B0_I2C_IFG_UCNACKIFG (0x0020)
4794 #define EUSCI_B0_I2C_IFG_UCNACKIFG__0 (0x0000)
4795 #define EUSCI_B0_I2C_IFG_UCNACKIFG__1 (0x0020)
4796 #define EUSCI_B0_I2C_IFG_UCRXIFG0 (0x0001)
4797 #define EUSCI_B0_I2C_IFG_UCRXIFG0__0 (0x0000)
4798 #define EUSCI_B0_I2C_IFG_UCRXIFG0__1 (0x0001)
4799 #define EUSCI_B0_I2C_IFG_UCRXIFG1 (0x0100)
4800 #define EUSCI_B0_I2C_IFG_UCRXIFG1__0 (0x0000)
4801 #define EUSCI_B0_I2C_IFG_UCRXIFG1__1 (0x0100)
4802 #define EUSCI_B0_I2C_IFG_UCRXIFG2 (0x0400)
4803 #define EUSCI_B0_I2C_IFG_UCRXIFG2__0 (0x0000)
4804 #define EUSCI_B0_I2C_IFG_UCRXIFG2__1 (0x0400)
4805 #define EUSCI_B0_I2C_IFG_UCRXIFG3 (0x1000)
4806 #define EUSCI_B0_I2C_IFG_UCRXIFG3__0 (0x0000)
4807 #define EUSCI_B0_I2C_IFG_UCRXIFG3__1 (0x1000)
4808 #define EUSCI_B0_I2C_IFG_UCSTPIFG (0x0008)
4809 #define EUSCI_B0_I2C_IFG_UCSTPIFG__0 (0x0000)
4810 #define EUSCI_B0_I2C_IFG_UCSTPIFG__1 (0x0008)
4811 #define EUSCI_B0_I2C_IFG_UCSTTIFG (0x0004)
4812 #define EUSCI_B0_I2C_IFG_UCSTTIFG__0 (0x0000)
4813 #define EUSCI_B0_I2C_IFG_UCSTTIFG__1 (0x0004)
4814 #define EUSCI_B0_I2C_IFG_UCTXIFG0 (0x0002)
4815 #define EUSCI_B0_I2C_IFG_UCTXIFG0__0 (0x0000)
4816 #define EUSCI_B0_I2C_IFG_UCTXIFG0__1 (0x0002)
4817 #define EUSCI_B0_I2C_IFG_UCTXIFG1 (0x0200)
4818 #define EUSCI_B0_I2C_IFG_UCTXIFG1__0 (0x0000)
4819 #define EUSCI_B0_I2C_IFG_UCTXIFG1__1 (0x0200)
4820 #define EUSCI_B0_I2C_IFG_UCTXIFG2 (0x0800)
4821 #define EUSCI_B0_I2C_IFG_UCTXIFG2__0 (0x0000)
4822 #define EUSCI_B0_I2C_IFG_UCTXIFG2__1 (0x0800)
4823 #define EUSCI_B0_I2C_IFG_UCTXIFG3 (0x2000)
4824 #define EUSCI_B0_I2C_IFG_UCTXIFG3__0 (0x0000)
4825 #define EUSCI_B0_I2C_IFG_UCTXIFG3__1 (0x2000)
4826 #define EUSCI_B0_I2C_IV (HWREG16(0x4000202E))
4827 #define EUSCI_B0_I2C_RXBUF (HWREG16(0x4000200C))
4828 #define EUSCI_B0_I2C_RXBUF_UCRXBUF__M (0x00ff)
4829 #define EUSCI_B0_I2C_STATW (HWREG16(0x40002008))
4830 #define EUSCI_B0_I2C_STATW_UCBBUSY (0x0010)
4831 #define EUSCI_B0_I2C_STATW_UCBBUSY__0 (0x0000)
4832 #define EUSCI_B0_I2C_STATW_UCBBUSY__0_BUS_INACTIVE (0x0000)
4833 #define EUSCI_B0_I2C_STATW_UCBBUSY__1 (0x0010)
4834 #define EUSCI_B0_I2C_STATW_UCBBUSY__1_BUS_BUSY (0x0010)
4835 #define EUSCI_B0_I2C_STATW_UCBCNT__M (0xff00)
4836 #define EUSCI_B0_I2C_STATW_UCGC (0x0020)
4837 #define EUSCI_B0_I2C_STATW_UCGC__0 (0x0000)
4838 #define EUSCI_B0_I2C_STATW_UCGC__1 (0x0020)
4839 #define EUSCI_B0_I2C_STATW_UCSCLLOW (0x0040)
4840 #define EUSCI_B0_I2C_STATW_UCSCLLOW__0 (0x0000)
4841 #define EUSCI_B0_I2C_STATW_UCSCLLOW__1 (0x0040)
4842 #define EUSCI_B0_I2C_STATW_UCSCLLOW__1_SCL_IS_HELD_LOW (0x0040)
4843 #define EUSCI_B0_I2C_TBCNT (HWREG16(0x4000200A))
4844 #define EUSCI_B0_I2C_TBCNT_UCTBCNT__M (0x00ff)
4845 #define EUSCI_B0_I2C_TXBUF (HWREG16(0x4000200E))
4846 #define EUSCI_B0_I2C_TXBUF_UCTXBUF__M (0x00ff)
4847 #define EUSCI_B0_SPI_BRW (HWREG16(0x40002006))
4848 #define EUSCI_B0_SPI_CTLW0 (HWREG16(0x40002000))
4849 #define EUSCI_B0_SPI_CTLW0_UC7BIT (0x1000)
4850 #define EUSCI_B0_SPI_CTLW0_UC7BIT__0 (0x0000)
4851 #define EUSCI_B0_SPI_CTLW0_UC7BIT__0_8_BIT_DATA (0x0000)
4852 #define EUSCI_B0_SPI_CTLW0_UC7BIT__1 (0x1000)
4853 #define EUSCI_B0_SPI_CTLW0_UC7BIT__1_7_BIT_DATA (0x1000)
4854 #define EUSCI_B0_SPI_CTLW0_UCCKPH (0x8000)
4855 #define EUSCI_B0_SPI_CTLW0_UCCKPH__0 (0x0000)
4856 #define EUSCI_B0_SPI_CTLW0_UCCKPH__1 (0x8000)
4857 #define EUSCI_B0_SPI_CTLW0_UCCKPL (0x4000)
4858 #define EUSCI_B0_SPI_CTLW0_UCCKPL__0 (0x0000)
4859 #define EUSCI_B0_SPI_CTLW0_UCCKPL__1 (0x4000)
4860 #define EUSCI_B0_SPI_CTLW0_UCMODE__0 (0x0000)
4861 #define EUSCI_B0_SPI_CTLW0_UCMODE__0_3_PIN_SPI (0x0000)
4862 #define EUSCI_B0_SPI_CTLW0_UCMODE__1 (0x0200)
4863 #define EUSCI_B0_SPI_CTLW0_UCMODE__2 (0x0400)
4864 #define EUSCI_B0_SPI_CTLW0_UCMODE__3 (0x0600)
4865 #define EUSCI_B0_SPI_CTLW0_UCMODE__3_I2C_MODE (0x0600)
4866 #define EUSCI_B0_SPI_CTLW0_UCMODE__M (0x0600)
4867 #define EUSCI_B0_SPI_CTLW0_UCMSB (0x2000)
4868 #define EUSCI_B0_SPI_CTLW0_UCMSB__0 (0x0000)
4869 #define EUSCI_B0_SPI_CTLW0_UCMSB__0_LSB_FIRST (0x0000)
4870 #define EUSCI_B0_SPI_CTLW0_UCMSB__1 (0x2000)
4871 #define EUSCI_B0_SPI_CTLW0_UCMSB__1_MSB_FIRST (0x2000)
4872 #define EUSCI_B0_SPI_CTLW0_UCMST (0x0800)
4873 #define EUSCI_B0_SPI_CTLW0_UCMST__0 (0x0000)
4874 #define EUSCI_B0_SPI_CTLW0_UCMST__0_SLAVE_MODE (0x0000)
4875 #define EUSCI_B0_SPI_CTLW0_UCMST__1 (0x0800)
4876 #define EUSCI_B0_SPI_CTLW0_UCMST__1_MASTER_MODE (0x0800)
4877 #define EUSCI_B0_SPI_CTLW0_UCSSEL__1 (0x0040)
4878 #define EUSCI_B0_SPI_CTLW0_UCSSEL__1_ACLK (0x0040)
4879 #define EUSCI_B0_SPI_CTLW0_UCSSEL__2 (0x0080)
4880 #define EUSCI_B0_SPI_CTLW0_UCSSEL__2_SMCLK (0x0080)
4881 #define EUSCI_B0_SPI_CTLW0_UCSSEL__3 (0x00c0)
4882 #define EUSCI_B0_SPI_CTLW0_UCSSEL__3_SMCLK (0x00c0)
4883 #define EUSCI_B0_SPI_CTLW0_UCSSEL__M (0x00c0)
4884 #define EUSCI_B0_SPI_CTLW0_UCSTEM (0x0002)
4885 #define EUSCI_B0_SPI_CTLW0_UCSTEM__0 (0x0000)
4886 #define EUSCI_B0_SPI_CTLW0_UCSTEM__1 (0x0002)
4887 #define EUSCI_B0_SPI_CTLW0_UCSWRST (0x0001)
4888 #define EUSCI_B0_SPI_CTLW0_UCSWRST__0 (0x0000)
4889 #define EUSCI_B0_SPI_CTLW0_UCSWRST__1 (0x0001)
4890 #define EUSCI_B0_SPI_CTLW0_UCSYNC (0x0100)
4891 #define EUSCI_B0_SPI_CTLW0_UCSYNC__0 (0x0000)
4892 #define EUSCI_B0_SPI_CTLW0_UCSYNC__1 (0x0100)
4893 #define EUSCI_B0_SPI_IE (HWREG16(0x4000202A))
4894 #define EUSCI_B0_SPI_IE_UCRXIE (0x0001)
4895 #define EUSCI_B0_SPI_IE_UCRXIE__0 (0x0000)
4896 #define EUSCI_B0_SPI_IE_UCRXIE__1 (0x0001)
4897 #define EUSCI_B0_SPI_IE_UCTXIE (0x0002)
4898 #define EUSCI_B0_SPI_IE_UCTXIE__0 (0x0000)
4899 #define EUSCI_B0_SPI_IE_UCTXIE__1 (0x0002)
4900 #define EUSCI_B0_SPI_IFG (HWREG16(0x4000202C))
4901 #define EUSCI_B0_SPI_IFG_UCRXIFG (0x0001)
4902 #define EUSCI_B0_SPI_IFG_UCRXIFG__0 (0x0000)
4903 #define EUSCI_B0_SPI_IFG_UCRXIFG__1 (0x0001)
4904 #define EUSCI_B0_SPI_IFG_UCTXIFG (0x0002)
4905 #define EUSCI_B0_SPI_IFG_UCTXIFG__0 (0x0000)
4906 #define EUSCI_B0_SPI_IFG_UCTXIFG__1 (0x0002)
4907 #define EUSCI_B0_SPI_IV (HWREG16(0x4000202E))
4908 #define EUSCI_B0_SPI_RXBUF (HWREG16(0x4000200C))
4909 #define EUSCI_B0_SPI_RXBUF_UCRXBUF__M (0x00ff)
4910 #define EUSCI_B0_SPI_STATW (HWREG16(0x40002008))
4911 #define EUSCI_B0_SPI_STATW_UCBUSY (0x0001)
4912 #define EUSCI_B0_SPI_STATW_UCBUSY__0 (0x0000)
4913 #define EUSCI_B0_SPI_STATW_UCBUSY__0_EUSCI_INACTIVE (0x0000)
4914 #define EUSCI_B0_SPI_STATW_UCBUSY__1 (0x0001)
4915 #define EUSCI_B0_SPI_STATW_UCFE (0x0040)
4916 #define EUSCI_B0_SPI_STATW_UCFE__0 (0x0000)
4917 #define EUSCI_B0_SPI_STATW_UCFE__0_NO_ERROR (0x0000)
4918 #define EUSCI_B0_SPI_STATW_UCFE__1 (0x0040)
4919 #define EUSCI_B0_SPI_STATW_UCLISTEN (0x0080)
4920 #define EUSCI_B0_SPI_STATW_UCLISTEN__0 (0x0000)
4921 #define EUSCI_B0_SPI_STATW_UCLISTEN__0_DISABLED (0x0000)
4922 #define EUSCI_B0_SPI_STATW_UCLISTEN__1 (0x0080)
4923 #define EUSCI_B0_SPI_STATW_UCOE (0x0020)
4924 #define EUSCI_B0_SPI_STATW_UCOE__0 (0x0000)
4925 #define EUSCI_B0_SPI_STATW_UCOE__0_NO_ERROR (0x0000)
4926 #define EUSCI_B0_SPI_STATW_UCOE__1 (0x0020)
4927 #define EUSCI_B0_SPI_TXBUF (HWREG16(0x4000200E))
4928 #define EUSCI_B0_SPI_TXBUF_UCTXBUF__M (0x00ff)
4929 #define EUSCI_B1_I2C_ADDMASK (HWREG16(0x4000241E))
4930 #define EUSCI_B1_I2C_ADDMASK_ADDMASK__M (0x03ff)
4931 #define EUSCI_B1_I2C_ADDRX (HWREG16(0x4000241C))
4932 #define EUSCI_B1_I2C_ADDRX_ADDRX__M (0x03ff)
4933 #define EUSCI_B1_I2C_BRW (HWREG16(0x40002406))
4934 #define EUSCI_B1_I2C_CTLW0 (HWREG16(0x40002400))
4935 #define EUSCI_B1_I2C_CTLW0_UCA10 (0x8000)
4936 #define EUSCI_B1_I2C_CTLW0_UCA10__0 (0x0000)
4937 #define EUSCI_B1_I2C_CTLW0_UCA10__1 (0x8000)
4938 #define EUSCI_B1_I2C_CTLW0_UCMM (0x2000)
4939 #define EUSCI_B1_I2C_CTLW0_UCMM__0 (0x0000)
4940 #define EUSCI_B1_I2C_CTLW0_UCMM__1 (0x2000)
4941 #define EUSCI_B1_I2C_CTLW0_UCMODE__0 (0x0000)
4942 #define EUSCI_B1_I2C_CTLW0_UCMODE__0_3_PIN_SPI (0x0000)
4943 #define EUSCI_B1_I2C_CTLW0_UCMODE__1 (0x0200)
4944 #define EUSCI_B1_I2C_CTLW0_UCMODE__2 (0x0400)
4945 #define EUSCI_B1_I2C_CTLW0_UCMODE__3 (0x0600)
4946 #define EUSCI_B1_I2C_CTLW0_UCMODE__3_I2C_MODE (0x0600)
4947 #define EUSCI_B1_I2C_CTLW0_UCMODE__M (0x0600)
4948 #define EUSCI_B1_I2C_CTLW0_UCMST (0x0800)
4949 #define EUSCI_B1_I2C_CTLW0_UCMST__0 (0x0000)
4950 #define EUSCI_B1_I2C_CTLW0_UCMST__0_SLAVE_MODE (0x0000)
4951 #define EUSCI_B1_I2C_CTLW0_UCMST__1 (0x0800)
4952 #define EUSCI_B1_I2C_CTLW0_UCMST__1_MASTER_MODE (0x0800)
4953 #define EUSCI_B1_I2C_CTLW0_UCSLA10 (0x4000)
4954 #define EUSCI_B1_I2C_CTLW0_UCSLA10__0 (0x0000)
4955 #define EUSCI_B1_I2C_CTLW0_UCSLA10__1 (0x4000)
4956 #define EUSCI_B1_I2C_CTLW0_UCSSEL__0 (0x0000)
4957 #define EUSCI_B1_I2C_CTLW0_UCSSEL__0_UCLKI (0x0000)
4958 #define EUSCI_B1_I2C_CTLW0_UCSSEL__1 (0x0040)
4959 #define EUSCI_B1_I2C_CTLW0_UCSSEL__1_ACLK (0x0040)
4960 #define EUSCI_B1_I2C_CTLW0_UCSSEL__2 (0x0080)
4961 #define EUSCI_B1_I2C_CTLW0_UCSSEL__2_SMCLK (0x0080)
4962 #define EUSCI_B1_I2C_CTLW0_UCSSEL__3 (0x00c0)
4963 #define EUSCI_B1_I2C_CTLW0_UCSSEL__3_SMCLK (0x00c0)
4964 #define EUSCI_B1_I2C_CTLW0_UCSSEL__M (0x00c0)
4965 #define EUSCI_B1_I2C_CTLW0_UCSWRST (0x0001)
4966 #define EUSCI_B1_I2C_CTLW0_UCSWRST__0 (0x0000)
4967 #define EUSCI_B1_I2C_CTLW0_UCSWRST__1 (0x0001)
4968 #define EUSCI_B1_I2C_CTLW0_UCSYNC (0x0100)
4969 #define EUSCI_B1_I2C_CTLW0_UCTR (0x0010)
4970 #define EUSCI_B1_I2C_CTLW0_UCTR__0 (0x0000)
4971 #define EUSCI_B1_I2C_CTLW0_UCTR__0_RECEIVER (0x0000)
4972 #define EUSCI_B1_I2C_CTLW0_UCTR__1 (0x0010)
4973 #define EUSCI_B1_I2C_CTLW0_UCTR__1_TRANSMITTER (0x0010)
4974 #define EUSCI_B1_I2C_CTLW0_UCTXACK (0x0020)
4975 #define EUSCI_B1_I2C_CTLW0_UCTXACK__0 (0x0000)
4976 #define EUSCI_B1_I2C_CTLW0_UCTXACK__1 (0x0020)
4977 #define EUSCI_B1_I2C_CTLW0_UCTXNACK (0x0008)
4978 #define EUSCI_B1_I2C_CTLW0_UCTXNACK__0 (0x0000)
4979 #define EUSCI_B1_I2C_CTLW0_UCTXNACK__1 (0x0008)
4980 #define EUSCI_B1_I2C_CTLW0_UCTXNACK__1_GENERATE_NACK (0x0008)
4981 #define EUSCI_B1_I2C_CTLW0_UCTXSTP (0x0004)
4982 #define EUSCI_B1_I2C_CTLW0_UCTXSTP__0 (0x0000)
4983 #define EUSCI_B1_I2C_CTLW0_UCTXSTP__1 (0x0004)
4984 #define EUSCI_B1_I2C_CTLW0_UCTXSTP__1_GENERATE_STOP (0x0004)
4985 #define EUSCI_B1_I2C_CTLW0_UCTXSTT (0x0002)
4986 #define EUSCI_B1_I2C_CTLW0_UCTXSTT__0 (0x0000)
4987 #define EUSCI_B1_I2C_CTLW0_UCTXSTT__1 (0x0002)
4988 #define EUSCI_B1_I2C_CTLW1 (HWREG16(0x40002402))
4989 #define EUSCI_B1_I2C_CTLW1_UCASTP__0 (0x0000)
4990 #define EUSCI_B1_I2C_CTLW1_UCASTP__1 (0x0004)
4991 #define EUSCI_B1_I2C_CTLW1_UCASTP__2 (0x0008)
4992 #define EUSCI_B1_I2C_CTLW1_UCASTP__M (0x000c)
4993 #define EUSCI_B1_I2C_CTLW1_UCCLTO__0 (0x0000)
4994 #define EUSCI_B1_I2C_CTLW1_UCCLTO__1 (0x0040)
4995 #define EUSCI_B1_I2C_CTLW1_UCCLTO__2 (0x0080)
4996 #define EUSCI_B1_I2C_CTLW1_UCCLTO__3 (0x00c0)
4997 #define EUSCI_B1_I2C_CTLW1_UCCLTO__M (0x00c0)
4998 #define EUSCI_B1_I2C_CTLW1_UCETXINT (0x0100)
4999 #define EUSCI_B1_I2C_CTLW1_UCETXINT__0 (0x0000)
5000 #define EUSCI_B1_I2C_CTLW1_UCETXINT__1 (0x0100)
5001 #define EUSCI_B1_I2C_CTLW1_UCGLIT__0 (0x0000)
5002 #define EUSCI_B1_I2C_CTLW1_UCGLIT__0_50_NS (0x0000)
5003 #define EUSCI_B1_I2C_CTLW1_UCGLIT__1 (0x0001)
5004 #define EUSCI_B1_I2C_CTLW1_UCGLIT__1_25_NS (0x0001)
5005 #define EUSCI_B1_I2C_CTLW1_UCGLIT__2 (0x0002)
5006 #define EUSCI_B1_I2C_CTLW1_UCGLIT__2_12_5_NS (0x0002)
5007 #define EUSCI_B1_I2C_CTLW1_UCGLIT__3 (0x0003)
5008 #define EUSCI_B1_I2C_CTLW1_UCGLIT__3_6_25_NS (0x0003)
5009 #define EUSCI_B1_I2C_CTLW1_UCGLIT__M (0x0003)
5010 #define EUSCI_B1_I2C_CTLW1_UCSTPNACK (0x0020)
5011 #define EUSCI_B1_I2C_CTLW1_UCSTPNACK__0 (0x0000)
5012 #define EUSCI_B1_I2C_CTLW1_UCSTPNACK__1 (0x0020)
5013 #define EUSCI_B1_I2C_CTLW1_UCSWACK (0x0010)
5014 #define EUSCI_B1_I2C_CTLW1_UCSWACK__0 (0x0000)
5015 #define EUSCI_B1_I2C_CTLW1_UCSWACK__1 (0x0010)
5016 #define EUSCI_B1_I2C_I2COA0 (HWREG16(0x40002414))
5017 #define EUSCI_B1_I2C_I2COA0_I2COA__M (0x03ff)
5018 #define EUSCI_B1_I2C_I2COA0_UCGCEN (0x8000)
5019 #define EUSCI_B1_I2C_I2COA0_UCGCEN__0 (0x0000)
5020 #define EUSCI_B1_I2C_I2COA0_UCGCEN__1 (0x8000)
5021 #define EUSCI_B1_I2C_I2COA0_UCOAEN (0x0400)
5022 #define EUSCI_B1_I2C_I2COA0_UCOAEN__0 (0x0000)
5023 #define EUSCI_B1_I2C_I2COA0_UCOAEN__1 (0x0400)
5024 #define EUSCI_B1_I2C_I2COA1 (HWREG16(0x40002416))
5025 #define EUSCI_B1_I2C_I2COA1_I2COA1__M (0x03ff)
5026 #define EUSCI_B1_I2C_I2COA1_UCOAEN (0x0400)
5027 #define EUSCI_B1_I2C_I2COA1_UCOAEN__0 (0x0000)
5028 #define EUSCI_B1_I2C_I2COA1_UCOAEN__1 (0x0400)
5029 #define EUSCI_B1_I2C_I2COA2 (HWREG16(0x40002418))
5030 #define EUSCI_B1_I2C_I2COA2_I2COA2__M (0x03ff)
5031 #define EUSCI_B1_I2C_I2COA2_UCOAEN (0x0400)
5032 #define EUSCI_B1_I2C_I2COA2_UCOAEN__0 (0x0000)
5033 #define EUSCI_B1_I2C_I2COA2_UCOAEN__1 (0x0400)
5034 #define EUSCI_B1_I2C_I2COA3 (HWREG16(0x4000241A))
5035 #define EUSCI_B1_I2C_I2COA3_I2COA3__M (0x03ff)
5036 #define EUSCI_B1_I2C_I2COA3_UCOAEN (0x0400)
5037 #define EUSCI_B1_I2C_I2COA3_UCOAEN__0 (0x0000)
5038 #define EUSCI_B1_I2C_I2COA3_UCOAEN__1 (0x0400)
5039 #define EUSCI_B1_I2C_I2CSA (HWREG16(0x40002420))
5040 #define EUSCI_B1_I2C_I2CSA_I2CSA__M (0x03ff)
5041 #define EUSCI_B1_I2C_IE (HWREG16(0x4000242A))
5042 #define EUSCI_B1_I2C_IE_UCALIE (0x0010)
5043 #define EUSCI_B1_I2C_IE_UCALIE__0 (0x0000)
5044 #define EUSCI_B1_I2C_IE_UCALIE__1 (0x0010)
5045 #define EUSCI_B1_I2C_IE_UCBCNTIE (0x0040)
5046 #define EUSCI_B1_I2C_IE_UCBCNTIE__0 (0x0000)
5047 #define EUSCI_B1_I2C_IE_UCBCNTIE__1 (0x0040)
5048 #define EUSCI_B1_I2C_IE_UCBIT9IE (0x4000)
5049 #define EUSCI_B1_I2C_IE_UCBIT9IE__0 (0x0000)
5050 #define EUSCI_B1_I2C_IE_UCBIT9IE__1 (0x4000)
5051 #define EUSCI_B1_I2C_IE_UCCLTOIE (0x0080)
5052 #define EUSCI_B1_I2C_IE_UCCLTOIE__0 (0x0000)
5053 #define EUSCI_B1_I2C_IE_UCCLTOIE__1 (0x0080)
5054 #define EUSCI_B1_I2C_IE_UCNACKIE (0x0020)
5055 #define EUSCI_B1_I2C_IE_UCNACKIE__0 (0x0000)
5056 #define EUSCI_B1_I2C_IE_UCNACKIE__1 (0x0020)
5057 #define EUSCI_B1_I2C_IE_UCRXIE0 (0x0001)
5058 #define EUSCI_B1_I2C_IE_UCRXIE0__0 (0x0000)
5059 #define EUSCI_B1_I2C_IE_UCRXIE0__1 (0x0001)
5060 #define EUSCI_B1_I2C_IE_UCRXIE1 (0x0100)
5061 #define EUSCI_B1_I2C_IE_UCRXIE1__0 (0x0000)
5062 #define EUSCI_B1_I2C_IE_UCRXIE1__1 (0x0100)
5063 #define EUSCI_B1_I2C_IE_UCRXIE2 (0x0400)
5064 #define EUSCI_B1_I2C_IE_UCRXIE2__0 (0x0000)
5065 #define EUSCI_B1_I2C_IE_UCRXIE2__1 (0x0400)
5066 #define EUSCI_B1_I2C_IE_UCRXIE3 (0x1000)
5067 #define EUSCI_B1_I2C_IE_UCRXIE3__0 (0x0000)
5068 #define EUSCI_B1_I2C_IE_UCRXIE3__1 (0x1000)
5069 #define EUSCI_B1_I2C_IE_UCSTPIE (0x0008)
5070 #define EUSCI_B1_I2C_IE_UCSTPIE__0 (0x0000)
5071 #define EUSCI_B1_I2C_IE_UCSTPIE__1 (0x0008)
5072 #define EUSCI_B1_I2C_IE_UCSTTIE (0x0004)
5073 #define EUSCI_B1_I2C_IE_UCSTTIE__0 (0x0000)
5074 #define EUSCI_B1_I2C_IE_UCSTTIE__1 (0x0004)
5075 #define EUSCI_B1_I2C_IE_UCTXIE0 (0x0002)
5076 #define EUSCI_B1_I2C_IE_UCTXIE0__0 (0x0000)
5077 #define EUSCI_B1_I2C_IE_UCTXIE0__1 (0x0002)
5078 #define EUSCI_B1_I2C_IE_UCTXIE1 (0x0200)
5079 #define EUSCI_B1_I2C_IE_UCTXIE1__0 (0x0000)
5080 #define EUSCI_B1_I2C_IE_UCTXIE1__1 (0x0200)
5081 #define EUSCI_B1_I2C_IE_UCTXIE2 (0x0800)
5082 #define EUSCI_B1_I2C_IE_UCTXIE2__0 (0x0000)
5083 #define EUSCI_B1_I2C_IE_UCTXIE2__1 (0x0800)
5084 #define EUSCI_B1_I2C_IE_UCTXIE3 (0x2000)
5085 #define EUSCI_B1_I2C_IE_UCTXIE3__0 (0x0000)
5086 #define EUSCI_B1_I2C_IE_UCTXIE3__1 (0x2000)
5087 #define EUSCI_B1_I2C_IFG (HWREG16(0x4000242C))
5088 #define EUSCI_B1_I2C_IFG_UCALIFG (0x0010)
5089 #define EUSCI_B1_I2C_IFG_UCALIFG__0 (0x0000)
5090 #define EUSCI_B1_I2C_IFG_UCALIFG__1 (0x0010)
5091 #define EUSCI_B1_I2C_IFG_UCBCNTIFG (0x0040)
5092 #define EUSCI_B1_I2C_IFG_UCBCNTIFG__0 (0x0000)
5093 #define EUSCI_B1_I2C_IFG_UCBCNTIFG__1 (0x0040)
5094 #define EUSCI_B1_I2C_IFG_UCBIT9IFG (0x4000)
5095 #define EUSCI_B1_I2C_IFG_UCBIT9IFG__0 (0x0000)
5096 #define EUSCI_B1_I2C_IFG_UCBIT9IFG__1 (0x4000)
5097 #define EUSCI_B1_I2C_IFG_UCCLTOIFG (0x0080)
5098 #define EUSCI_B1_I2C_IFG_UCCLTOIFG__0 (0x0000)
5099 #define EUSCI_B1_I2C_IFG_UCCLTOIFG__1 (0x0080)
5100 #define EUSCI_B1_I2C_IFG_UCNACKIFG (0x0020)
5101 #define EUSCI_B1_I2C_IFG_UCNACKIFG__0 (0x0000)
5102 #define EUSCI_B1_I2C_IFG_UCNACKIFG__1 (0x0020)
5103 #define EUSCI_B1_I2C_IFG_UCRXIFG0 (0x0001)
5104 #define EUSCI_B1_I2C_IFG_UCRXIFG0__0 (0x0000)
5105 #define EUSCI_B1_I2C_IFG_UCRXIFG0__1 (0x0001)
5106 #define EUSCI_B1_I2C_IFG_UCRXIFG1 (0x0100)
5107 #define EUSCI_B1_I2C_IFG_UCRXIFG1__0 (0x0000)
5108 #define EUSCI_B1_I2C_IFG_UCRXIFG1__1 (0x0100)
5109 #define EUSCI_B1_I2C_IFG_UCRXIFG2 (0x0400)
5110 #define EUSCI_B1_I2C_IFG_UCRXIFG2__0 (0x0000)
5111 #define EUSCI_B1_I2C_IFG_UCRXIFG2__1 (0x0400)
5112 #define EUSCI_B1_I2C_IFG_UCRXIFG3 (0x1000)
5113 #define EUSCI_B1_I2C_IFG_UCRXIFG3__0 (0x0000)
5114 #define EUSCI_B1_I2C_IFG_UCRXIFG3__1 (0x1000)
5115 #define EUSCI_B1_I2C_IFG_UCSTPIFG (0x0008)
5116 #define EUSCI_B1_I2C_IFG_UCSTPIFG__0 (0x0000)
5117 #define EUSCI_B1_I2C_IFG_UCSTPIFG__1 (0x0008)
5118 #define EUSCI_B1_I2C_IFG_UCSTTIFG (0x0004)
5119 #define EUSCI_B1_I2C_IFG_UCSTTIFG__0 (0x0000)
5120 #define EUSCI_B1_I2C_IFG_UCSTTIFG__1 (0x0004)
5121 #define EUSCI_B1_I2C_IFG_UCTXIFG0 (0x0002)
5122 #define EUSCI_B1_I2C_IFG_UCTXIFG0__0 (0x0000)
5123 #define EUSCI_B1_I2C_IFG_UCTXIFG0__1 (0x0002)
5124 #define EUSCI_B1_I2C_IFG_UCTXIFG1 (0x0200)
5125 #define EUSCI_B1_I2C_IFG_UCTXIFG1__0 (0x0000)
5126 #define EUSCI_B1_I2C_IFG_UCTXIFG1__1 (0x0200)
5127 #define EUSCI_B1_I2C_IFG_UCTXIFG2 (0x0800)
5128 #define EUSCI_B1_I2C_IFG_UCTXIFG2__0 (0x0000)
5129 #define EUSCI_B1_I2C_IFG_UCTXIFG2__1 (0x0800)
5130 #define EUSCI_B1_I2C_IFG_UCTXIFG3 (0x2000)
5131 #define EUSCI_B1_I2C_IFG_UCTXIFG3__0 (0x0000)
5132 #define EUSCI_B1_I2C_IFG_UCTXIFG3__1 (0x2000)
5133 #define EUSCI_B1_I2C_IV (HWREG16(0x4000242E))
5134 #define EUSCI_B1_I2C_RXBUF (HWREG16(0x4000240C))
5135 #define EUSCI_B1_I2C_RXBUF_UCRXBUF__M (0x00ff)
5136 #define EUSCI_B1_I2C_STATW (HWREG16(0x40002408))
5137 #define EUSCI_B1_I2C_STATW_UCBBUSY (0x0010)
5138 #define EUSCI_B1_I2C_STATW_UCBBUSY__0 (0x0000)
5139 #define EUSCI_B1_I2C_STATW_UCBBUSY__0_BUS_INACTIVE (0x0000)
5140 #define EUSCI_B1_I2C_STATW_UCBBUSY__1 (0x0010)
5141 #define EUSCI_B1_I2C_STATW_UCBBUSY__1_BUS_BUSY (0x0010)
5142 #define EUSCI_B1_I2C_STATW_UCBCNT__M (0xff00)
5143 #define EUSCI_B1_I2C_STATW_UCGC (0x0020)
5144 #define EUSCI_B1_I2C_STATW_UCGC__0 (0x0000)
5145 #define EUSCI_B1_I2C_STATW_UCGC__1 (0x0020)
5146 #define EUSCI_B1_I2C_STATW_UCSCLLOW (0x0040)
5147 #define EUSCI_B1_I2C_STATW_UCSCLLOW__0 (0x0000)
5148 #define EUSCI_B1_I2C_STATW_UCSCLLOW__1 (0x0040)
5149 #define EUSCI_B1_I2C_STATW_UCSCLLOW__1_SCL_IS_HELD_LOW (0x0040)
5150 #define EUSCI_B1_I2C_TBCNT (HWREG16(0x4000240A))
5151 #define EUSCI_B1_I2C_TBCNT_UCTBCNT__M (0x00ff)
5152 #define EUSCI_B1_I2C_TXBUF (HWREG16(0x4000240E))
5153 #define EUSCI_B1_I2C_TXBUF_UCTXBUF__M (0x00ff)
5154 #define EUSCI_B1_SPI_BRW (HWREG16(0x40002406))
5155 #define EUSCI_B1_SPI_CTLW0 (HWREG16(0x40002400))
5156 #define EUSCI_B1_SPI_CTLW0_UC7BIT (0x1000)
5157 #define EUSCI_B1_SPI_CTLW0_UC7BIT__0 (0x0000)
5158 #define EUSCI_B1_SPI_CTLW0_UC7BIT__0_8_BIT_DATA (0x0000)
5159 #define EUSCI_B1_SPI_CTLW0_UC7BIT__1 (0x1000)
5160 #define EUSCI_B1_SPI_CTLW0_UC7BIT__1_7_BIT_DATA (0x1000)
5161 #define EUSCI_B1_SPI_CTLW0_UCCKPH (0x8000)
5162 #define EUSCI_B1_SPI_CTLW0_UCCKPH__0 (0x0000)
5163 #define EUSCI_B1_SPI_CTLW0_UCCKPH__1 (0x8000)
5164 #define EUSCI_B1_SPI_CTLW0_UCCKPL (0x4000)
5165 #define EUSCI_B1_SPI_CTLW0_UCCKPL__0 (0x0000)
5166 #define EUSCI_B1_SPI_CTLW0_UCCKPL__1 (0x4000)
5167 #define EUSCI_B1_SPI_CTLW0_UCMODE__0 (0x0000)
5168 #define EUSCI_B1_SPI_CTLW0_UCMODE__0_3_PIN_SPI (0x0000)
5169 #define EUSCI_B1_SPI_CTLW0_UCMODE__1 (0x0200)
5170 #define EUSCI_B1_SPI_CTLW0_UCMODE__2 (0x0400)
5171 #define EUSCI_B1_SPI_CTLW0_UCMODE__3 (0x0600)
5172 #define EUSCI_B1_SPI_CTLW0_UCMODE__3_I2C_MODE (0x0600)
5173 #define EUSCI_B1_SPI_CTLW0_UCMODE__M (0x0600)
5174 #define EUSCI_B1_SPI_CTLW0_UCMSB (0x2000)
5175 #define EUSCI_B1_SPI_CTLW0_UCMSB__0 (0x0000)
5176 #define EUSCI_B1_SPI_CTLW0_UCMSB__0_LSB_FIRST (0x0000)
5177 #define EUSCI_B1_SPI_CTLW0_UCMSB__1 (0x2000)
5178 #define EUSCI_B1_SPI_CTLW0_UCMSB__1_MSB_FIRST (0x2000)
5179 #define EUSCI_B1_SPI_CTLW0_UCMST (0x0800)
5180 #define EUSCI_B1_SPI_CTLW0_UCMST__0 (0x0000)
5181 #define EUSCI_B1_SPI_CTLW0_UCMST__0_SLAVE_MODE (0x0000)
5182 #define EUSCI_B1_SPI_CTLW0_UCMST__1 (0x0800)
5183 #define EUSCI_B1_SPI_CTLW0_UCMST__1_MASTER_MODE (0x0800)
5184 #define EUSCI_B1_SPI_CTLW0_UCSSEL__1 (0x0040)
5185 #define EUSCI_B1_SPI_CTLW0_UCSSEL__1_ACLK (0x0040)
5186 #define EUSCI_B1_SPI_CTLW0_UCSSEL__2 (0x0080)
5187 #define EUSCI_B1_SPI_CTLW0_UCSSEL__2_SMCLK (0x0080)
5188 #define EUSCI_B1_SPI_CTLW0_UCSSEL__3 (0x00c0)
5189 #define EUSCI_B1_SPI_CTLW0_UCSSEL__3_SMCLK (0x00c0)
5190 #define EUSCI_B1_SPI_CTLW0_UCSSEL__M (0x00c0)
5191 #define EUSCI_B1_SPI_CTLW0_UCSTEM (0x0002)
5192 #define EUSCI_B1_SPI_CTLW0_UCSTEM__0 (0x0000)
5193 #define EUSCI_B1_SPI_CTLW0_UCSTEM__1 (0x0002)
5194 #define EUSCI_B1_SPI_CTLW0_UCSWRST (0x0001)
5195 #define EUSCI_B1_SPI_CTLW0_UCSWRST__0 (0x0000)
5196 #define EUSCI_B1_SPI_CTLW0_UCSWRST__1 (0x0001)
5197 #define EUSCI_B1_SPI_CTLW0_UCSYNC (0x0100)
5198 #define EUSCI_B1_SPI_CTLW0_UCSYNC__0 (0x0000)
5199 #define EUSCI_B1_SPI_CTLW0_UCSYNC__1 (0x0100)
5200 #define EUSCI_B1_SPI_IE (HWREG16(0x4000242A))
5201 #define EUSCI_B1_SPI_IE_UCRXIE (0x0001)
5202 #define EUSCI_B1_SPI_IE_UCRXIE__0 (0x0000)
5203 #define EUSCI_B1_SPI_IE_UCRXIE__1 (0x0001)
5204 #define EUSCI_B1_SPI_IE_UCTXIE (0x0002)
5205 #define EUSCI_B1_SPI_IE_UCTXIE__0 (0x0000)
5206 #define EUSCI_B1_SPI_IE_UCTXIE__1 (0x0002)
5207 #define EUSCI_B1_SPI_IFG (HWREG16(0x4000242C))
5208 #define EUSCI_B1_SPI_IFG_UCRXIFG (0x0001)
5209 #define EUSCI_B1_SPI_IFG_UCRXIFG__0 (0x0000)
5210 #define EUSCI_B1_SPI_IFG_UCRXIFG__1 (0x0001)
5211 #define EUSCI_B1_SPI_IFG_UCTXIFG (0x0002)
5212 #define EUSCI_B1_SPI_IFG_UCTXIFG__0 (0x0000)
5213 #define EUSCI_B1_SPI_IFG_UCTXIFG__1 (0x0002)
5214 #define EUSCI_B1_SPI_IV (HWREG16(0x4000242E))
5215 #define EUSCI_B1_SPI_RXBUF (HWREG16(0x4000240C))
5216 #define EUSCI_B1_SPI_RXBUF_UCRXBUF__M (0x00ff)
5217 #define EUSCI_B1_SPI_STATW (HWREG16(0x40002408))
5218 #define EUSCI_B1_SPI_STATW_UCBUSY (0x0001)
5219 #define EUSCI_B1_SPI_STATW_UCBUSY__0 (0x0000)
5220 #define EUSCI_B1_SPI_STATW_UCBUSY__0_EUSCI_INACTIVE (0x0000)
5221 #define EUSCI_B1_SPI_STATW_UCBUSY__1 (0x0001)
5222 #define EUSCI_B1_SPI_STATW_UCFE (0x0040)
5223 #define EUSCI_B1_SPI_STATW_UCFE__0 (0x0000)
5224 #define EUSCI_B1_SPI_STATW_UCFE__0_NO_ERROR (0x0000)
5225 #define EUSCI_B1_SPI_STATW_UCFE__1 (0x0040)
5226 #define EUSCI_B1_SPI_STATW_UCLISTEN (0x0080)
5227 #define EUSCI_B1_SPI_STATW_UCLISTEN__0 (0x0000)
5228 #define EUSCI_B1_SPI_STATW_UCLISTEN__0_DISABLED (0x0000)
5229 #define EUSCI_B1_SPI_STATW_UCLISTEN__1 (0x0080)
5230 #define EUSCI_B1_SPI_STATW_UCOE (0x0020)
5231 #define EUSCI_B1_SPI_STATW_UCOE__0 (0x0000)
5232 #define EUSCI_B1_SPI_STATW_UCOE__0_NO_ERROR (0x0000)
5233 #define EUSCI_B1_SPI_STATW_UCOE__1 (0x0020)
5234 #define EUSCI_B1_SPI_TXBUF (HWREG16(0x4000240E))
5235 #define EUSCI_B1_SPI_TXBUF_UCTXBUF__M (0x00ff)
5236 #define EUSCI_B2_I2C_ADDMASK (HWREG16(0x4000281E))
5237 #define EUSCI_B2_I2C_ADDMASK_ADDMASK__M (0x03ff)
5238 #define EUSCI_B2_I2C_ADDRX (HWREG16(0x4000281C))
5239 #define EUSCI_B2_I2C_ADDRX_ADDRX__M (0x03ff)
5240 #define EUSCI_B2_I2C_BRW (HWREG16(0x40002806))
5241 #define EUSCI_B2_I2C_CTLW0 (HWREG16(0x40002800))
5242 #define EUSCI_B2_I2C_CTLW0_UCA10 (0x8000)
5243 #define EUSCI_B2_I2C_CTLW0_UCA10__0 (0x0000)
5244 #define EUSCI_B2_I2C_CTLW0_UCA10__1 (0x8000)
5245 #define EUSCI_B2_I2C_CTLW0_UCMM (0x2000)
5246 #define EUSCI_B2_I2C_CTLW0_UCMM__0 (0x0000)
5247 #define EUSCI_B2_I2C_CTLW0_UCMM__1 (0x2000)
5248 #define EUSCI_B2_I2C_CTLW0_UCMODE__0 (0x0000)
5249 #define EUSCI_B2_I2C_CTLW0_UCMODE__0_3_PIN_SPI (0x0000)
5250 #define EUSCI_B2_I2C_CTLW0_UCMODE__1 (0x0200)
5251 #define EUSCI_B2_I2C_CTLW0_UCMODE__2 (0x0400)
5252 #define EUSCI_B2_I2C_CTLW0_UCMODE__3 (0x0600)
5253 #define EUSCI_B2_I2C_CTLW0_UCMODE__3_I2C_MODE (0x0600)
5254 #define EUSCI_B2_I2C_CTLW0_UCMODE__M (0x0600)
5255 #define EUSCI_B2_I2C_CTLW0_UCMST (0x0800)
5256 #define EUSCI_B2_I2C_CTLW0_UCMST__0 (0x0000)
5257 #define EUSCI_B2_I2C_CTLW0_UCMST__0_SLAVE_MODE (0x0000)
5258 #define EUSCI_B2_I2C_CTLW0_UCMST__1 (0x0800)
5259 #define EUSCI_B2_I2C_CTLW0_UCMST__1_MASTER_MODE (0x0800)
5260 #define EUSCI_B2_I2C_CTLW0_UCSLA10 (0x4000)
5261 #define EUSCI_B2_I2C_CTLW0_UCSLA10__0 (0x0000)
5262 #define EUSCI_B2_I2C_CTLW0_UCSLA10__1 (0x4000)
5263 #define EUSCI_B2_I2C_CTLW0_UCSSEL__0 (0x0000)
5264 #define EUSCI_B2_I2C_CTLW0_UCSSEL__0_UCLKI (0x0000)
5265 #define EUSCI_B2_I2C_CTLW0_UCSSEL__1 (0x0040)
5266 #define EUSCI_B2_I2C_CTLW0_UCSSEL__1_ACLK (0x0040)
5267 #define EUSCI_B2_I2C_CTLW0_UCSSEL__2 (0x0080)
5268 #define EUSCI_B2_I2C_CTLW0_UCSSEL__2_SMCLK (0x0080)
5269 #define EUSCI_B2_I2C_CTLW0_UCSSEL__3 (0x00c0)
5270 #define EUSCI_B2_I2C_CTLW0_UCSSEL__3_SMCLK (0x00c0)
5271 #define EUSCI_B2_I2C_CTLW0_UCSSEL__M (0x00c0)
5272 #define EUSCI_B2_I2C_CTLW0_UCSWRST (0x0001)
5273 #define EUSCI_B2_I2C_CTLW0_UCSWRST__0 (0x0000)
5274 #define EUSCI_B2_I2C_CTLW0_UCSWRST__1 (0x0001)
5275 #define EUSCI_B2_I2C_CTLW0_UCSYNC (0x0100)
5276 #define EUSCI_B2_I2C_CTLW0_UCTR (0x0010)
5277 #define EUSCI_B2_I2C_CTLW0_UCTR__0 (0x0000)
5278 #define EUSCI_B2_I2C_CTLW0_UCTR__0_RECEIVER (0x0000)
5279 #define EUSCI_B2_I2C_CTLW0_UCTR__1 (0x0010)
5280 #define EUSCI_B2_I2C_CTLW0_UCTR__1_TRANSMITTER (0x0010)
5281 #define EUSCI_B2_I2C_CTLW0_UCTXACK (0x0020)
5282 #define EUSCI_B2_I2C_CTLW0_UCTXACK__0 (0x0000)
5283 #define EUSCI_B2_I2C_CTLW0_UCTXACK__1 (0x0020)
5284 #define EUSCI_B2_I2C_CTLW0_UCTXNACK (0x0008)
5285 #define EUSCI_B2_I2C_CTLW0_UCTXNACK__0 (0x0000)
5286 #define EUSCI_B2_I2C_CTLW0_UCTXNACK__1 (0x0008)
5287 #define EUSCI_B2_I2C_CTLW0_UCTXNACK__1_GENERATE_NACK (0x0008)
5288 #define EUSCI_B2_I2C_CTLW0_UCTXSTP (0x0004)
5289 #define EUSCI_B2_I2C_CTLW0_UCTXSTP__0 (0x0000)
5290 #define EUSCI_B2_I2C_CTLW0_UCTXSTP__1 (0x0004)
5291 #define EUSCI_B2_I2C_CTLW0_UCTXSTP__1_GENERATE_STOP (0x0004)
5292 #define EUSCI_B2_I2C_CTLW0_UCTXSTT (0x0002)
5293 #define EUSCI_B2_I2C_CTLW0_UCTXSTT__0 (0x0000)
5294 #define EUSCI_B2_I2C_CTLW0_UCTXSTT__1 (0x0002)
5295 #define EUSCI_B2_I2C_CTLW1 (HWREG16(0x40002802))
5296 #define EUSCI_B2_I2C_CTLW1_UCASTP__0 (0x0000)
5297 #define EUSCI_B2_I2C_CTLW1_UCASTP__1 (0x0004)
5298 #define EUSCI_B2_I2C_CTLW1_UCASTP__2 (0x0008)
5299 #define EUSCI_B2_I2C_CTLW1_UCASTP__M (0x000c)
5300 #define EUSCI_B2_I2C_CTLW1_UCCLTO__0 (0x0000)
5301 #define EUSCI_B2_I2C_CTLW1_UCCLTO__1 (0x0040)
5302 #define EUSCI_B2_I2C_CTLW1_UCCLTO__2 (0x0080)
5303 #define EUSCI_B2_I2C_CTLW1_UCCLTO__3 (0x00c0)
5304 #define EUSCI_B2_I2C_CTLW1_UCCLTO__M (0x00c0)
5305 #define EUSCI_B2_I2C_CTLW1_UCETXINT (0x0100)
5306 #define EUSCI_B2_I2C_CTLW1_UCETXINT__0 (0x0000)
5307 #define EUSCI_B2_I2C_CTLW1_UCETXINT__1 (0x0100)
5308 #define EUSCI_B2_I2C_CTLW1_UCGLIT__0 (0x0000)
5309 #define EUSCI_B2_I2C_CTLW1_UCGLIT__0_50_NS (0x0000)
5310 #define EUSCI_B2_I2C_CTLW1_UCGLIT__1 (0x0001)
5311 #define EUSCI_B2_I2C_CTLW1_UCGLIT__1_25_NS (0x0001)
5312 #define EUSCI_B2_I2C_CTLW1_UCGLIT__2 (0x0002)
5313 #define EUSCI_B2_I2C_CTLW1_UCGLIT__2_12_5_NS (0x0002)
5314 #define EUSCI_B2_I2C_CTLW1_UCGLIT__3 (0x0003)
5315 #define EUSCI_B2_I2C_CTLW1_UCGLIT__3_6_25_NS (0x0003)
5316 #define EUSCI_B2_I2C_CTLW1_UCGLIT__M (0x0003)
5317 #define EUSCI_B2_I2C_CTLW1_UCSTPNACK (0x0020)
5318 #define EUSCI_B2_I2C_CTLW1_UCSTPNACK__0 (0x0000)
5319 #define EUSCI_B2_I2C_CTLW1_UCSTPNACK__1 (0x0020)
5320 #define EUSCI_B2_I2C_CTLW1_UCSWACK (0x0010)
5321 #define EUSCI_B2_I2C_CTLW1_UCSWACK__0 (0x0000)
5322 #define EUSCI_B2_I2C_CTLW1_UCSWACK__1 (0x0010)
5323 #define EUSCI_B2_I2C_I2COA0 (HWREG16(0x40002814))
5324 #define EUSCI_B2_I2C_I2COA0_I2COA__M (0x03ff)
5325 #define EUSCI_B2_I2C_I2COA0_UCGCEN (0x8000)
5326 #define EUSCI_B2_I2C_I2COA0_UCGCEN__0 (0x0000)
5327 #define EUSCI_B2_I2C_I2COA0_UCGCEN__1 (0x8000)
5328 #define EUSCI_B2_I2C_I2COA0_UCOAEN (0x0400)
5329 #define EUSCI_B2_I2C_I2COA0_UCOAEN__0 (0x0000)
5330 #define EUSCI_B2_I2C_I2COA0_UCOAEN__1 (0x0400)
5331 #define EUSCI_B2_I2C_I2COA1 (HWREG16(0x40002816))
5332 #define EUSCI_B2_I2C_I2COA1_I2COA1__M (0x03ff)
5333 #define EUSCI_B2_I2C_I2COA1_UCOAEN (0x0400)
5334 #define EUSCI_B2_I2C_I2COA1_UCOAEN__0 (0x0000)
5335 #define EUSCI_B2_I2C_I2COA1_UCOAEN__1 (0x0400)
5336 #define EUSCI_B2_I2C_I2COA2 (HWREG16(0x40002818))
5337 #define EUSCI_B2_I2C_I2COA2_I2COA2__M (0x03ff)
5338 #define EUSCI_B2_I2C_I2COA2_UCOAEN (0x0400)
5339 #define EUSCI_B2_I2C_I2COA2_UCOAEN__0 (0x0000)
5340 #define EUSCI_B2_I2C_I2COA2_UCOAEN__1 (0x0400)
5341 #define EUSCI_B2_I2C_I2COA3 (HWREG16(0x4000281A))
5342 #define EUSCI_B2_I2C_I2COA3_I2COA3__M (0x03ff)
5343 #define EUSCI_B2_I2C_I2COA3_UCOAEN (0x0400)
5344 #define EUSCI_B2_I2C_I2COA3_UCOAEN__0 (0x0000)
5345 #define EUSCI_B2_I2C_I2COA3_UCOAEN__1 (0x0400)
5346 #define EUSCI_B2_I2C_I2CSA (HWREG16(0x40002820))
5347 #define EUSCI_B2_I2C_I2CSA_I2CSA__M (0x03ff)
5348 #define EUSCI_B2_I2C_IE (HWREG16(0x4000282A))
5349 #define EUSCI_B2_I2C_IE_UCALIE (0x0010)
5350 #define EUSCI_B2_I2C_IE_UCALIE__0 (0x0000)
5351 #define EUSCI_B2_I2C_IE_UCALIE__1 (0x0010)
5352 #define EUSCI_B2_I2C_IE_UCBCNTIE (0x0040)
5353 #define EUSCI_B2_I2C_IE_UCBCNTIE__0 (0x0000)
5354 #define EUSCI_B2_I2C_IE_UCBCNTIE__1 (0x0040)
5355 #define EUSCI_B2_I2C_IE_UCBIT9IE (0x4000)
5356 #define EUSCI_B2_I2C_IE_UCBIT9IE__0 (0x0000)
5357 #define EUSCI_B2_I2C_IE_UCBIT9IE__1 (0x4000)
5358 #define EUSCI_B2_I2C_IE_UCCLTOIE (0x0080)
5359 #define EUSCI_B2_I2C_IE_UCCLTOIE__0 (0x0000)
5360 #define EUSCI_B2_I2C_IE_UCCLTOIE__1 (0x0080)
5361 #define EUSCI_B2_I2C_IE_UCNACKIE (0x0020)
5362 #define EUSCI_B2_I2C_IE_UCNACKIE__0 (0x0000)
5363 #define EUSCI_B2_I2C_IE_UCNACKIE__1 (0x0020)
5364 #define EUSCI_B2_I2C_IE_UCRXIE0 (0x0001)
5365 #define EUSCI_B2_I2C_IE_UCRXIE0__0 (0x0000)
5366 #define EUSCI_B2_I2C_IE_UCRXIE0__1 (0x0001)
5367 #define EUSCI_B2_I2C_IE_UCRXIE1 (0x0100)
5368 #define EUSCI_B2_I2C_IE_UCRXIE1__0 (0x0000)
5369 #define EUSCI_B2_I2C_IE_UCRXIE1__1 (0x0100)
5370 #define EUSCI_B2_I2C_IE_UCRXIE2 (0x0400)
5371 #define EUSCI_B2_I2C_IE_UCRXIE2__0 (0x0000)
5372 #define EUSCI_B2_I2C_IE_UCRXIE2__1 (0x0400)
5373 #define EUSCI_B2_I2C_IE_UCRXIE3 (0x1000)
5374 #define EUSCI_B2_I2C_IE_UCRXIE3__0 (0x0000)
5375 #define EUSCI_B2_I2C_IE_UCRXIE3__1 (0x1000)
5376 #define EUSCI_B2_I2C_IE_UCSTPIE (0x0008)
5377 #define EUSCI_B2_I2C_IE_UCSTPIE__0 (0x0000)
5378 #define EUSCI_B2_I2C_IE_UCSTPIE__1 (0x0008)
5379 #define EUSCI_B2_I2C_IE_UCSTTIE (0x0004)
5380 #define EUSCI_B2_I2C_IE_UCSTTIE__0 (0x0000)
5381 #define EUSCI_B2_I2C_IE_UCSTTIE__1 (0x0004)
5382 #define EUSCI_B2_I2C_IE_UCTXIE0 (0x0002)
5383 #define EUSCI_B2_I2C_IE_UCTXIE0__0 (0x0000)
5384 #define EUSCI_B2_I2C_IE_UCTXIE0__1 (0x0002)
5385 #define EUSCI_B2_I2C_IE_UCTXIE1 (0x0200)
5386 #define EUSCI_B2_I2C_IE_UCTXIE1__0 (0x0000)
5387 #define EUSCI_B2_I2C_IE_UCTXIE1__1 (0x0200)
5388 #define EUSCI_B2_I2C_IE_UCTXIE2 (0x0800)
5389 #define EUSCI_B2_I2C_IE_UCTXIE2__0 (0x0000)
5390 #define EUSCI_B2_I2C_IE_UCTXIE2__1 (0x0800)
5391 #define EUSCI_B2_I2C_IE_UCTXIE3 (0x2000)
5392 #define EUSCI_B2_I2C_IE_UCTXIE3__0 (0x0000)
5393 #define EUSCI_B2_I2C_IE_UCTXIE3__1 (0x2000)
5394 #define EUSCI_B2_I2C_IFG (HWREG16(0x4000282C))
5395 #define EUSCI_B2_I2C_IFG_UCALIFG (0x0010)
5396 #define EUSCI_B2_I2C_IFG_UCALIFG__0 (0x0000)
5397 #define EUSCI_B2_I2C_IFG_UCALIFG__1 (0x0010)
5398 #define EUSCI_B2_I2C_IFG_UCBCNTIFG (0x0040)
5399 #define EUSCI_B2_I2C_IFG_UCBCNTIFG__0 (0x0000)
5400 #define EUSCI_B2_I2C_IFG_UCBCNTIFG__1 (0x0040)
5401 #define EUSCI_B2_I2C_IFG_UCBIT9IFG (0x4000)
5402 #define EUSCI_B2_I2C_IFG_UCBIT9IFG__0 (0x0000)
5403 #define EUSCI_B2_I2C_IFG_UCBIT9IFG__1 (0x4000)
5404 #define EUSCI_B2_I2C_IFG_UCCLTOIFG (0x0080)
5405 #define EUSCI_B2_I2C_IFG_UCCLTOIFG__0 (0x0000)
5406 #define EUSCI_B2_I2C_IFG_UCCLTOIFG__1 (0x0080)
5407 #define EUSCI_B2_I2C_IFG_UCNACKIFG (0x0020)
5408 #define EUSCI_B2_I2C_IFG_UCNACKIFG__0 (0x0000)
5409 #define EUSCI_B2_I2C_IFG_UCNACKIFG__1 (0x0020)
5410 #define EUSCI_B2_I2C_IFG_UCRXIFG0 (0x0001)
5411 #define EUSCI_B2_I2C_IFG_UCRXIFG0__0 (0x0000)
5412 #define EUSCI_B2_I2C_IFG_UCRXIFG0__1 (0x0001)
5413 #define EUSCI_B2_I2C_IFG_UCRXIFG1 (0x0100)
5414 #define EUSCI_B2_I2C_IFG_UCRXIFG1__0 (0x0000)
5415 #define EUSCI_B2_I2C_IFG_UCRXIFG1__1 (0x0100)
5416 #define EUSCI_B2_I2C_IFG_UCRXIFG2 (0x0400)
5417 #define EUSCI_B2_I2C_IFG_UCRXIFG2__0 (0x0000)
5418 #define EUSCI_B2_I2C_IFG_UCRXIFG2__1 (0x0400)
5419 #define EUSCI_B2_I2C_IFG_UCRXIFG3 (0x1000)
5420 #define EUSCI_B2_I2C_IFG_UCRXIFG3__0 (0x0000)
5421 #define EUSCI_B2_I2C_IFG_UCRXIFG3__1 (0x1000)
5422 #define EUSCI_B2_I2C_IFG_UCSTPIFG (0x0008)
5423 #define EUSCI_B2_I2C_IFG_UCSTPIFG__0 (0x0000)
5424 #define EUSCI_B2_I2C_IFG_UCSTPIFG__1 (0x0008)
5425 #define EUSCI_B2_I2C_IFG_UCSTTIFG (0x0004)
5426 #define EUSCI_B2_I2C_IFG_UCSTTIFG__0 (0x0000)
5427 #define EUSCI_B2_I2C_IFG_UCSTTIFG__1 (0x0004)
5428 #define EUSCI_B2_I2C_IFG_UCTXIFG0 (0x0002)
5429 #define EUSCI_B2_I2C_IFG_UCTXIFG0__0 (0x0000)
5430 #define EUSCI_B2_I2C_IFG_UCTXIFG0__1 (0x0002)
5431 #define EUSCI_B2_I2C_IFG_UCTXIFG1 (0x0200)
5432 #define EUSCI_B2_I2C_IFG_UCTXIFG1__0 (0x0000)
5433 #define EUSCI_B2_I2C_IFG_UCTXIFG1__1 (0x0200)
5434 #define EUSCI_B2_I2C_IFG_UCTXIFG2 (0x0800)
5435 #define EUSCI_B2_I2C_IFG_UCTXIFG2__0 (0x0000)
5436 #define EUSCI_B2_I2C_IFG_UCTXIFG2__1 (0x0800)
5437 #define EUSCI_B2_I2C_IFG_UCTXIFG3 (0x2000)
5438 #define EUSCI_B2_I2C_IFG_UCTXIFG3__0 (0x0000)
5439 #define EUSCI_B2_I2C_IFG_UCTXIFG3__1 (0x2000)
5440 #define EUSCI_B2_I2C_IV (HWREG16(0x4000282E))
5441 #define EUSCI_B2_I2C_RXBUF (HWREG16(0x4000280C))
5442 #define EUSCI_B2_I2C_RXBUF_UCRXBUF__M (0x00ff)
5443 #define EUSCI_B2_I2C_STATW (HWREG16(0x40002808))
5444 #define EUSCI_B2_I2C_STATW_UCBBUSY (0x0010)
5445 #define EUSCI_B2_I2C_STATW_UCBBUSY__0 (0x0000)
5446 #define EUSCI_B2_I2C_STATW_UCBBUSY__0_BUS_INACTIVE (0x0000)
5447 #define EUSCI_B2_I2C_STATW_UCBBUSY__1 (0x0010)
5448 #define EUSCI_B2_I2C_STATW_UCBBUSY__1_BUS_BUSY (0x0010)
5449 #define EUSCI_B2_I2C_STATW_UCBCNT__M (0xff00)
5450 #define EUSCI_B2_I2C_STATW_UCGC (0x0020)
5451 #define EUSCI_B2_I2C_STATW_UCGC__0 (0x0000)
5452 #define EUSCI_B2_I2C_STATW_UCGC__1 (0x0020)
5453 #define EUSCI_B2_I2C_STATW_UCSCLLOW (0x0040)
5454 #define EUSCI_B2_I2C_STATW_UCSCLLOW__0 (0x0000)
5455 #define EUSCI_B2_I2C_STATW_UCSCLLOW__1 (0x0040)
5456 #define EUSCI_B2_I2C_STATW_UCSCLLOW__1_SCL_IS_HELD_LOW (0x0040)
5457 #define EUSCI_B2_I2C_TBCNT (HWREG16(0x4000280A))
5458 #define EUSCI_B2_I2C_TBCNT_UCTBCNT__M (0x00ff)
5459 #define EUSCI_B2_I2C_TXBUF (HWREG16(0x4000280E))
5460 #define EUSCI_B2_I2C_TXBUF_UCTXBUF__M (0x00ff)
5461 #define EUSCI_B2_SPI_BRW (HWREG16(0x40002806))
5462 #define EUSCI_B2_SPI_CTLW0 (HWREG16(0x40002800))
5463 #define EUSCI_B2_SPI_CTLW0_UC7BIT (0x1000)
5464 #define EUSCI_B2_SPI_CTLW0_UC7BIT__0 (0x0000)
5465 #define EUSCI_B2_SPI_CTLW0_UC7BIT__0_8_BIT_DATA (0x0000)
5466 #define EUSCI_B2_SPI_CTLW0_UC7BIT__1 (0x1000)
5467 #define EUSCI_B2_SPI_CTLW0_UC7BIT__1_7_BIT_DATA (0x1000)
5468 #define EUSCI_B2_SPI_CTLW0_UCCKPH (0x8000)
5469 #define EUSCI_B2_SPI_CTLW0_UCCKPH__0 (0x0000)
5470 #define EUSCI_B2_SPI_CTLW0_UCCKPH__1 (0x8000)
5471 #define EUSCI_B2_SPI_CTLW0_UCCKPL (0x4000)
5472 #define EUSCI_B2_SPI_CTLW0_UCCKPL__0 (0x0000)
5473 #define EUSCI_B2_SPI_CTLW0_UCCKPL__1 (0x4000)
5474 #define EUSCI_B2_SPI_CTLW0_UCMODE__0 (0x0000)
5475 #define EUSCI_B2_SPI_CTLW0_UCMODE__0_3_PIN_SPI (0x0000)
5476 #define EUSCI_B2_SPI_CTLW0_UCMODE__1 (0x0200)
5477 #define EUSCI_B2_SPI_CTLW0_UCMODE__2 (0x0400)
5478 #define EUSCI_B2_SPI_CTLW0_UCMODE__3 (0x0600)
5479 #define EUSCI_B2_SPI_CTLW0_UCMODE__3_I2C_MODE (0x0600)
5480 #define EUSCI_B2_SPI_CTLW0_UCMODE__M (0x0600)
5481 #define EUSCI_B2_SPI_CTLW0_UCMSB (0x2000)
5482 #define EUSCI_B2_SPI_CTLW0_UCMSB__0 (0x0000)
5483 #define EUSCI_B2_SPI_CTLW0_UCMSB__0_LSB_FIRST (0x0000)
5484 #define EUSCI_B2_SPI_CTLW0_UCMSB__1 (0x2000)
5485 #define EUSCI_B2_SPI_CTLW0_UCMSB__1_MSB_FIRST (0x2000)
5486 #define EUSCI_B2_SPI_CTLW0_UCMST (0x0800)
5487 #define EUSCI_B2_SPI_CTLW0_UCMST__0 (0x0000)
5488 #define EUSCI_B2_SPI_CTLW0_UCMST__0_SLAVE_MODE (0x0000)
5489 #define EUSCI_B2_SPI_CTLW0_UCMST__1 (0x0800)
5490 #define EUSCI_B2_SPI_CTLW0_UCMST__1_MASTER_MODE (0x0800)
5491 #define EUSCI_B2_SPI_CTLW0_UCSSEL__1 (0x0040)
5492 #define EUSCI_B2_SPI_CTLW0_UCSSEL__1_ACLK (0x0040)
5493 #define EUSCI_B2_SPI_CTLW0_UCSSEL__2 (0x0080)
5494 #define EUSCI_B2_SPI_CTLW0_UCSSEL__2_SMCLK (0x0080)
5495 #define EUSCI_B2_SPI_CTLW0_UCSSEL__3 (0x00c0)
5496 #define EUSCI_B2_SPI_CTLW0_UCSSEL__3_SMCLK (0x00c0)
5497 #define EUSCI_B2_SPI_CTLW0_UCSSEL__M (0x00c0)
5498 #define EUSCI_B2_SPI_CTLW0_UCSTEM (0x0002)
5499 #define EUSCI_B2_SPI_CTLW0_UCSTEM__0 (0x0000)
5500 #define EUSCI_B2_SPI_CTLW0_UCSTEM__1 (0x0002)
5501 #define EUSCI_B2_SPI_CTLW0_UCSWRST (0x0001)
5502 #define EUSCI_B2_SPI_CTLW0_UCSWRST__0 (0x0000)
5503 #define EUSCI_B2_SPI_CTLW0_UCSWRST__1 (0x0001)
5504 #define EUSCI_B2_SPI_CTLW0_UCSYNC (0x0100)
5505 #define EUSCI_B2_SPI_CTLW0_UCSYNC__0 (0x0000)
5506 #define EUSCI_B2_SPI_CTLW0_UCSYNC__1 (0x0100)
5507 #define EUSCI_B2_SPI_IE (HWREG16(0x4000282A))
5508 #define EUSCI_B2_SPI_IE_UCRXIE (0x0001)
5509 #define EUSCI_B2_SPI_IE_UCRXIE__0 (0x0000)
5510 #define EUSCI_B2_SPI_IE_UCRXIE__1 (0x0001)
5511 #define EUSCI_B2_SPI_IE_UCTXIE (0x0002)
5512 #define EUSCI_B2_SPI_IE_UCTXIE__0 (0x0000)
5513 #define EUSCI_B2_SPI_IE_UCTXIE__1 (0x0002)
5514 #define EUSCI_B2_SPI_IFG (HWREG16(0x4000282C))
5515 #define EUSCI_B2_SPI_IFG_UCRXIFG (0x0001)
5516 #define EUSCI_B2_SPI_IFG_UCRXIFG__0 (0x0000)
5517 #define EUSCI_B2_SPI_IFG_UCRXIFG__1 (0x0001)
5518 #define EUSCI_B2_SPI_IFG_UCTXIFG (0x0002)
5519 #define EUSCI_B2_SPI_IFG_UCTXIFG__0 (0x0000)
5520 #define EUSCI_B2_SPI_IFG_UCTXIFG__1 (0x0002)
5521 #define EUSCI_B2_SPI_IV (HWREG16(0x4000282E))
5522 #define EUSCI_B2_SPI_RXBUF (HWREG16(0x4000280C))
5523 #define EUSCI_B2_SPI_RXBUF_UCRXBUF__M (0x00ff)
5524 #define EUSCI_B2_SPI_STATW (HWREG16(0x40002808))
5525 #define EUSCI_B2_SPI_STATW_UCBUSY (0x0001)
5526 #define EUSCI_B2_SPI_STATW_UCBUSY__0 (0x0000)
5527 #define EUSCI_B2_SPI_STATW_UCBUSY__0_EUSCI_INACTIVE (0x0000)
5528 #define EUSCI_B2_SPI_STATW_UCBUSY__1 (0x0001)
5529 #define EUSCI_B2_SPI_STATW_UCFE (0x0040)
5530 #define EUSCI_B2_SPI_STATW_UCFE__0 (0x0000)
5531 #define EUSCI_B2_SPI_STATW_UCFE__0_NO_ERROR (0x0000)
5532 #define EUSCI_B2_SPI_STATW_UCFE__1 (0x0040)
5533 #define EUSCI_B2_SPI_STATW_UCLISTEN (0x0080)
5534 #define EUSCI_B2_SPI_STATW_UCLISTEN__0 (0x0000)
5535 #define EUSCI_B2_SPI_STATW_UCLISTEN__0_DISABLED (0x0000)
5536 #define EUSCI_B2_SPI_STATW_UCLISTEN__1 (0x0080)
5537 #define EUSCI_B2_SPI_STATW_UCOE (0x0020)
5538 #define EUSCI_B2_SPI_STATW_UCOE__0 (0x0000)
5539 #define EUSCI_B2_SPI_STATW_UCOE__0_NO_ERROR (0x0000)
5540 #define EUSCI_B2_SPI_STATW_UCOE__1 (0x0020)
5541 #define EUSCI_B2_SPI_TXBUF (HWREG16(0x4000280E))
5542 #define EUSCI_B2_SPI_TXBUF_UCTXBUF__M (0x00ff)
5543 #define EUSCI_B3_I2C_ADDMASK (HWREG16(0x40002C1E))
5544 #define EUSCI_B3_I2C_ADDMASK_ADDMASK__M (0x03ff)
5545 #define EUSCI_B3_I2C_ADDRX (HWREG16(0x40002C1C))
5546 #define EUSCI_B3_I2C_ADDRX_ADDRX__M (0x03ff)
5547 #define EUSCI_B3_I2C_BRW (HWREG16(0x40002C06))
5548 #define EUSCI_B3_I2C_CTLW0 (HWREG16(0x40002C00))
5549 #define EUSCI_B3_I2C_CTLW0_UCA10 (0x8000)
5550 #define EUSCI_B3_I2C_CTLW0_UCA10__0 (0x0000)
5551 #define EUSCI_B3_I2C_CTLW0_UCA10__1 (0x8000)
5552 #define EUSCI_B3_I2C_CTLW0_UCMM (0x2000)
5553 #define EUSCI_B3_I2C_CTLW0_UCMM__0 (0x0000)
5554 #define EUSCI_B3_I2C_CTLW0_UCMM__1 (0x2000)
5555 #define EUSCI_B3_I2C_CTLW0_UCMODE__0 (0x0000)
5556 #define EUSCI_B3_I2C_CTLW0_UCMODE__0_3_PIN_SPI (0x0000)
5557 #define EUSCI_B3_I2C_CTLW0_UCMODE__1 (0x0200)
5558 #define EUSCI_B3_I2C_CTLW0_UCMODE__2 (0x0400)
5559 #define EUSCI_B3_I2C_CTLW0_UCMODE__3 (0x0600)
5560 #define EUSCI_B3_I2C_CTLW0_UCMODE__3_I2C_MODE (0x0600)
5561 #define EUSCI_B3_I2C_CTLW0_UCMODE__M (0x0600)
5562 #define EUSCI_B3_I2C_CTLW0_UCMST (0x0800)
5563 #define EUSCI_B3_I2C_CTLW0_UCMST__0 (0x0000)
5564 #define EUSCI_B3_I2C_CTLW0_UCMST__0_SLAVE_MODE (0x0000)
5565 #define EUSCI_B3_I2C_CTLW0_UCMST__1 (0x0800)
5566 #define EUSCI_B3_I2C_CTLW0_UCMST__1_MASTER_MODE (0x0800)
5567 #define EUSCI_B3_I2C_CTLW0_UCSLA10 (0x4000)
5568 #define EUSCI_B3_I2C_CTLW0_UCSLA10__0 (0x0000)
5569 #define EUSCI_B3_I2C_CTLW0_UCSLA10__1 (0x4000)
5570 #define EUSCI_B3_I2C_CTLW0_UCSSEL__0 (0x0000)
5571 #define EUSCI_B3_I2C_CTLW0_UCSSEL__0_UCLKI (0x0000)
5572 #define EUSCI_B3_I2C_CTLW0_UCSSEL__1 (0x0040)
5573 #define EUSCI_B3_I2C_CTLW0_UCSSEL__1_ACLK (0x0040)
5574 #define EUSCI_B3_I2C_CTLW0_UCSSEL__2 (0x0080)
5575 #define EUSCI_B3_I2C_CTLW0_UCSSEL__2_SMCLK (0x0080)
5576 #define EUSCI_B3_I2C_CTLW0_UCSSEL__3 (0x00c0)
5577 #define EUSCI_B3_I2C_CTLW0_UCSSEL__3_SMCLK (0x00c0)
5578 #define EUSCI_B3_I2C_CTLW0_UCSSEL__M (0x00c0)
5579 #define EUSCI_B3_I2C_CTLW0_UCSWRST (0x0001)
5580 #define EUSCI_B3_I2C_CTLW0_UCSWRST__0 (0x0000)
5581 #define EUSCI_B3_I2C_CTLW0_UCSWRST__1 (0x0001)
5582 #define EUSCI_B3_I2C_CTLW0_UCSYNC (0x0100)
5583 #define EUSCI_B3_I2C_CTLW0_UCTR (0x0010)
5584 #define EUSCI_B3_I2C_CTLW0_UCTR__0 (0x0000)
5585 #define EUSCI_B3_I2C_CTLW0_UCTR__0_RECEIVER (0x0000)
5586 #define EUSCI_B3_I2C_CTLW0_UCTR__1 (0x0010)
5587 #define EUSCI_B3_I2C_CTLW0_UCTR__1_TRANSMITTER (0x0010)
5588 #define EUSCI_B3_I2C_CTLW0_UCTXACK (0x0020)
5589 #define EUSCI_B3_I2C_CTLW0_UCTXACK__0 (0x0000)
5590 #define EUSCI_B3_I2C_CTLW0_UCTXACK__1 (0x0020)
5591 #define EUSCI_B3_I2C_CTLW0_UCTXNACK (0x0008)
5592 #define EUSCI_B3_I2C_CTLW0_UCTXNACK__0 (0x0000)
5593 #define EUSCI_B3_I2C_CTLW0_UCTXNACK__1 (0x0008)
5594 #define EUSCI_B3_I2C_CTLW0_UCTXNACK__1_GENERATE_NACK (0x0008)
5595 #define EUSCI_B3_I2C_CTLW0_UCTXSTP (0x0004)
5596 #define EUSCI_B3_I2C_CTLW0_UCTXSTP__0 (0x0000)
5597 #define EUSCI_B3_I2C_CTLW0_UCTXSTP__1 (0x0004)
5598 #define EUSCI_B3_I2C_CTLW0_UCTXSTP__1_GENERATE_STOP (0x0004)
5599 #define EUSCI_B3_I2C_CTLW0_UCTXSTT (0x0002)
5600 #define EUSCI_B3_I2C_CTLW0_UCTXSTT__0 (0x0000)
5601 #define EUSCI_B3_I2C_CTLW0_UCTXSTT__1 (0x0002)
5602 #define EUSCI_B3_I2C_CTLW1 (HWREG16(0x40002C02))
5603 #define EUSCI_B3_I2C_CTLW1_UCASTP__0 (0x0000)
5604 #define EUSCI_B3_I2C_CTLW1_UCASTP__1 (0x0004)
5605 #define EUSCI_B3_I2C_CTLW1_UCASTP__2 (0x0008)
5606 #define EUSCI_B3_I2C_CTLW1_UCASTP__M (0x000c)
5607 #define EUSCI_B3_I2C_CTLW1_UCCLTO__0 (0x0000)
5608 #define EUSCI_B3_I2C_CTLW1_UCCLTO__1 (0x0040)
5609 #define EUSCI_B3_I2C_CTLW1_UCCLTO__2 (0x0080)
5610 #define EUSCI_B3_I2C_CTLW1_UCCLTO__3 (0x00c0)
5611 #define EUSCI_B3_I2C_CTLW1_UCCLTO__M (0x00c0)
5612 #define EUSCI_B3_I2C_CTLW1_UCETXINT (0x0100)
5613 #define EUSCI_B3_I2C_CTLW1_UCETXINT__0 (0x0000)
5614 #define EUSCI_B3_I2C_CTLW1_UCETXINT__1 (0x0100)
5615 #define EUSCI_B3_I2C_CTLW1_UCGLIT__0 (0x0000)
5616 #define EUSCI_B3_I2C_CTLW1_UCGLIT__0_50_NS (0x0000)
5617 #define EUSCI_B3_I2C_CTLW1_UCGLIT__1 (0x0001)
5618 #define EUSCI_B3_I2C_CTLW1_UCGLIT__1_25_NS (0x0001)
5619 #define EUSCI_B3_I2C_CTLW1_UCGLIT__2 (0x0002)
5620 #define EUSCI_B3_I2C_CTLW1_UCGLIT__2_12_5_NS (0x0002)
5621 #define EUSCI_B3_I2C_CTLW1_UCGLIT__3 (0x0003)
5622 #define EUSCI_B3_I2C_CTLW1_UCGLIT__3_6_25_NS (0x0003)
5623 #define EUSCI_B3_I2C_CTLW1_UCGLIT__M (0x0003)
5624 #define EUSCI_B3_I2C_CTLW1_UCSTPNACK (0x0020)
5625 #define EUSCI_B3_I2C_CTLW1_UCSTPNACK__0 (0x0000)
5626 #define EUSCI_B3_I2C_CTLW1_UCSTPNACK__1 (0x0020)
5627 #define EUSCI_B3_I2C_CTLW1_UCSWACK (0x0010)
5628 #define EUSCI_B3_I2C_CTLW1_UCSWACK__0 (0x0000)
5629 #define EUSCI_B3_I2C_CTLW1_UCSWACK__1 (0x0010)
5630 #define EUSCI_B3_I2C_I2COA0 (HWREG16(0x40002C14))
5631 #define EUSCI_B3_I2C_I2COA0_I2COA__M (0x03ff)
5632 #define EUSCI_B3_I2C_I2COA0_UCGCEN (0x8000)
5633 #define EUSCI_B3_I2C_I2COA0_UCGCEN__0 (0x0000)
5634 #define EUSCI_B3_I2C_I2COA0_UCGCEN__1 (0x8000)
5635 #define EUSCI_B3_I2C_I2COA0_UCOAEN (0x0400)
5636 #define EUSCI_B3_I2C_I2COA0_UCOAEN__0 (0x0000)
5637 #define EUSCI_B3_I2C_I2COA0_UCOAEN__1 (0x0400)
5638 #define EUSCI_B3_I2C_I2COA1 (HWREG16(0x40002C16))
5639 #define EUSCI_B3_I2C_I2COA1_I2COA1__M (0x03ff)
5640 #define EUSCI_B3_I2C_I2COA1_UCOAEN (0x0400)
5641 #define EUSCI_B3_I2C_I2COA1_UCOAEN__0 (0x0000)
5642 #define EUSCI_B3_I2C_I2COA1_UCOAEN__1 (0x0400)
5643 #define EUSCI_B3_I2C_I2COA2 (HWREG16(0x40002C18))
5644 #define EUSCI_B3_I2C_I2COA2_I2COA2__M (0x03ff)
5645 #define EUSCI_B3_I2C_I2COA2_UCOAEN (0x0400)
5646 #define EUSCI_B3_I2C_I2COA2_UCOAEN__0 (0x0000)
5647 #define EUSCI_B3_I2C_I2COA2_UCOAEN__1 (0x0400)
5648 #define EUSCI_B3_I2C_I2COA3 (HWREG16(0x40002C1A))
5649 #define EUSCI_B3_I2C_I2COA3_I2COA3__M (0x03ff)
5650 #define EUSCI_B3_I2C_I2COA3_UCOAEN (0x0400)
5651 #define EUSCI_B3_I2C_I2COA3_UCOAEN__0 (0x0000)
5652 #define EUSCI_B3_I2C_I2COA3_UCOAEN__1 (0x0400)
5653 #define EUSCI_B3_I2C_I2CSA (HWREG16(0x40002C20))
5654 #define EUSCI_B3_I2C_I2CSA_I2CSA__M (0x03ff)
5655 #define EUSCI_B3_I2C_IE (HWREG16(0x40002C2A))
5656 #define EUSCI_B3_I2C_IE_UCALIE (0x0010)
5657 #define EUSCI_B3_I2C_IE_UCALIE__0 (0x0000)
5658 #define EUSCI_B3_I2C_IE_UCALIE__1 (0x0010)
5659 #define EUSCI_B3_I2C_IE_UCBCNTIE (0x0040)
5660 #define EUSCI_B3_I2C_IE_UCBCNTIE__0 (0x0000)
5661 #define EUSCI_B3_I2C_IE_UCBCNTIE__1 (0x0040)
5662 #define EUSCI_B3_I2C_IE_UCBIT9IE (0x4000)
5663 #define EUSCI_B3_I2C_IE_UCBIT9IE__0 (0x0000)
5664 #define EUSCI_B3_I2C_IE_UCBIT9IE__1 (0x4000)
5665 #define EUSCI_B3_I2C_IE_UCCLTOIE (0x0080)
5666 #define EUSCI_B3_I2C_IE_UCCLTOIE__0 (0x0000)
5667 #define EUSCI_B3_I2C_IE_UCCLTOIE__1 (0x0080)
5668 #define EUSCI_B3_I2C_IE_UCNACKIE (0x0020)
5669 #define EUSCI_B3_I2C_IE_UCNACKIE__0 (0x0000)
5670 #define EUSCI_B3_I2C_IE_UCNACKIE__1 (0x0020)
5671 #define EUSCI_B3_I2C_IE_UCRXIE0 (0x0001)
5672 #define EUSCI_B3_I2C_IE_UCRXIE0__0 (0x0000)
5673 #define EUSCI_B3_I2C_IE_UCRXIE0__1 (0x0001)
5674 #define EUSCI_B3_I2C_IE_UCRXIE1 (0x0100)
5675 #define EUSCI_B3_I2C_IE_UCRXIE1__0 (0x0000)
5676 #define EUSCI_B3_I2C_IE_UCRXIE1__1 (0x0100)
5677 #define EUSCI_B3_I2C_IE_UCRXIE2 (0x0400)
5678 #define EUSCI_B3_I2C_IE_UCRXIE2__0 (0x0000)
5679 #define EUSCI_B3_I2C_IE_UCRXIE2__1 (0x0400)
5680 #define EUSCI_B3_I2C_IE_UCRXIE3 (0x1000)
5681 #define EUSCI_B3_I2C_IE_UCRXIE3__0 (0x0000)
5682 #define EUSCI_B3_I2C_IE_UCRXIE3__1 (0x1000)
5683 #define EUSCI_B3_I2C_IE_UCSTPIE (0x0008)
5684 #define EUSCI_B3_I2C_IE_UCSTPIE__0 (0x0000)
5685 #define EUSCI_B3_I2C_IE_UCSTPIE__1 (0x0008)
5686 #define EUSCI_B3_I2C_IE_UCSTTIE (0x0004)
5687 #define EUSCI_B3_I2C_IE_UCSTTIE__0 (0x0000)
5688 #define EUSCI_B3_I2C_IE_UCSTTIE__1 (0x0004)
5689 #define EUSCI_B3_I2C_IE_UCTXIE0 (0x0002)
5690 #define EUSCI_B3_I2C_IE_UCTXIE0__0 (0x0000)
5691 #define EUSCI_B3_I2C_IE_UCTXIE0__1 (0x0002)
5692 #define EUSCI_B3_I2C_IE_UCTXIE1 (0x0200)
5693 #define EUSCI_B3_I2C_IE_UCTXIE1__0 (0x0000)
5694 #define EUSCI_B3_I2C_IE_UCTXIE1__1 (0x0200)
5695 #define EUSCI_B3_I2C_IE_UCTXIE2 (0x0800)
5696 #define EUSCI_B3_I2C_IE_UCTXIE2__0 (0x0000)
5697 #define EUSCI_B3_I2C_IE_UCTXIE2__1 (0x0800)
5698 #define EUSCI_B3_I2C_IE_UCTXIE3 (0x2000)
5699 #define EUSCI_B3_I2C_IE_UCTXIE3__0 (0x0000)
5700 #define EUSCI_B3_I2C_IE_UCTXIE3__1 (0x2000)
5701 #define EUSCI_B3_I2C_IFG (HWREG16(0x40002C2C))
5702 #define EUSCI_B3_I2C_IFG_UCALIFG (0x0010)
5703 #define EUSCI_B3_I2C_IFG_UCALIFG__0 (0x0000)
5704 #define EUSCI_B3_I2C_IFG_UCALIFG__1 (0x0010)
5705 #define EUSCI_B3_I2C_IFG_UCBCNTIFG (0x0040)
5706 #define EUSCI_B3_I2C_IFG_UCBCNTIFG__0 (0x0000)
5707 #define EUSCI_B3_I2C_IFG_UCBCNTIFG__1 (0x0040)
5708 #define EUSCI_B3_I2C_IFG_UCBIT9IFG (0x4000)
5709 #define EUSCI_B3_I2C_IFG_UCBIT9IFG__0 (0x0000)
5710 #define EUSCI_B3_I2C_IFG_UCBIT9IFG__1 (0x4000)
5711 #define EUSCI_B3_I2C_IFG_UCCLTOIFG (0x0080)
5712 #define EUSCI_B3_I2C_IFG_UCCLTOIFG__0 (0x0000)
5713 #define EUSCI_B3_I2C_IFG_UCCLTOIFG__1 (0x0080)
5714 #define EUSCI_B3_I2C_IFG_UCNACKIFG (0x0020)
5715 #define EUSCI_B3_I2C_IFG_UCNACKIFG__0 (0x0000)
5716 #define EUSCI_B3_I2C_IFG_UCNACKIFG__1 (0x0020)
5717 #define EUSCI_B3_I2C_IFG_UCRXIFG0 (0x0001)
5718 #define EUSCI_B3_I2C_IFG_UCRXIFG0__0 (0x0000)
5719 #define EUSCI_B3_I2C_IFG_UCRXIFG0__1 (0x0001)
5720 #define EUSCI_B3_I2C_IFG_UCRXIFG1 (0x0100)
5721 #define EUSCI_B3_I2C_IFG_UCRXIFG1__0 (0x0000)
5722 #define EUSCI_B3_I2C_IFG_UCRXIFG1__1 (0x0100)
5723 #define EUSCI_B3_I2C_IFG_UCRXIFG2 (0x0400)
5724 #define EUSCI_B3_I2C_IFG_UCRXIFG2__0 (0x0000)
5725 #define EUSCI_B3_I2C_IFG_UCRXIFG2__1 (0x0400)
5726 #define EUSCI_B3_I2C_IFG_UCRXIFG3 (0x1000)
5727 #define EUSCI_B3_I2C_IFG_UCRXIFG3__0 (0x0000)
5728 #define EUSCI_B3_I2C_IFG_UCRXIFG3__1 (0x1000)
5729 #define EUSCI_B3_I2C_IFG_UCSTPIFG (0x0008)
5730 #define EUSCI_B3_I2C_IFG_UCSTPIFG__0 (0x0000)
5731 #define EUSCI_B3_I2C_IFG_UCSTPIFG__1 (0x0008)
5732 #define EUSCI_B3_I2C_IFG_UCSTTIFG (0x0004)
5733 #define EUSCI_B3_I2C_IFG_UCSTTIFG__0 (0x0000)
5734 #define EUSCI_B3_I2C_IFG_UCSTTIFG__1 (0x0004)
5735 #define EUSCI_B3_I2C_IFG_UCTXIFG0 (0x0002)
5736 #define EUSCI_B3_I2C_IFG_UCTXIFG0__0 (0x0000)
5737 #define EUSCI_B3_I2C_IFG_UCTXIFG0__1 (0x0002)
5738 #define EUSCI_B3_I2C_IFG_UCTXIFG1 (0x0200)
5739 #define EUSCI_B3_I2C_IFG_UCTXIFG1__0 (0x0000)
5740 #define EUSCI_B3_I2C_IFG_UCTXIFG1__1 (0x0200)
5741 #define EUSCI_B3_I2C_IFG_UCTXIFG2 (0x0800)
5742 #define EUSCI_B3_I2C_IFG_UCTXIFG2__0 (0x0000)
5743 #define EUSCI_B3_I2C_IFG_UCTXIFG2__1 (0x0800)
5744 #define EUSCI_B3_I2C_IFG_UCTXIFG3 (0x2000)
5745 #define EUSCI_B3_I2C_IFG_UCTXIFG3__0 (0x0000)
5746 #define EUSCI_B3_I2C_IFG_UCTXIFG3__1 (0x2000)
5747 #define EUSCI_B3_I2C_IV (HWREG16(0x40002C2E))
5748 #define EUSCI_B3_I2C_RXBUF (HWREG16(0x40002C0C))
5749 #define EUSCI_B3_I2C_RXBUF_UCRXBUF__M (0x00ff)
5750 #define EUSCI_B3_I2C_STATW (HWREG16(0x40002C08))
5751 #define EUSCI_B3_I2C_STATW_UCBBUSY (0x0010)
5752 #define EUSCI_B3_I2C_STATW_UCBBUSY__0 (0x0000)
5753 #define EUSCI_B3_I2C_STATW_UCBBUSY__0_BUS_INACTIVE (0x0000)
5754 #define EUSCI_B3_I2C_STATW_UCBBUSY__1 (0x0010)
5755 #define EUSCI_B3_I2C_STATW_UCBBUSY__1_BUS_BUSY (0x0010)
5756 #define EUSCI_B3_I2C_STATW_UCBCNT__M (0xff00)
5757 #define EUSCI_B3_I2C_STATW_UCGC (0x0020)
5758 #define EUSCI_B3_I2C_STATW_UCGC__0 (0x0000)
5759 #define EUSCI_B3_I2C_STATW_UCGC__1 (0x0020)
5760 #define EUSCI_B3_I2C_STATW_UCSCLLOW (0x0040)
5761 #define EUSCI_B3_I2C_STATW_UCSCLLOW__0 (0x0000)
5762 #define EUSCI_B3_I2C_STATW_UCSCLLOW__1 (0x0040)
5763 #define EUSCI_B3_I2C_STATW_UCSCLLOW__1_SCL_IS_HELD_LOW (0x0040)
5764 #define EUSCI_B3_I2C_TBCNT (HWREG16(0x40002C0A))
5765 #define EUSCI_B3_I2C_TBCNT_UCTBCNT__M (0x00ff)
5766 #define EUSCI_B3_I2C_TXBUF (HWREG16(0x40002C0E))
5767 #define EUSCI_B3_I2C_TXBUF_UCTXBUF__M (0x00ff)
5768 #define EUSCI_B3_SPI_BRW (HWREG16(0x40002C06))
5769 #define EUSCI_B3_SPI_CTLW0 (HWREG16(0x40002C00))
5770 #define EUSCI_B3_SPI_CTLW0_UC7BIT (0x1000)
5771 #define EUSCI_B3_SPI_CTLW0_UC7BIT__0 (0x0000)
5772 #define EUSCI_B3_SPI_CTLW0_UC7BIT__0_8_BIT_DATA (0x0000)
5773 #define EUSCI_B3_SPI_CTLW0_UC7BIT__1 (0x1000)
5774 #define EUSCI_B3_SPI_CTLW0_UC7BIT__1_7_BIT_DATA (0x1000)
5775 #define EUSCI_B3_SPI_CTLW0_UCCKPH (0x8000)
5776 #define EUSCI_B3_SPI_CTLW0_UCCKPH__0 (0x0000)
5777 #define EUSCI_B3_SPI_CTLW0_UCCKPH__1 (0x8000)
5778 #define EUSCI_B3_SPI_CTLW0_UCCKPL (0x4000)
5779 #define EUSCI_B3_SPI_CTLW0_UCCKPL__0 (0x0000)
5780 #define EUSCI_B3_SPI_CTLW0_UCCKPL__1 (0x4000)
5781 #define EUSCI_B3_SPI_CTLW0_UCMODE__0 (0x0000)
5782 #define EUSCI_B3_SPI_CTLW0_UCMODE__0_3_PIN_SPI (0x0000)
5783 #define EUSCI_B3_SPI_CTLW0_UCMODE__1 (0x0200)
5784 #define EUSCI_B3_SPI_CTLW0_UCMODE__2 (0x0400)
5785 #define EUSCI_B3_SPI_CTLW0_UCMODE__3 (0x0600)
5786 #define EUSCI_B3_SPI_CTLW0_UCMODE__3_I2C_MODE (0x0600)
5787 #define EUSCI_B3_SPI_CTLW0_UCMODE__M (0x0600)
5788 #define EUSCI_B3_SPI_CTLW0_UCMSB (0x2000)
5789 #define EUSCI_B3_SPI_CTLW0_UCMSB__0 (0x0000)
5790 #define EUSCI_B3_SPI_CTLW0_UCMSB__0_LSB_FIRST (0x0000)
5791 #define EUSCI_B3_SPI_CTLW0_UCMSB__1 (0x2000)
5792 #define EUSCI_B3_SPI_CTLW0_UCMSB__1_MSB_FIRST (0x2000)
5793 #define EUSCI_B3_SPI_CTLW0_UCMST (0x0800)
5794 #define EUSCI_B3_SPI_CTLW0_UCMST__0 (0x0000)
5795 #define EUSCI_B3_SPI_CTLW0_UCMST__0_SLAVE_MODE (0x0000)
5796 #define EUSCI_B3_SPI_CTLW0_UCMST__1 (0x0800)
5797 #define EUSCI_B3_SPI_CTLW0_UCMST__1_MASTER_MODE (0x0800)
5798 #define EUSCI_B3_SPI_CTLW0_UCSSEL__1 (0x0040)
5799 #define EUSCI_B3_SPI_CTLW0_UCSSEL__1_ACLK (0x0040)
5800 #define EUSCI_B3_SPI_CTLW0_UCSSEL__2 (0x0080)
5801 #define EUSCI_B3_SPI_CTLW0_UCSSEL__2_SMCLK (0x0080)
5802 #define EUSCI_B3_SPI_CTLW0_UCSSEL__3 (0x00c0)
5803 #define EUSCI_B3_SPI_CTLW0_UCSSEL__3_SMCLK (0x00c0)
5804 #define EUSCI_B3_SPI_CTLW0_UCSSEL__M (0x00c0)
5805 #define EUSCI_B3_SPI_CTLW0_UCSTEM (0x0002)
5806 #define EUSCI_B3_SPI_CTLW0_UCSTEM__0 (0x0000)
5807 #define EUSCI_B3_SPI_CTLW0_UCSTEM__1 (0x0002)
5808 #define EUSCI_B3_SPI_CTLW0_UCSWRST (0x0001)
5809 #define EUSCI_B3_SPI_CTLW0_UCSWRST__0 (0x0000)
5810 #define EUSCI_B3_SPI_CTLW0_UCSWRST__1 (0x0001)
5811 #define EUSCI_B3_SPI_CTLW0_UCSYNC (0x0100)
5812 #define EUSCI_B3_SPI_CTLW0_UCSYNC__0 (0x0000)
5813 #define EUSCI_B3_SPI_CTLW0_UCSYNC__1 (0x0100)
5814 #define EUSCI_B3_SPI_IE (HWREG16(0x40002C2A))
5815 #define EUSCI_B3_SPI_IE_UCRXIE (0x0001)
5816 #define EUSCI_B3_SPI_IE_UCRXIE__0 (0x0000)
5817 #define EUSCI_B3_SPI_IE_UCRXIE__1 (0x0001)
5818 #define EUSCI_B3_SPI_IE_UCTXIE (0x0002)
5819 #define EUSCI_B3_SPI_IE_UCTXIE__0 (0x0000)
5820 #define EUSCI_B3_SPI_IE_UCTXIE__1 (0x0002)
5821 #define EUSCI_B3_SPI_IFG (HWREG16(0x40002C2C))
5822 #define EUSCI_B3_SPI_IFG_UCRXIFG (0x0001)
5823 #define EUSCI_B3_SPI_IFG_UCRXIFG__0 (0x0000)
5824 #define EUSCI_B3_SPI_IFG_UCRXIFG__1 (0x0001)
5825 #define EUSCI_B3_SPI_IFG_UCTXIFG (0x0002)
5826 #define EUSCI_B3_SPI_IFG_UCTXIFG__0 (0x0000)
5827 #define EUSCI_B3_SPI_IFG_UCTXIFG__1 (0x0002)
5828 #define EUSCI_B3_SPI_IV (HWREG16(0x40002C2E))
5829 #define EUSCI_B3_SPI_RXBUF (HWREG16(0x40002C0C))
5830 #define EUSCI_B3_SPI_RXBUF_UCRXBUF__M (0x00ff)
5831 #define EUSCI_B3_SPI_STATW (HWREG16(0x40002C08))
5832 #define EUSCI_B3_SPI_STATW_UCBUSY (0x0001)
5833 #define EUSCI_B3_SPI_STATW_UCBUSY__0 (0x0000)
5834 #define EUSCI_B3_SPI_STATW_UCBUSY__0_EUSCI_INACTIVE (0x0000)
5835 #define EUSCI_B3_SPI_STATW_UCBUSY__1 (0x0001)
5836 #define EUSCI_B3_SPI_STATW_UCFE (0x0040)
5837 #define EUSCI_B3_SPI_STATW_UCFE__0 (0x0000)
5838 #define EUSCI_B3_SPI_STATW_UCFE__0_NO_ERROR (0x0000)
5839 #define EUSCI_B3_SPI_STATW_UCFE__1 (0x0040)
5840 #define EUSCI_B3_SPI_STATW_UCLISTEN (0x0080)
5841 #define EUSCI_B3_SPI_STATW_UCLISTEN__0 (0x0000)
5842 #define EUSCI_B3_SPI_STATW_UCLISTEN__0_DISABLED (0x0000)
5843 #define EUSCI_B3_SPI_STATW_UCLISTEN__1 (0x0080)
5844 #define EUSCI_B3_SPI_STATW_UCOE (0x0020)
5845 #define EUSCI_B3_SPI_STATW_UCOE__0 (0x0000)
5846 #define EUSCI_B3_SPI_STATW_UCOE__0_NO_ERROR (0x0000)
5847 #define EUSCI_B3_SPI_STATW_UCOE__1 (0x0020)
5848 #define EUSCI_B3_SPI_TXBUF (HWREG16(0x40002C0E))
5849 #define EUSCI_B3_SPI_TXBUF_UCTXBUF__M (0x00ff)
5850 #define FCNTHF2__0 (0x00000000)
5851 #define FCNTHF2__1 (0x00000100)
5852 #define FCNTHF2__2 (0x00000200)
5853 #define FCNTHF2__3 (0x00000300)
5854 #define FCNTHF__0 (0x00000000)
5855 #define FCNTHF__1 (0x00000010)
5856 #define FCNTHF__2 (0x00000020)
5857 #define FCNTHF__3 (0x00000030)
5858 #define FCNTLF__0 (0x00000000)
5859 #define FCNTLF__1 (0x00000001)
5860 #define FCNTLF__2 (0x00000002)
5861 #define FCNTLF__3 (0x00000003)
5862 #define FLCTL_BMRK_CTLSTAT_CMP_SEL__0 (0x00000000)
5863 #define FLCTL_BMRK_CTLSTAT_CMP_SEL__1 (0x00000008)
5864 #define FLCTL_ERASE_CTLSTAT_MODE__0 (0x00000000)
5865 #define FLCTL_ERASE_CTLSTAT_MODE__1 (0x00000002)
5866 #define FLCTL_ERASE_CTLSTAT_STATUS__0 (0x00000000)
5867 #define FLCTL_ERASE_CTLSTAT_STATUS__1 (0x00010000)
5868 #define FLCTL_ERASE_CTLSTAT_STATUS__2 (0x00020000)
5869 #define FLCTL_ERASE_CTLSTAT_STATUS__3 (0x00030000)
5870 #define FLCTL_ERASE_CTLSTAT_STATUS__M (0x00030000)
5871 #define FLCTL_ERASE_CTLSTAT_TYPE__0 (0x00000000)
5872 #define FLCTL_ERASE_CTLSTAT_TYPE__0_USER (0x00000000)
5873 #define FLCTL_ERASE_CTLSTAT_TYPE__1 (0x00000004)
5874 #define FLCTL_ERASE_CTLSTAT_TYPE__1_INFO (0x00000004)
5875 #define FLCTL_ERASE_CTLSTAT_TYPE__3 (0x0000000c)
5876 #define FLCTL_ERASE_CTLSTAT_TYPE__3_ENGR (0x0000000c)
5877 #define FLCTL_ERASE_CTLSTAT_TYPE__M (0x0000000c)
5878 #define FLCTL_ERASE_SECTADDR_SECT_ADDRESS__M (0x003fffff)
5879 #define FLCTL_ERASE_TIMCTL_ACTIVE__M (0x0fffff00)
5880 #define FLCTL_ERASE_TIMCTL_HOLD__M (0xf0000000)
5881 #define FLCTL_ERASE_TIMCTL_SETUP__M (0x000000ff)
5882 #define FLCTL_ERSVER_TIMCTL_SETUP__M (0x000000ff)
5883 #define FLCTL_LKGVER_TIMCTL_SETUP__M (0x000000ff)
5884 #define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE__M (0x000000ff)
5885 #define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD__M (0x0000ff00)
5886 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE__0 (0x00000000)
5887 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE__1 (0x00000040)
5888 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PST__0 (0x00000000)
5889 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PST__1 (0x00000080)
5890 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS__0 (0x00000000)
5891 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS__1 (0x00010000)
5892 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS__2 (0x00020000)
5893 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS__3 (0x00030000)
5894 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS__4 (0x00040000)
5895 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS__5 (0x00050000)
5896 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS__7 (0x00070000)
5897 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS__M (0x00070000)
5898 #define FLCTL_PRGBRST_CTLSTAT_LEN__0 (0x00000000)
5899 #define FLCTL_PRGBRST_CTLSTAT_LEN__1 (0x00000008)
5900 #define FLCTL_PRGBRST_CTLSTAT_LEN__2 (0x00000010)
5901 #define FLCTL_PRGBRST_CTLSTAT_LEN__3 (0x00000018)
5902 #define FLCTL_PRGBRST_CTLSTAT_LEN__4 (0x00000020)
5903 #define FLCTL_PRGBRST_CTLSTAT_LEN__5 (0x00000028)
5904 #define FLCTL_PRGBRST_CTLSTAT_LEN__6 (0x00000030)
5905 #define FLCTL_PRGBRST_CTLSTAT_LEN__7 (0x00000038)
5906 #define FLCTL_PRGBRST_CTLSTAT_LEN__M (0x00000038)
5907 #define FLCTL_PRGBRST_CTLSTAT_TYPE__0 (0x00000000)
5908 #define FLCTL_PRGBRST_CTLSTAT_TYPE__0_USER (0x00000000)
5909 #define FLCTL_PRGBRST_CTLSTAT_TYPE__1 (0x00000002)
5910 #define FLCTL_PRGBRST_CTLSTAT_TYPE__1_INFO (0x00000002)
5911 #define FLCTL_PRGBRST_CTLSTAT_TYPE__3 (0x00000006)
5912 #define FLCTL_PRGBRST_CTLSTAT_TYPE__3_ENGR (0x00000006)
5913 #define FLCTL_PRGBRST_CTLSTAT_TYPE__M (0x00000006)
5914 #define FLCTL_PRGBRST_STARTADDR_START_ADDRESS__M (0x003fffff)
5915 #define FLCTL_PRGVER_TIMCTL_ACTIVE__M (0x00000f00)
5916 #define FLCTL_PRGVER_TIMCTL_HOLD__M (0x0000f000)
5917 #define FLCTL_PRGVER_TIMCTL_SETUP__M (0x000000ff)
5918 #define FLCTL_PRG_CTLSTAT_BNK_ACT__0 (0x00000000)
5919 #define FLCTL_PRG_CTLSTAT_BNK_ACT__1 (0x00040000)
5920 #define FLCTL_PRG_CTLSTAT_ENABLE__0 (0x00000000)
5921 #define FLCTL_PRG_CTLSTAT_ENABLE__1 (0x00000001)
5922 #define FLCTL_PRG_CTLSTAT_MODE__0 (0x00000000)
5923 #define FLCTL_PRG_CTLSTAT_MODE__1 (0x00000002)
5924 #define FLCTL_PRG_CTLSTAT_STATUS__0 (0x00000000)
5925 #define FLCTL_PRG_CTLSTAT_STATUS__1 (0x00010000)
5926 #define FLCTL_PRG_CTLSTAT_STATUS__2 (0x00020000)
5927 #define FLCTL_PRG_CTLSTAT_STATUS__M (0x00030000)
5928 #define FLCTL_PRG_CTLSTAT_VER_PRE__0 (0x00000000)
5929 #define FLCTL_PRG_CTLSTAT_VER_PRE__1 (0x00000004)
5930 #define FLCTL_PRG_CTLSTAT_VER_PST__0 (0x00000000)
5931 #define FLCTL_PRG_CTLSTAT_VER_PST__1 (0x00000008)
5932 #define FLCTL_PROGRAM_TIMCTL_ACTIVE__M (0x0fffff00)
5933 #define FLCTL_PROGRAM_TIMCTL_HOLD__M (0xf0000000)
5934 #define FLCTL_PROGRAM_TIMCTL_SETUP__M (0x000000ff)
5935 #define FLCTL_PWRSTAT_IREFSTAT__0 (0x00000000)
5936 #define FLCTL_PWRSTAT_IREFSTAT__0_IREF_NOT_STABLE (0x00000000)
5937 #define FLCTL_PWRSTAT_IREFSTAT__1 (0x00000020)
5938 #define FLCTL_PWRSTAT_IREFSTAT__1_IREF_STABLE (0x00000020)
5939 #define FLCTL_PWRSTAT_LDOSTAT__0 (0x00000000)
5940 #define FLCTL_PWRSTAT_LDOSTAT__0_FLDO_NOT_GOOD (0x00000000)
5941 #define FLCTL_PWRSTAT_LDOSTAT__1 (0x00000008)
5942 #define FLCTL_PWRSTAT_LDOSTAT__1_FLDO_GOOD (0x00000008)
5943 #define FLCTL_PWRSTAT_PSTAT__0 (0x00000000)
5944 #define FLCTL_PWRSTAT_PSTAT__1 (0x00000001)
5945 #define FLCTL_PWRSTAT_PSTAT__2 (0x00000002)
5946 #define FLCTL_PWRSTAT_PSTAT__3 (0x00000003)
5947 #define FLCTL_PWRSTAT_PSTAT__4 (0x00000004)
5948 #define FLCTL_PWRSTAT_PSTAT__4_FLASH_IP_ACTIVE (0x00000004)
5949 #define FLCTL_PWRSTAT_PSTAT__5 (0x00000005)
5950 #define FLCTL_PWRSTAT_PSTAT__6 (0x00000006)
5951 #define FLCTL_PWRSTAT_PSTAT__7 (0x00000007)
5952 #define FLCTL_PWRSTAT_PSTAT__M (0x00000007)
5953 #define FLCTL_PWRSTAT_RD_2T__0 (0x00000000)
5954 #define FLCTL_PWRSTAT_RD_2T__1 (0x00000080)
5955 #define FLCTL_PWRSTAT_TRIMSTAT__0 (0x00000000)
5956 #define FLCTL_PWRSTAT_TRIMSTAT__1 (0x00000040)
5957 #define FLCTL_PWRSTAT_VREFSTAT__0 (0x00000000)
5958 #define FLCTL_PWRSTAT_VREFSTAT__1 (0x00000010)
5959 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT__0 (0x00000000)
5960 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT__0_IDLE (0x00000000)
5961 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT__1 (0x00010000)
5962 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT__2 (0x00020000)
5963 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT__3 (0x00030000)
5964 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT__M (0x00030000)
5965 #define FLCTL_RDBRST_CTLSTAT_DATA_CMP__0 (0x00000000)
5966 #define FLCTL_RDBRST_CTLSTAT_DATA_CMP__1 (0x00000010)
5967 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE__0 (0x00000000)
5968 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE__0_USER (0x00000000)
5969 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE__1 (0x00000002)
5970 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE__1_INFO (0x00000002)
5971 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE__3 (0x00000006)
5972 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE__3_ENGR (0x00000006)
5973 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE__M (0x00000006)
5974 #define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS__M (0x001fffff)
5975 #define FLCTL_RDBRST_FAILCNT_FAIL_COUNT__M (0x0001ffff)
5976 #define FLCTL_RDBRST_LEN_BURST_LENGTH__M (0x001fffff)
5977 #define FLCTL_RDBRST_STARTADDR_START_ADDRESS__M (0x001fffff)
5978 #define FLCTL_RDCTL_BNK0_INFO_PARD__0 (0x00000000)
5979 #define FLCTL_RDCTL_BNK0_INFO_PARD__1 (0x00000200)
5980 #define FLCTL_RDCTL_BNK0_INFO_PARI__0 (0x00000000)
5981 #define FLCTL_RDCTL_BNK0_INFO_PARI__1 (0x00000100)
5982 #define FLCTL_RDCTL_BNK0_RD_MODE_STATUS__0 (0x00000000)
5983 #define FLCTL_RDCTL_BNK0_RD_MODE_STATUS__1 (0x00010000)
5984 #define FLCTL_RDCTL_BNK0_RD_MODE_STATUS__1_READ_MARGIN_0 (0x00010000)
5985 #define FLCTL_RDCTL_BNK0_RD_MODE_STATUS__2 (0x00020000)
5986 #define FLCTL_RDCTL_BNK0_RD_MODE_STATUS__2_READ_MARGIN_1 (0x00020000)
5987 #define FLCTL_RDCTL_BNK0_RD_MODE_STATUS__3 (0x00030000)
5988 #define FLCTL_RDCTL_BNK0_RD_MODE_STATUS__3_PROGRAM_VERIFY (0x00030000)
5989 #define FLCTL_RDCTL_BNK0_RD_MODE_STATUS__4 (0x00040000)
5990 #define FLCTL_RDCTL_BNK0_RD_MODE_STATUS__4_ERASE_VERIFY (0x00040000)
5991 #define FLCTL_RDCTL_BNK0_RD_MODE_STATUS__5 (0x00050000)
5992 #define FLCTL_RDCTL_BNK0_RD_MODE_STATUS__5_LEAKAGE_VERIFY (0x00050000)
5993 #define FLCTL_RDCTL_BNK0_RD_MODE_STATUS__M (0x000f0000)
5994 #define FLCTL_RDCTL_BNK0_RD_MODE__0 (0x00000000)
5995 #define FLCTL_RDCTL_BNK0_RD_MODE__1 (0x00000001)
5996 #define FLCTL_RDCTL_BNK0_RD_MODE__1_READ_MARGIN_0 (0x00000001)
5997 #define FLCTL_RDCTL_BNK0_RD_MODE__2 (0x00000002)
5998 #define FLCTL_RDCTL_BNK0_RD_MODE__2_READ_MARGIN_1 (0x00000002)
5999 #define FLCTL_RDCTL_BNK0_RD_MODE__3 (0x00000003)
6000 #define FLCTL_RDCTL_BNK0_RD_MODE__3_PROGRAM_VERIFY (0x00000003)
6001 #define FLCTL_RDCTL_BNK0_RD_MODE__4 (0x00000004)
6002 #define FLCTL_RDCTL_BNK0_RD_MODE__4_ERASE_VERIFY (0x00000004)
6003 #define FLCTL_RDCTL_BNK0_RD_MODE__5 (0x00000005)
6004 #define FLCTL_RDCTL_BNK0_RD_MODE__5_LEAKAGE_VERIFY (0x00000005)
6005 #define FLCTL_RDCTL_BNK0_RD_MODE__M (0x0000000f)
6006 #define FLCTL_RDCTL_BNK0_USR_PARD__0 (0x00000000)
6007 #define FLCTL_RDCTL_BNK0_USR_PARD__1 (0x00000800)
6008 #define FLCTL_RDCTL_BNK0_USR_PARI__0 (0x00000000)
6009 #define FLCTL_RDCTL_BNK0_USR_PARI__1 (0x00000400)
6010 #define FLCTL_RDCTL_BNK0_WAIT__M (0x0000f000)
6011 #define FLCTL_RDCTL_BNK1_INFO_PARD__0 (0x00000000)
6012 #define FLCTL_RDCTL_BNK1_INFO_PARD__1 (0x00000200)
6013 #define FLCTL_RDCTL_BNK1_INFO_PARI__0 (0x00000000)
6014 #define FLCTL_RDCTL_BNK1_INFO_PARI__1 (0x00000100)
6015 #define FLCTL_RDCTL_BNK1_RD_MODE_STATUS__0 (0x00000000)
6016 #define FLCTL_RDCTL_BNK1_RD_MODE_STATUS__1 (0x00010000)
6017 #define FLCTL_RDCTL_BNK1_RD_MODE_STATUS__1_READ_MARGIN_0 (0x00010000)
6018 #define FLCTL_RDCTL_BNK1_RD_MODE_STATUS__2 (0x00020000)
6019 #define FLCTL_RDCTL_BNK1_RD_MODE_STATUS__2_READ_MARGIN_1 (0x00020000)
6020 #define FLCTL_RDCTL_BNK1_RD_MODE_STATUS__3 (0x00030000)
6021 #define FLCTL_RDCTL_BNK1_RD_MODE_STATUS__3_PROGRAM_VERIFY (0x00030000)
6022 #define FLCTL_RDCTL_BNK1_RD_MODE_STATUS__4 (0x00040000)
6023 #define FLCTL_RDCTL_BNK1_RD_MODE_STATUS__4_ERASE_VERIFY (0x00040000)
6024 #define FLCTL_RDCTL_BNK1_RD_MODE_STATUS__5 (0x00050000)
6025 #define FLCTL_RDCTL_BNK1_RD_MODE_STATUS__5_LEAKAGE_VERIFY (0x00050000)
6026 #define FLCTL_RDCTL_BNK1_RD_MODE_STATUS__M (0x000f0000)
6027 #define FLCTL_RDCTL_BNK1_RD_MODE__0 (0x00000000)
6028 #define FLCTL_RDCTL_BNK1_RD_MODE__1 (0x00000001)
6029 #define FLCTL_RDCTL_BNK1_RD_MODE__1_READ_MARGIN_0 (0x00000001)
6030 #define FLCTL_RDCTL_BNK1_RD_MODE__2 (0x00000002)
6031 #define FLCTL_RDCTL_BNK1_RD_MODE__2_READ_MARGIN_1 (0x00000002)
6032 #define FLCTL_RDCTL_BNK1_RD_MODE__3 (0x00000003)
6033 #define FLCTL_RDCTL_BNK1_RD_MODE__3_PROGRAM_VERIFY (0x00000003)
6034 #define FLCTL_RDCTL_BNK1_RD_MODE__4 (0x00000004)
6035 #define FLCTL_RDCTL_BNK1_RD_MODE__4_ERASE_VERIFY (0x00000004)
6036 #define FLCTL_RDCTL_BNK1_RD_MODE__5 (0x00000005)
6037 #define FLCTL_RDCTL_BNK1_RD_MODE__5_LEAKAGE_VERIFY (0x00000005)
6038 #define FLCTL_RDCTL_BNK1_RD_MODE__M (0x0000000f)
6039 #define FLCTL_RDCTL_BNK1_USR_PARD__0 (0x00000000)
6040 #define FLCTL_RDCTL_BNK1_USR_PARD__1 (0x00000800)
6041 #define FLCTL_RDCTL_BNK1_USR_PARI__0 (0x00000000)
6042 #define FLCTL_RDCTL_BNK1_USR_PARI__1 (0x00000400)
6043 #define FLCTL_RDCTL_BNK1_WAIT__M (0x0000f000)
6044 #define FLCTL_READMARGIN_TIMCTL_SETUP__M (0x000000ff)
6045 #define FLCTL_READ_TIMCTL_IREF_BOOST1__M (0x0000f000)
6046 #define FLCTL_READ_TIMCTL_SETUP_LONG__M (0x00ff0000)
6047 #define FLCTL_READ_TIMCTL_SETUP__M (0x000000ff)
6048 #define FPB_FP_COMP0_COMP__M (0x1ffffffc)
6049 #define FPB_FP_COMP0_ENABLE__0 (0x00000000)
6050 #define FPB_FP_COMP0_ENABLE__1 (0x00000001)
6051 #define FPB_FP_COMP0_REPLACE__0 (0x00000000)
6052 #define FPB_FP_COMP0_REPLACE__1 (0x40000000)
6053 #define FPB_FP_COMP0_REPLACE__2 (0x80000000)
6054 #define FPB_FP_COMP0_REPLACE__3 (0xc0000000)
6055 #define FPB_FP_COMP0_REPLACE__M (0xc0000000)
6056 #define FPB_FP_COMP1_COMP__M (0x1ffffffc)
6057 #define FPB_FP_COMP1_ENABLE__0 (0x00000000)
6058 #define FPB_FP_COMP1_ENABLE__1 (0x00000001)
6059 #define FPB_FP_COMP1_REPLACE__0 (0x00000000)
6060 #define FPB_FP_COMP1_REPLACE__1 (0x40000000)
6061 #define FPB_FP_COMP1_REPLACE__2 (0x80000000)
6062 #define FPB_FP_COMP1_REPLACE__3 (0xc0000000)
6063 #define FPB_FP_COMP1_REPLACE__M (0xc0000000)
6064 #define FPB_FP_COMP2_COMP__M (0x1ffffffc)
6065 #define FPB_FP_COMP2_ENABLE__0 (0x00000000)
6066 #define FPB_FP_COMP2_ENABLE__1 (0x00000001)
6067 #define FPB_FP_COMP2_REPLACE__0 (0x00000000)
6068 #define FPB_FP_COMP2_REPLACE__1 (0x40000000)
6069 #define FPB_FP_COMP2_REPLACE__2 (0x80000000)
6070 #define FPB_FP_COMP2_REPLACE__3 (0xc0000000)
6071 #define FPB_FP_COMP2_REPLACE__M (0xc0000000)
6072 #define FPB_FP_COMP3_COMP__M (0x1ffffffc)
6073 #define FPB_FP_COMP3_ENABLE__0 (0x00000000)
6074 #define FPB_FP_COMP3_ENABLE__1 (0x00000001)
6075 #define FPB_FP_COMP3_REPLACE__0 (0x00000000)
6076 #define FPB_FP_COMP3_REPLACE__1 (0x40000000)
6077 #define FPB_FP_COMP3_REPLACE__2 (0x80000000)
6078 #define FPB_FP_COMP3_REPLACE__3 (0xc0000000)
6079 #define FPB_FP_COMP3_REPLACE__M (0xc0000000)
6080 #define FPB_FP_COMP4_COMP__M (0x1ffffffc)
6081 #define FPB_FP_COMP4_ENABLE__0 (0x00000000)
6082 #define FPB_FP_COMP4_ENABLE__1 (0x00000001)
6083 #define FPB_FP_COMP4_REPLACE__0 (0x00000000)
6084 #define FPB_FP_COMP4_REPLACE__1 (0x40000000)
6085 #define FPB_FP_COMP4_REPLACE__2 (0x80000000)
6086 #define FPB_FP_COMP4_REPLACE__3 (0xc0000000)
6087 #define FPB_FP_COMP4_REPLACE__M (0xc0000000)
6088 #define FPB_FP_COMP5_COMP__M (0x1ffffffc)
6089 #define FPB_FP_COMP5_ENABLE__0 (0x00000000)
6090 #define FPB_FP_COMP5_ENABLE__1 (0x00000001)
6091 #define FPB_FP_COMP5_REPLACE__0 (0x00000000)
6092 #define FPB_FP_COMP5_REPLACE__1 (0x40000000)
6093 #define FPB_FP_COMP5_REPLACE__2 (0x80000000)
6094 #define FPB_FP_COMP5_REPLACE__3 (0xc0000000)
6095 #define FPB_FP_COMP5_REPLACE__M (0xc0000000)
6096 #define FPB_FP_COMP6_COMP__M (0x1ffffffc)
6097 #define FPB_FP_COMP6_ENABLE__0 (0x00000000)
6098 #define FPB_FP_COMP6_ENABLE__1 (0x00000001)
6099 #define FPB_FP_COMP6_REPLACE__0 (0x00000000)
6100 #define FPB_FP_COMP6_REPLACE__1 (0x40000000)
6101 #define FPB_FP_COMP6_REPLACE__2 (0x80000000)
6102 #define FPB_FP_COMP6_REPLACE__3 (0xc0000000)
6103 #define FPB_FP_COMP6_REPLACE__M (0xc0000000)
6104 #define FPB_FP_COMP7_COMP__M (0x1ffffffc)
6105 #define FPB_FP_COMP7_ENABLE__0 (0x00000000)
6106 #define FPB_FP_COMP7_ENABLE__1 (0x00000001)
6107 #define FPB_FP_COMP7_REPLACE__0 (0x00000000)
6108 #define FPB_FP_COMP7_REPLACE__1 (0x40000000)
6109 #define FPB_FP_COMP7_REPLACE__2 (0x80000000)
6110 #define FPB_FP_COMP7_REPLACE__3 (0xc0000000)
6111 #define FPB_FP_COMP7_REPLACE__M (0xc0000000)
6112 #define FPB_FP_CTRL_ENABLE__0 (0x00000000)
6113 #define FPB_FP_CTRL_ENABLE__1 (0x00000001)
6114 #define FPB_FP_CTRL_NUM_CODE1__0 (0x00000000)
6115 #define FPB_FP_CTRL_NUM_CODE1__0_NO_CODE_SLOTS (0x00000000)
6116 #define FPB_FP_CTRL_NUM_CODE1__2 (0x00000020)
6117 #define FPB_FP_CTRL_NUM_CODE1__2_TWO_CODE_SLOTS (0x00000020)
6118 #define FPB_FP_CTRL_NUM_CODE1__6 (0x00000060)
6119 #define FPB_FP_CTRL_NUM_CODE1__6_SIX_CODE_SLOTS (0x00000060)
6120 #define FPB_FP_CTRL_NUM_CODE1__M (0x000000f0)
6121 #define FPB_FP_CTRL_NUM_CODE2__M (0x00003000)
6122 #define FPB_FP_CTRL_NUM_LIT__0 (0x00000000)
6123 #define FPB_FP_CTRL_NUM_LIT__2 (0x00000200)
6124 #define FPB_FP_CTRL_NUM_LIT__M (0x00000f00)
6125 #define FPB_FP_REMAP_REMAP__M (0x1fffffe0)
6126 #define FPU_CPACR_CP10__M (0x00300000)
6127 #define FPU_CPACR_CP11__M (0x00c00000)
6128 #define FPU_FPCAR_ADDRESS__M (0x7ffffffc)
6129 #define FPU_FPDSCR_RMODE__M (0x00c00000)
6130 #define FPU_MVFR0_A_SIMD_REGISTERS__M (0x0000000f)
6131 #define FPU_MVFR0_DIVIDE__M (0x000f0000)
6132 #define FPU_MVFR0_DOUBLE_PRECISION__M (0x00000f00)
6133 #define FPU_MVFR0_FP_ECEPTION_TRAPPING__M (0x0000f000)
6134 #define FPU_MVFR0_FP_ROUNDING_MODES__M (0xf0000000)
6135 #define FPU_MVFR0_SHORT_VECTORS__M (0x0f000000)
6136 #define FPU_MVFR0_SINGLE_PRECISION__M (0x000000f0)
6137 #define FPU_MVFR0_SQUARE_ROOT__M (0x00f00000)
6138 #define FPU_MVFR1_D_NAN_MODE__M (0x000000f0)
6139 #define FPU_MVFR1_FP_FUSED_MAC__M (0xf0000000)
6140 #define FPU_MVFR1_FP_HPFP__M (0x0f000000)
6141 #define FPU_MVFR1_FTZ_MODE__M (0x0000000f)
6142 #define HFXT2DRIVE (0x00000001)
6143 #define HFXT2FREQ__0 (0x00000000)
6144 #define HFXT2FREQ__1 (0x00000010)
6145 #define HFXT2FREQ__2 (0x00000020)
6146 #define HFXT2FREQ__3 (0x00000030)
6147 #define HFXT2FREQ__4 (0x00000040)
6148 #define HFXT2FREQ__5 (0x00000050)
6149 #define HFXT2FREQ__6 (0x00000060)
6150 #define HFXT2FREQ__7 (0x00000070)
6151 #define HFXTFREQ__0 (0x00000000)
6152 #define HFXTFREQ__1 (0x00100000)
6153 #define HFXTFREQ__2 (0x00200000)
6154 #define HFXTFREQ__3 (0x00300000)
6155 #define HFXTFREQ__4 (0x00400000)
6156 #define HFXTFREQ__5 (0x00500000)
6157 #define HFXTFREQ__6 (0x00600000)
6158 #define HFXTFREQ__7 (0x00700000)
6159 #define ID0 (0x0040)
6160 #define ID1 (0x0080)
6161 #define ITM_ITM_IMCR (HWREG32(0xE0000F00))
6162 #define ITM_ITM_IMCR_INTEGRATION (0x00000001)
6163 #define ITM_ITM_IMCR_INTEGRATION__0 (0x00000000)
6164 #define ITM_ITM_IMCR_INTEGRATION__0_ATVALIDM_NORMAL (0x00000000)
6165 #define ITM_ITM_IMCR_INTEGRATION__1 (0x00000001)
6166 #define ITM_ITM_IWR (HWREG32(0xE0000EF8))
6167 #define ITM_ITM_IWR_ATVALIDM (0x00000001)
6168 #define ITM_ITM_IWR_ATVALIDM__0 (0x00000000)
6169 #define ITM_ITM_IWR_ATVALIDM__0_ATVALIDM_CLEAR (0x00000000)
6170 #define ITM_ITM_IWR_ATVALIDM__1 (0x00000001)
6171 #define ITM_ITM_IWR_ATVALIDM__1_ATVALIDM_SET (0x00000001)
6172 #define ITM_ITM_LAR (HWREG32(0xE0000FB0))
6173 #define ITM_ITM_LSR (HWREG32(0xE0000FB4))
6174 #define ITM_ITM_LSR_ACCESS (0x00000002)
6175 #define ITM_ITM_LSR_BYTEACC (0x00000004)
6176 #define ITM_ITM_LSR_PRESENT (0x00000001)
6177 #define ITM_ITM_STIM0 (HWREG32(0xE0000000))
6178 #define ITM_ITM_STIM1 (HWREG32(0xE0000004))
6179 #define ITM_ITM_STIM10 (HWREG32(0xE0000028))
6180 #define ITM_ITM_STIM11 (HWREG32(0xE000002C))
6181 #define ITM_ITM_STIM12 (HWREG32(0xE0000030))
6182 #define ITM_ITM_STIM13 (HWREG32(0xE0000034))
6183 #define ITM_ITM_STIM14 (HWREG32(0xE0000038))
6184 #define ITM_ITM_STIM15 (HWREG32(0xE000003C))
6185 #define ITM_ITM_STIM16 (HWREG32(0xE0000040))
6186 #define ITM_ITM_STIM17 (HWREG32(0xE0000044))
6187 #define ITM_ITM_STIM18 (HWREG32(0xE0000048))
6188 #define ITM_ITM_STIM19 (HWREG32(0xE000004C))
6189 #define ITM_ITM_STIM2 (HWREG32(0xE0000008))
6190 #define ITM_ITM_STIM20 (HWREG32(0xE0000050))
6191 #define ITM_ITM_STIM21 (HWREG32(0xE0000054))
6192 #define ITM_ITM_STIM22 (HWREG32(0xE0000058))
6193 #define ITM_ITM_STIM23 (HWREG32(0xE000005C))
6194 #define ITM_ITM_STIM24 (HWREG32(0xE0000060))
6195 #define ITM_ITM_STIM25 (HWREG32(0xE0000064))
6196 #define ITM_ITM_STIM26 (HWREG32(0xE0000068))
6197 #define ITM_ITM_STIM27 (HWREG32(0xE000006C))
6198 #define ITM_ITM_STIM28 (HWREG32(0xE0000070))
6199 #define ITM_ITM_STIM29 (HWREG32(0xE0000074))
6200 #define ITM_ITM_STIM3 (HWREG32(0xE000000C))
6201 #define ITM_ITM_STIM30 (HWREG32(0xE0000078))
6202 #define ITM_ITM_STIM31 (HWREG32(0xE000007C))
6203 #define ITM_ITM_STIM4 (HWREG32(0xE0000010))
6204 #define ITM_ITM_STIM5 (HWREG32(0xE0000014))
6205 #define ITM_ITM_STIM6 (HWREG32(0xE0000018))
6206 #define ITM_ITM_STIM7 (HWREG32(0xE000001C))
6207 #define ITM_ITM_STIM8 (HWREG32(0xE0000020))
6208 #define ITM_ITM_STIM9 (HWREG32(0xE0000024))
6209 #define ITM_ITM_TCR (HWREG32(0xE0000E80))
6210 #define ITM_ITM_TCR_ATBID__M (0x007f0000)
6211 #define ITM_ITM_TCR_BUSY (0x00800000)
6212 #define ITM_ITM_TCR_DWTENA (0x00000008)
6213 #define ITM_ITM_TCR_ITMENA (0x00000001)
6214 #define ITM_ITM_TCR_SWOENA (0x00000010)
6215 #define ITM_ITM_TCR_SYNCENA (0x00000004)
6216 #define ITM_ITM_TCR_TSENA (0x00000002)
6217 #define ITM_ITM_TCR_TSPRESCALE__0 (0x00000000)
6218 #define ITM_ITM_TCR_TSPRESCALE__0_NO_PRESCALING (0x00000000)
6219 #define ITM_ITM_TCR_TSPRESCALE__1 (0x00000100)
6220 #define ITM_ITM_TCR_TSPRESCALE__1_DIVIDE_BY_4 (0x00000100)
6221 #define ITM_ITM_TCR_TSPRESCALE__2 (0x00000200)
6222 #define ITM_ITM_TCR_TSPRESCALE__2_DIVIDE_BY_16 (0x00000200)
6223 #define ITM_ITM_TCR_TSPRESCALE__3 (0x00000300)
6224 #define ITM_ITM_TCR_TSPRESCALE__3_DIVIDE_BY_64 (0x00000300)
6225 #define ITM_ITM_TCR_TSPRESCALE__M (0x00000300)
6226 #define ITM_ITM_TER (HWREG32(0xE0000E00))
6227 #define ITM_ITM_TPR (HWREG32(0xE0000E40))
6228 #define ITM_ITM_TPR_PRIVMASK__M (0x0000000f)
6229 #define LFXTDRIVE__0 (0x00000000)
6230 #define LFXTDRIVE__1 (0x00000001)
6231 #define LFXTDRIVE__2 (0x00000002)
6232 #define LFXTDRIVE__3 (0x00000003)
6233 #define LFXTDRIVE__4 (0x00000004)
6234 #define LFXTDRIVE__5 (0x00000005)
6235 #define LFXTDRIVE__6 (0x00000006)
6236 #define LFXTDRIVE__7 (0x00000007)
6237 #define MC0 (0x0010)
6238 #define MC1 (0x0020)
6239 #define MC__CONTINOUS (2*0x10u)
6240 #define MPU_CTRL_ENABLE__0 (0x00000000)
6241 #define MPU_CTRL_ENABLE__0_DISABLE_MPU (0x00000000)
6242 #define MPU_CTRL_ENABLE__1 (0x00000001)
6243 #define MPU_CTRL_ENABLE__1_ENABLE_MPU (0x00000001)
6244 #define MPU_RASR_AP__0 (0x00000000)
6245 #define MPU_RASR_AP__1 (0x01000000)
6246 #define MPU_RASR_AP__2 (0x02000000)
6247 #define MPU_RASR_AP__3 (0x03000000)
6248 #define MPU_RASR_AP__5 (0x05000000)
6249 #define MPU_RASR_AP__6 (0x06000000)
6250 #define MPU_RASR_AP__7 (0x07000000)
6251 #define MPU_RASR_AP__M (0x07000000)
6252 #define MPU_RASR_B__0 (0x00000000)
6253 #define MPU_RASR_B__0_NOT_BUFFERABLE (0x00000000)
6254 #define MPU_RASR_B__1 (0x00010000)
6255 #define MPU_RASR_B__1_BUFFERABLE (0x00010000)
6256 #define MPU_RASR_C__0 (0x00000000)
6257 #define MPU_RASR_C__0_NOT_CACHEABLE (0x00000000)
6258 #define MPU_RASR_C__1 (0x00020000)
6259 #define MPU_RASR_C__1_CACHEABLE (0x00020000)
6260 #define MPU_RASR_SIZE__0 (0x00000000)
6261 #define MPU_RASR_SIZE__0_4KB (0x00000000)
6262 #define MPU_RASR_SIZE__1 (0x00000002)
6263 #define MPU_RASR_SIZE__10 (0x00000014)
6264 #define MPU_RASR_SIZE__10_2KB (0x00000014)
6265 #define MPU_RASR_SIZE__12 (0x00000018)
6266 #define MPU_RASR_SIZE__12_8KB (0x00000018)
6267 #define MPU_RASR_SIZE__13 (0x0000001a)
6268 #define MPU_RASR_SIZE__13_16KB (0x0000001a)
6269 #define MPU_RASR_SIZE__14 (0x0000001c)
6270 #define MPU_RASR_SIZE__14_32KB (0x0000001c)
6271 #define MPU_RASR_SIZE__15 (0x0000001e)
6272 #define MPU_RASR_SIZE__15_64KB (0x0000001e)
6273 #define MPU_RASR_SIZE__16 (0x00000020)
6274 #define MPU_RASR_SIZE__16_128KB (0x00000020)
6275 #define MPU_RASR_SIZE__17 (0x00000022)
6276 #define MPU_RASR_SIZE__17_256KB (0x00000022)
6277 #define MPU_RASR_SIZE__18 (0x00000024)
6278 #define MPU_RASR_SIZE__18_512KB (0x00000024)
6279 #define MPU_RASR_SIZE__19 (0x00000026)
6280 #define MPU_RASR_SIZE__19_1MB (0x00000026)
6281 #define MPU_RASR_SIZE__1_256MB (0x00000002)
6282 #define MPU_RASR_SIZE__20 (0x00000028)
6283 #define MPU_RASR_SIZE__20_2MB (0x00000028)
6284 #define MPU_RASR_SIZE__21 (0x0000002a)
6285 #define MPU_RASR_SIZE__21_4MB (0x0000002a)
6286 #define MPU_RASR_SIZE__22 (0x0000002c)
6287 #define MPU_RASR_SIZE__22_8MB (0x0000002c)
6288 #define MPU_RASR_SIZE__23 (0x0000002e)
6289 #define MPU_RASR_SIZE__23_16MB (0x0000002e)
6290 #define MPU_RASR_SIZE__24 (0x00000030)
6291 #define MPU_RASR_SIZE__24_32MB (0x00000030)
6292 #define MPU_RASR_SIZE__25 (0x00000032)
6293 #define MPU_RASR_SIZE__25_64MB (0x00000032)
6294 #define MPU_RASR_SIZE__26 (0x00000034)
6295 #define MPU_RASR_SIZE__26_128MB (0x00000034)
6296 #define MPU_RASR_SIZE__28 (0x00000038)
6297 #define MPU_RASR_SIZE__28_512MB (0x00000038)
6298 #define MPU_RASR_SIZE__29 (0x0000003a)
6299 #define MPU_RASR_SIZE__29_1GB (0x0000003a)
6300 #define MPU_RASR_SIZE__30 (0x0000003c)
6301 #define MPU_RASR_SIZE__30_2GB (0x0000003c)
6302 #define MPU_RASR_SIZE__31 (0x0000003e)
6303 #define MPU_RASR_SIZE__31_4GB (0x0000003e)
6304 #define MPU_RASR_SIZE__4_32B (0x00000008)
6305 #define MPU_RASR_SIZE__5 (0x0000000a)
6306 #define MPU_RASR_SIZE__5_64B (0x0000000a)
6307 #define MPU_RASR_SIZE__6 (0x0000000c)
6308 #define MPU_RASR_SIZE__6_128B (0x0000000c)
6309 #define MPU_RASR_SIZE__7 (0x0000000e)
6310 #define MPU_RASR_SIZE__7_256B (0x0000000e)
6311 #define MPU_RASR_SIZE__8 (0x00000010)
6312 #define MPU_RASR_SIZE__8_512B (0x00000010)
6313 #define MPU_RASR_SIZE__9 (0x00000012)
6314 #define MPU_RASR_SIZE__9_1KB (0x00000012)
6315 #define MPU_RASR_SIZE__M (0x0000003e)
6316 #define MPU_RASR_SRD__M (0x0000ff00)
6317 #define MPU_RASR_S__0 (0x00000000)
6318 #define MPU_RASR_S__0_NOT_SHAREABLE (0x00000000)
6319 #define MPU_RASR_S__1 (0x00040000)
6320 #define MPU_RASR_S__1_SHAREABLE (0x00040000)
6321 #define MPU_RASR_TEX__M (0x00380000)
6322 #define MPU_RASR_XN__0 (0x00000000)
6323 #define MPU_RASR_XN__1 (0x10000000)
6324 #define MPU_RBAR_ADDR__M (0xffffffe0)
6325 #define MPU_RBAR_REGION__M (0x0000000f)
6326 #define MPU_RBAR_VALID__0 (0x00000000)
6327 #define MPU_RBAR_VALID__1 (0x00000010)
6328 #define MPU_RNR_REGION__M (0x000000ff)
6329 #define MPU_TYPE_DREGION__M (0x0000ff00)
6330 #define MPU_TYPE_IREGION__M (0x00ff0000)
6331 #define OFS_ADC14CLRIFGR0 (0x0000014C)
6332 #define OFS_ADC14CLRIFGR1 (0x00000150)
6333 #define OFS_ADC14CTL0 (0x00000000)
6334 #define OFS_ADC14CTL1 (0x00000004)
6335 #define OFS_ADC14DBG0 (0x00000340)
6336 #define OFS_ADC14DSCR0 (0x00000380)
6337 #define OFS_ADC14HI0 (0x0000000C)
6338 #define OFS_ADC14HI1 (0x00000014)
6339 #define OFS_ADC14IER0 (0x0000013C)
6340 #define OFS_ADC14IER1 (0x00000140)
6341 #define OFS_ADC14IFGR0 (0x00000144)
6342 #define OFS_ADC14IFGR1 (0x00000148)
6343 #define OFS_ADC14IV (0x00000154)
6344 #define OFS_ADC14LO0 (0x00000008)
6345 #define OFS_ADC14LO1 (0x00000010)
6346 #define OFS_ADC14MCTL0 (0x00000018)
6347 #define OFS_ADC14MCTL1 (0x0000001C)
6348 #define OFS_ADC14MCTL10 (0x00000040)
6349 #define OFS_ADC14MCTL11 (0x00000044)
6350 #define OFS_ADC14MCTL12 (0x00000048)
6351 #define OFS_ADC14MCTL13 (0x0000004C)
6352 #define OFS_ADC14MCTL14 (0x00000050)
6353 #define OFS_ADC14MCTL15 (0x00000054)
6354 #define OFS_ADC14MCTL16 (0x00000058)
6355 #define OFS_ADC14MCTL17 (0x0000005C)
6356 #define OFS_ADC14MCTL18 (0x00000060)
6357 #define OFS_ADC14MCTL19 (0x00000064)
6358 #define OFS_ADC14MCTL2 (0x00000020)
6359 #define OFS_ADC14MCTL20 (0x00000068)
6360 #define OFS_ADC14MCTL21 (0x0000006C)
6361 #define OFS_ADC14MCTL22 (0x00000070)
6362 #define OFS_ADC14MCTL23 (0x00000074)
6363 #define OFS_ADC14MCTL24 (0x00000078)
6364 #define OFS_ADC14MCTL25 (0x0000007C)
6365 #define OFS_ADC14MCTL26 (0x00000080)
6366 #define OFS_ADC14MCTL27 (0x00000084)
6367 #define OFS_ADC14MCTL28 (0x00000088)
6368 #define OFS_ADC14MCTL29 (0x0000008C)
6369 #define OFS_ADC14MCTL3 (0x00000024)
6370 #define OFS_ADC14MCTL30 (0x00000090)
6371 #define OFS_ADC14MCTL31 (0x00000094)
6372 #define OFS_ADC14MCTL4 (0x00000028)
6373 #define OFS_ADC14MCTL5 (0x0000002C)
6374 #define OFS_ADC14MCTL6 (0x00000030)
6375 #define OFS_ADC14MCTL7 (0x00000034)
6376 #define OFS_ADC14MCTL8 (0x00000038)
6377 #define OFS_ADC14MCTL9 (0x0000003C)
6378 #define OFS_ADC14MEM0 (0x00000098)
6379 #define OFS_ADC14MEM1 (0x0000009C)
6380 #define OFS_ADC14MEM10 (0x000000C0)
6381 #define OFS_ADC14MEM11 (0x000000C4)
6382 #define OFS_ADC14MEM12 (0x000000C8)
6383 #define OFS_ADC14MEM13 (0x000000CC)
6384 #define OFS_ADC14MEM14 (0x000000D0)
6385 #define OFS_ADC14MEM15 (0x000000D4)
6386 #define OFS_ADC14MEM16 (0x000000D8)
6387 #define OFS_ADC14MEM17 (0x000000DC)
6388 #define OFS_ADC14MEM18 (0x000000E0)
6389 #define OFS_ADC14MEM19 (0x000000E4)
6390 #define OFS_ADC14MEM2 (0x000000A0)
6391 #define OFS_ADC14MEM20 (0x000000E8)
6392 #define OFS_ADC14MEM21 (0x000000EC)
6393 #define OFS_ADC14MEM22 (0x000000F0)
6394 #define OFS_ADC14MEM23 (0x000000F4)
6395 #define OFS_ADC14MEM24 (0x000000F8)
6396 #define OFS_ADC14MEM25 (0x000000FC)
6397 #define OFS_ADC14MEM26 (0x00000100)
6398 #define OFS_ADC14MEM27 (0x00000104)
6399 #define OFS_ADC14MEM28 (0x00000108)
6400 #define OFS_ADC14MEM29 (0x0000010C)
6401 #define OFS_ADC14MEM3 (0x000000A4)
6402 #define OFS_ADC14MEM30 (0x00000110)
6403 #define OFS_ADC14MEM31 (0x00000114)
6404 #define OFS_ADC14MEM4 (0x000000A8)
6405 #define OFS_ADC14MEM5 (0x000000AC)
6406 #define OFS_ADC14MEM6 (0x000000B0)
6407 #define OFS_ADC14MEM7 (0x000000B4)
6408 #define OFS_ADC14MEM8 (0x000000B8)
6409 #define OFS_ADC14MEM9 (0x000000BC)
6410 #define OFS_ADC14TEST0 (0x00000300)
6411 #define OFS_ADC14TEST1 (0x00000304)
6412 #define OFS_ADC14TEST2 (0x00000308)
6413 #define OFS_ADC14TEST3 (0x0000030C)
6414 #define OFS_ADC14TEST4 (0x00000310)
6415 #define OFS_ADC14TEST5 (0x00000314)
6416 #define OFS_ADC14TEST6 (0x00000318)
6417 #define OFS_ADC14TEST7 (0x0000031C)
6418 #define OFS_ADC14_CLRIFGR0 (0x0000014C)
6419 #define OFS_ADC14_CLRIFGR1 (0x00000150)
6420 #define OFS_ADC14_CTL0 (0x00000000)
6421 #define OFS_ADC14_CTL1 (0x00000004)
6422 #define OFS_ADC14_HI0 (0x0000000C)
6423 #define OFS_ADC14_HI1 (0x00000014)
6424 #define OFS_ADC14_IER0 (0x0000013C)
6425 #define OFS_ADC14_IER1 (0x00000140)
6426 #define OFS_ADC14_IFGR0 (0x00000144)
6427 #define OFS_ADC14_IFGR1 (0x00000148)
6428 #define OFS_ADC14_IV (0x00000154)
6429 #define OFS_ADC14_LO0 (0x00000008)
6430 #define OFS_ADC14_LO1 (0x00000010)
6431 #define OFS_ADC14_MCTL0 (0x00000018)
6432 #define OFS_ADC14_MCTL1 (0x0000001C)
6433 #define OFS_ADC14_MCTL10 (0x00000040)
6434 #define OFS_ADC14_MCTL11 (0x00000044)
6435 #define OFS_ADC14_MCTL12 (0x00000048)
6436 #define OFS_ADC14_MCTL13 (0x0000004C)
6437 #define OFS_ADC14_MCTL14 (0x00000050)
6438 #define OFS_ADC14_MCTL15 (0x00000054)
6439 #define OFS_ADC14_MCTL16 (0x00000058)
6440 #define OFS_ADC14_MCTL17 (0x0000005C)
6441 #define OFS_ADC14_MCTL18 (0x00000060)
6442 #define OFS_ADC14_MCTL19 (0x00000064)
6443 #define OFS_ADC14_MCTL2 (0x00000020)
6444 #define OFS_ADC14_MCTL20 (0x00000068)
6445 #define OFS_ADC14_MCTL21 (0x0000006C)
6446 #define OFS_ADC14_MCTL22 (0x00000070)
6447 #define OFS_ADC14_MCTL23 (0x00000074)
6448 #define OFS_ADC14_MCTL24 (0x00000078)
6449 #define OFS_ADC14_MCTL25 (0x0000007C)
6450 #define OFS_ADC14_MCTL26 (0x00000080)
6451 #define OFS_ADC14_MCTL27 (0x00000084)
6452 #define OFS_ADC14_MCTL28 (0x00000088)
6453 #define OFS_ADC14_MCTL29 (0x0000008C)
6454 #define OFS_ADC14_MCTL3 (0x00000024)
6455 #define OFS_ADC14_MCTL30 (0x00000090)
6456 #define OFS_ADC14_MCTL31 (0x00000094)
6457 #define OFS_ADC14_MCTL4 (0x00000028)
6458 #define OFS_ADC14_MCTL5 (0x0000002C)
6459 #define OFS_ADC14_MCTL6 (0x00000030)
6460 #define OFS_ADC14_MCTL7 (0x00000034)
6461 #define OFS_ADC14_MCTL8 (0x00000038)
6462 #define OFS_ADC14_MCTL9 (0x0000003C)
6463 #define OFS_ADC14_MEM0 (0x00000098)
6464 #define OFS_ADC14_MEM1 (0x0000009C)
6465 #define OFS_ADC14_MEM10 (0x000000C0)
6466 #define OFS_ADC14_MEM11 (0x000000C4)
6467 #define OFS_ADC14_MEM12 (0x000000C8)
6468 #define OFS_ADC14_MEM13 (0x000000CC)
6469 #define OFS_ADC14_MEM14 (0x000000D0)
6470 #define OFS_ADC14_MEM15 (0x000000D4)
6471 #define OFS_ADC14_MEM16 (0x000000D8)
6472 #define OFS_ADC14_MEM17 (0x000000DC)
6473 #define OFS_ADC14_MEM18 (0x000000E0)
6474 #define OFS_ADC14_MEM19 (0x000000E4)
6475 #define OFS_ADC14_MEM2 (0x000000A0)
6476 #define OFS_ADC14_MEM20 (0x000000E8)
6477 #define OFS_ADC14_MEM21 (0x000000EC)
6478 #define OFS_ADC14_MEM22 (0x000000F0)
6479 #define OFS_ADC14_MEM23 (0x000000F4)
6480 #define OFS_ADC14_MEM24 (0x000000F8)
6481 #define OFS_ADC14_MEM25 (0x000000FC)
6482 #define OFS_ADC14_MEM26 (0x00000100)
6483 #define OFS_ADC14_MEM27 (0x00000104)
6484 #define OFS_ADC14_MEM28 (0x00000108)
6485 #define OFS_ADC14_MEM29 (0x0000010C)
6486 #define OFS_ADC14_MEM3 (0x000000A4)
6487 #define OFS_ADC14_MEM30 (0x00000110)
6488 #define OFS_ADC14_MEM31 (0x00000114)
6489 #define OFS_ADC14_MEM4 (0x000000A8)
6490 #define OFS_ADC14_MEM5 (0x000000AC)
6491 #define OFS_ADC14_MEM6 (0x000000B0)
6492 #define OFS_ADC14_MEM7 (0x000000B4)
6493 #define OFS_ADC14_MEM8 (0x000000B8)
6494 #define OFS_ADC14_MEM9 (0x000000BC)
6495 #define OFS_AES256_ACTL0 (0x00000000)
6496 #define OFS_AES256_ACTL1 (0x00000002)
6497 #define OFS_AES256_ADIN (0x00000008)
6498 #define OFS_AES256_ADOUT (0x0000000A)
6499 #define OFS_AES256_AKEY (0x00000006)
6500 #define OFS_AES256_ASTAT (0x00000004)
6501 #define OFS_AES256_AXDIN (0x0000000C)
6502 #define OFS_AES256_AXIN (0x0000000E)
6503 #define OFS_AESACTL0 (OFS_AES256_ACTL0)
6504 #define OFS_AESACTL0_H (OFS_AESACTL0+1)
6505 #define OFS_AESACTL0_L (OFS_AESACTL0)
6506 #define OFS_AESACTL1 (OFS_AES256_ACTL1)
6507 #define OFS_AESACTL1_H (OFS_AESACTL1+1)
6508 #define OFS_AESACTL1_L (OFS_AESACTL1)
6509 #define OFS_AESADIN (OFS_AES256_ADIN)
6510 #define OFS_AESADIN_H (OFS_AESADIN+1)
6511 #define OFS_AESADIN_L (OFS_AESADIN)
6512 #define OFS_AESADOUT (OFS_AES256_ADOUT)
6513 #define OFS_AESADOUT_H (OFS_AESADOUT+1)
6514 #define OFS_AESADOUT_L (OFS_AESADOUT)
6515 #define OFS_AESAKEY (OFS_AES256_AKEY)
6516 #define OFS_AESAKEY_H (OFS_AESAKEY+1)
6517 #define OFS_AESAKEY_L (OFS_AESAKEY)
6518 #define OFS_AESASTAT (OFS_AES256_ASTAT)
6519 #define OFS_AESASTAT_H (OFS_AESASTAT+1)
6520 #define OFS_AESASTAT_L (OFS_AESASTAT)
6521 #define OFS_AESAXDIN (OFS_AES256_AXDIN)
6522 #define OFS_AESAXDIN_H (OFS_AESAXDIN+1)
6523 #define OFS_AESAXDIN_L (OFS_AESAXDIN)
6524 #define OFS_AESAXIN (OFS_AES256_AXIN)
6525 #define OFS_AESAXIN_H (OFS_AESAXIN+1)
6526 #define OFS_AESAXIN_L (OFS_AESAXIN)
6527 #define OFS_BCD2BIN (0x001E)
6528 #define OFS_BIN2BCD (0x001C)
6529 #define OFS_CAPSIOxCTL (OFS_CAPTIO0_CTL)
6530 #define OFS_CAPSIOxCTL_H (OFS_CAPSIOxCTL+1)
6531 #define OFS_CAPSIOxCTL_L (OFS_CAPSIOxCTL)
6532 #define OFS_CAPTIO0_CTL (0x0000000E)
6533 #define OFS_CAPTIO1_CTL (0x0000000E)
6534 #define OFS_CE0CTL0 (OFS_COMP_E0CTL0)
6535 #define OFS_CE0CTL0_H (OFS_CE0CTL0+1)
6536 #define OFS_CE0CTL0_L (OFS_CE0CTL0)
6537 #define OFS_CE0CTL1 (OFS_COMP_E0CTL1)
6538 #define OFS_CE0CTL1_H (OFS_CE0CTL1+1)
6539 #define OFS_CE0CTL1_L (OFS_CE0CTL1)
6540 #define OFS_CE0CTL2 (OFS_COMP_E0CTL2)
6541 #define OFS_CE0CTL2_H (OFS_CE0CTL2+1)
6542 #define OFS_CE0CTL2_L (OFS_CE0CTL2)
6543 #define OFS_CE0CTL3 (OFS_COMP_E0CTL3)
6544 #define OFS_CE0CTL3_H (OFS_CE0CTL3+1)
6545 #define OFS_CE0CTL3_L (OFS_CE0CTL3)
6546 #define OFS_CE0INT (OFS_COMP_E0INT)
6547 #define OFS_CE0INT_H (OFS_CE0INT+1)
6548 #define OFS_CE0INT_L (OFS_CE0INT)
6549 #define OFS_CE0IV (OFS_COMP_E0IV)
6550 #define OFS_CE0IV_H (OFS_CE0IV+1)
6551 #define OFS_CE0IV_L (OFS_CE0IV)
6552 #define OFS_CECTL0 (OFS_COMP_E0_CTL0)
6553 #define OFS_CECTL0_H (OFS_CECTL0+1)
6554 #define OFS_CECTL0_L (OFS_CECTL0)
6555 #define OFS_CECTL1 (OFS_COMP_E0_CTL1)
6556 #define OFS_CECTL1_H (OFS_CECTL1+1)
6557 #define OFS_CECTL1_L (OFS_CECTL1)
6558 #define OFS_CECTL2 (OFS_COMP_E0_CTL2)
6559 #define OFS_CECTL2_H (OFS_CECTL2+1)
6560 #define OFS_CECTL2_L (OFS_CECTL2)
6561 #define OFS_CECTL3 (OFS_COMP_E0_CTL3)
6562 #define OFS_CECTL3_H (OFS_CECTL3+1)
6563 #define OFS_CECTL3_L (OFS_CECTL3)
6564 #define OFS_CEINT (OFS_COMP_E0_INT)
6565 #define OFS_CEINT_H (OFS_CEINT+1)
6566 #define OFS_CEINT_L (OFS_CEINT)
6567 #define OFS_CEIV (OFS_COMP_E0_IV)
6568 #define OFS_CEIV_H (OFS_CEIV+1)
6569 #define OFS_CEIV_L (OFS_CEIV)
6570 #define OFS_COMP_E0_CTL0 (0x00000000)
6571 #define OFS_COMP_E0_CTL1 (0x00000002)
6572 #define OFS_COMP_E0_CTL2 (0x00000004)
6573 #define OFS_COMP_E0_CTL3 (0x00000006)
6574 #define OFS_COMP_E0_INT (0x0000000C)
6575 #define OFS_COMP_E0_IV (0x0000000E)
6576 #define OFS_COMP_E1CTL0 (0x00000000)
6577 #define OFS_COMP_E1CTL1 (0x00000002)
6578 #define OFS_COMP_E1CTL2 (0x00000004)
6579 #define OFS_COMP_E1CTL3 (0x00000006)
6580 #define OFS_COMP_E1INT (0x0000000C)
6581 #define OFS_COMP_E1IV (0x0000000E)
6582 #define OFS_COMP_E1_CTL0 (0x00000000)
6583 #define OFS_COMP_E1_CTL1 (0x00000002)
6584 #define OFS_COMP_E1_CTL2 (0x00000004)
6585 #define OFS_COMP_E1_CTL3 (0x00000006)
6586 #define OFS_COMP_E1_INT (0x0000000C)
6587 #define OFS_COMP_E1_IV (0x0000000E)
6588 #define OFS_CRC16DI (0x00000010)
6589 #define OFS_CRC16DIRB (0x00000014)
6590 #define OFS_CRC16INIRES (0x00000018)
6591 #define OFS_CRC16RESR (0x0000001E)
6592 #define OFS_CRC32DI (0x00000000)
6593 #define OFS_CRC32DIRB (0x00000004)
6594 #define OFS_CRC32INIRES_HI (0x0000000A)
6595 #define OFS_CRC32INIRES_LO (0x00000008)
6596 #define OFS_CRC32RESR_HI (0x0000000E)
6597 #define OFS_CRC32RESR_LO (0x0000000C)
6598 #define OFS_CRCDI (0x0000)
6599 #define OFS_CRCDIRB (0x0002)
6600 #define OFS_CRCDIRB_H (OFS_CRCDIRB+1)
6601 #define OFS_CRCDIRB_L (OFS_CRCDIRB)
6602 #define OFS_CRCDI_H (OFS_CRCDI+1)
6603 #define OFS_CRCDI_L (OFS_CRCDI)
6604 #define OFS_CRCINIRES (0x0004)
6605 #define OFS_CRCINIRES_H (OFS_CRCINIRES+1)
6606 #define OFS_CRCINIRES_L (OFS_CRCINIRES)
6607 #define OFS_CRCRESR (0x0006)
6608 #define OFS_CRCRESR_H (OFS_CRCRESR+1)
6609 #define OFS_CRCRESR_L (OFS_CRCRESR)
6610 #define OFS_CS_ACC (0x00000000)
6611 #define OFS_CS_CLKEN (0x00000030)
6612 #define OFS_CS_CLRIFG (0x00000050)
6613 #define OFS_CS_CTL0 (0x00000004)
6614 #define OFS_CS_CTL1 (0x00000008)
6615 #define OFS_CS_CTL2 (0x0000000C)
6616 #define OFS_CS_CTL3 (0x00000010)
6617 #define OFS_CS_CTL4 (0x00000014)
6618 #define OFS_CS_CTL5 (0x00000018)
6619 #define OFS_CS_CTL6 (0x0000001C)
6620 #define OFS_CS_CTL7 (0x00000020)
6621 #define OFS_CS_DCOERCAL (0x00000060)
6622 #define OFS_CS_IE (0x00000040)
6623 #define OFS_CS_IFG (0x00000048)
6624 #define OFS_CS_SETIFG (0x00000058)
6625 #define OFS_CS_STAT (0x00000034)
6626 #define OFS_DDDS_ADC14_PARAM0 (0x00000038)
6627 #define OFS_DDDS_ADC14_REFTEMP0 (0x0000003C)
6628 #define OFS_DDDS_ADC14_REFTEMP1 (0x00000040)
6629 #define OFS_DDDS_ADC14_REFTEMP2 (0x00000044)
6630 #define OFS_DDDS_ADC14_REFTEMP3 (0x00000048)
6631 #define OFS_DDDS_BCREV (0x00000010)
6632 #define OFS_DDDS_CSDCOCONST (0x00000030)
6633 #define OFS_DDDS_CSDCOERCAL (0x0000002C)
6634 #define OFS_DDDS_CSDCOIRCAL (0x00000028)
6635 #define OFS_DDDS_DDDS_CHECKSUM (0x00000000)
6636 #define OFS_DDDS_DDDS_ENDWORD (0x0000006C)
6637 #define OFS_DDDS_DEVID (0x00000008)
6638 #define OFS_DDDS_DIE_POSITION (0x0000001C)
6639 #define OFS_DDDS_HWREV (0x0000000C)
6640 #define OFS_DDDS_LOT_ID (0x00000018)
6641 #define OFS_DDDS_MODID_ADC14 (0x00000034)
6642 #define OFS_DDDS_MODID_CS (0x00000024)
6643 #define OFS_DDDS_MODID_DEVINFO (0x00000004)
6644 #define OFS_DDDS_MODID_DIEREC (0x00000014)
6645 #define OFS_DDDS_MODID_RANDNUM (0x00000058)
6646 #define OFS_DDDS_MODID_REF (0x0000004C)
6647 #define OFS_DDDS_RAND0 (0x0000005C)
6648 #define OFS_DDDS_RAND1 (0x00000060)
6649 #define OFS_DDDS_RAND2 (0x00000064)
6650 #define OFS_DDDS_RAND3 (0x00000068)
6651 #define OFS_DDDS_REF_PARAM0 (0x00000050)
6652 #define OFS_DDDS_REF_PARAM1 (0x00000054)
6653 #define OFS_DDDS_TEST_RESULTS (0x00000020)
6654 #define OFS_DMA_CH0_SRCCFG (0x00000010)
6655 #define OFS_DMA_CH10_SRCCFG (0x00000038)
6656 #define OFS_DMA_CH11_SRCCFG (0x0000003C)
6657 #define OFS_DMA_CH12_SRCCFG (0x00000040)
6658 #define OFS_DMA_CH13_SRCCFG (0x00000044)
6659 #define OFS_DMA_CH14_SRCCFG (0x00000048)
6660 #define OFS_DMA_CH15_SRCCFG (0x0000004C)
6661 #define OFS_DMA_CH16_SRCCFG (0x00000050)
6662 #define OFS_DMA_CH17_SRCCFG (0x00000054)
6663 #define OFS_DMA_CH18_SRCCFG (0x00000058)
6664 #define OFS_DMA_CH19_SRCCFG (0x0000005C)
6665 #define OFS_DMA_CH1_SRCCFG (0x00000014)
6666 #define OFS_DMA_CH20_SRCCFG (0x00000060)
6667 #define OFS_DMA_CH21_SRCCFG (0x00000064)
6668 #define OFS_DMA_CH22_SRCCFG (0x00000068)
6669 #define OFS_DMA_CH23_SRCCFG (0x0000006C)
6670 #define OFS_DMA_CH24_SRCCFG (0x00000070)
6671 #define OFS_DMA_CH25_SRCCFG (0x00000074)
6672 #define OFS_DMA_CH26_SRCCFG (0x00000078)
6673 #define OFS_DMA_CH27_SRCCFG (0x0000007C)
6674 #define OFS_DMA_CH28_SRCCFG (0x00000080)
6675 #define OFS_DMA_CH29_SRCCFG (0x00000084)
6676 #define OFS_DMA_CH2_SRCCFG (0x00000018)
6677 #define OFS_DMA_CH30_SRCCFG (0x00000088)
6678 #define OFS_DMA_CH31_SRCCFG (0x0000008C)
6679 #define OFS_DMA_CH3_SRCCFG (0x0000001C)
6680 #define OFS_DMA_CH4_SRCCFG (0x00000020)
6681 #define OFS_DMA_CH5_SRCCFG (0x00000024)
6682 #define OFS_DMA_CH6_SRCCFG (0x00000028)
6683 #define OFS_DMA_CH7_SRCCFG (0x0000002C)
6684 #define OFS_DMA_CH8_SRCCFG (0x00000030)
6685 #define OFS_DMA_CH9_SRCCFG (0x00000034)
6686 #define OFS_DMA_DEVCONFIG (0x00000000)
6687 #define OFS_DMA_INT0_CLRFLG (0x00000114)
6688 #define OFS_DMA_INT0_SRCFLG (0x00000110)
6689 #define OFS_DMA_INT1_SRCCFG (0x00000100)
6690 #define OFS_DMA_INT2_SRCCFG (0x00000104)
6691 #define OFS_DMA_INT3_SRCCFG (0x00000108)
6692 #define OFS_DMA_SW_CHTRIG (0x00000004)
6693 #define OFS_DWT_CID0 (0x00000FF0)
6694 #define OFS_DWT_CID1 (0x00000FF4)
6695 #define OFS_DWT_CID2 (0x00000FF8)
6696 #define OFS_DWT_CID3 (0x00000FFC)
6697 #define OFS_DWT_COMP0 (0x00000020)
6698 #define OFS_DWT_COMP1 (0x00000030)
6699 #define OFS_DWT_COMP2 (0x00000040)
6700 #define OFS_DWT_COMP3 (0x00000050)
6701 #define OFS_DWT_CPICNT (0x00000008)
6702 #define OFS_DWT_CTRL (0x00000000)
6703 #define OFS_DWT_CYCCNT (0x00000004)
6704 #define OFS_DWT_EXCCNT (0x0000000C)
6705 #define OFS_DWT_FOLDCNT (0x00000018)
6706 #define OFS_DWT_FUNCTION0 (0x00000028)
6707 #define OFS_DWT_FUNCTION1 (0x00000038)
6708 #define OFS_DWT_FUNCTION2 (0x00000048)
6709 #define OFS_DWT_FUNCTION3 (0x00000058)
6710 #define OFS_DWT_LSUCNT (0x00000014)
6711 #define OFS_DWT_MASK0 (0x00000024)
6712 #define OFS_DWT_MASK1 (0x00000034)
6713 #define OFS_DWT_MASK2 (0x00000044)
6714 #define OFS_DWT_MASK3 (0x00000054)
6715 #define OFS_DWT_PCSR (0x0000001C)
6716 #define OFS_DWT_PID0 (0x00000FE0)
6717 #define OFS_DWT_PID1 (0x00000FE4)
6718 #define OFS_DWT_PID2 (0x00000FE8)
6719 #define OFS_DWT_PID3 (0x00000FEC)
6720 #define OFS_DWT_PID4 (0x00000FD0)
6721 #define OFS_DWT_PID5 (0x00000FD4)
6722 #define OFS_DWT_PID6 (0x00000FD8)
6723 #define OFS_DWT_PID7 (0x00000FDC)
6724 #define OFS_DWT_SLEEPCNT (0x00000010)
6725 #define OFS_EUSCI_A0_SPI_BRW (0x00000006)
6726 #define OFS_EUSCI_A0_SPI_CTLW0 (0x00000000)
6727 #define OFS_EUSCI_A0_SPI_IE (0x0000001A)
6728 #define OFS_EUSCI_A0_SPI_IFG (0x0000001C)
6729 #define OFS_EUSCI_A0_SPI_IV (0x0000001E)
6730 #define OFS_EUSCI_A0_SPI_RXBUF (0x0000000C)
6731 #define OFS_EUSCI_A0_SPI_STATW (0x0000000A)
6732 #define OFS_EUSCI_A0_SPI_TXBUF (0x0000000E)
6733 #define OFS_EUSCI_A0_UART_ABCTL (0x00000010)
6734 #define OFS_EUSCI_A0_UART_BRW (0x00000006)
6735 #define OFS_EUSCI_A0_UART_CTLW0 (0x00000000)
6736 #define OFS_EUSCI_A0_UART_CTLW1 (0x00000002)
6737 #define OFS_EUSCI_A0_UART_IE (0x0000001A)
6738 #define OFS_EUSCI_A0_UART_IFG (0x0000001C)
6739 #define OFS_EUSCI_A0_UART_IRCTL (0x00000012)
6740 #define OFS_EUSCI_A0_UART_IV (0x0000001E)
6741 #define OFS_EUSCI_A0_UART_MCTLW (0x00000008)
6742 #define OFS_EUSCI_A0_UART_RXBUF (0x0000000C)
6743 #define OFS_EUSCI_A0_UART_STATW (0x0000000A)
6744 #define OFS_EUSCI_A0_UART_TXBUF (0x0000000E)
6745 #define OFS_EUSCI_A1_SPI_BRW (0x00000006)
6746 #define OFS_EUSCI_A1_SPI_CTLW0 (0x00000000)
6747 #define OFS_EUSCI_A1_SPI_IE (0x0000001A)
6748 #define OFS_EUSCI_A1_SPI_IFG (0x0000001C)
6749 #define OFS_EUSCI_A1_SPI_IV (0x0000001E)
6750 #define OFS_EUSCI_A1_SPI_RXBUF (0x0000000C)
6751 #define OFS_EUSCI_A1_SPI_STATW (0x0000000A)
6752 #define OFS_EUSCI_A1_SPI_TXBUF (0x0000000E)
6753 #define OFS_EUSCI_A1_UART_ABCTL (0x00000010)
6754 #define OFS_EUSCI_A1_UART_BRW (0x00000006)
6755 #define OFS_EUSCI_A1_UART_CTLW0 (0x00000000)
6756 #define OFS_EUSCI_A1_UART_CTLW1 (0x00000002)
6757 #define OFS_EUSCI_A1_UART_IE (0x0000001A)
6758 #define OFS_EUSCI_A1_UART_IFG (0x0000001C)
6759 #define OFS_EUSCI_A1_UART_IRCTL (0x00000012)
6760 #define OFS_EUSCI_A1_UART_IV (0x0000001E)
6761 #define OFS_EUSCI_A1_UART_MCTLW (0x00000008)
6762 #define OFS_EUSCI_A1_UART_RXBUF (0x0000000C)
6763 #define OFS_EUSCI_A1_UART_STATW (0x0000000A)
6764 #define OFS_EUSCI_A1_UART_TXBUF (0x0000000E)
6765 #define OFS_EUSCI_A2_SPI_BRW (0x00000006)
6766 #define OFS_EUSCI_A2_SPI_CTLW0 (0x00000000)
6767 #define OFS_EUSCI_A2_SPI_IE (0x0000001A)
6768 #define OFS_EUSCI_A2_SPI_IFG (0x0000001C)
6769 #define OFS_EUSCI_A2_SPI_IV (0x0000001E)
6770 #define OFS_EUSCI_A2_SPI_RXBUF (0x0000000C)
6771 #define OFS_EUSCI_A2_SPI_STATW (0x0000000A)
6772 #define OFS_EUSCI_A2_SPI_TXBUF (0x0000000E)
6773 #define OFS_EUSCI_A2_UART_ABCTL (0x00000010)
6774 #define OFS_EUSCI_A2_UART_BRW (0x00000006)
6775 #define OFS_EUSCI_A2_UART_CTLW0 (0x00000000)
6776 #define OFS_EUSCI_A2_UART_CTLW1 (0x00000002)
6777 #define OFS_EUSCI_A2_UART_IE (0x0000001A)
6778 #define OFS_EUSCI_A2_UART_IFG (0x0000001C)
6779 #define OFS_EUSCI_A2_UART_IRCTL (0x00000012)
6780 #define OFS_EUSCI_A2_UART_IV (0x0000001E)
6781 #define OFS_EUSCI_A2_UART_MCTLW (0x00000008)
6782 #define OFS_EUSCI_A2_UART_RXBUF (0x0000000C)
6783 #define OFS_EUSCI_A2_UART_STATW (0x0000000A)
6784 #define OFS_EUSCI_A2_UART_TXBUF (0x0000000E)
6785 #define OFS_EUSCI_A3_SPI_BRW (0x00000006)
6786 #define OFS_EUSCI_A3_SPI_CTLW0 (0x00000000)
6787 #define OFS_EUSCI_A3_SPI_IE (0x0000001A)
6788 #define OFS_EUSCI_A3_SPI_IFG (0x0000001C)
6789 #define OFS_EUSCI_A3_SPI_IV (0x0000001E)
6790 #define OFS_EUSCI_A3_SPI_RXBUF (0x0000000C)
6791 #define OFS_EUSCI_A3_SPI_STATW (0x0000000A)
6792 #define OFS_EUSCI_A3_SPI_TXBUF (0x0000000E)
6793 #define OFS_EUSCI_A3_UART_ABCTL (0x00000010)
6794 #define OFS_EUSCI_A3_UART_BRW (0x00000006)
6795 #define OFS_EUSCI_A3_UART_CTLW0 (0x00000000)
6796 #define OFS_EUSCI_A3_UART_CTLW1 (0x00000002)
6797 #define OFS_EUSCI_A3_UART_IE (0x0000001A)
6798 #define OFS_EUSCI_A3_UART_IFG (0x0000001C)
6799 #define OFS_EUSCI_A3_UART_IRCTL (0x00000012)
6800 #define OFS_EUSCI_A3_UART_IV (0x0000001E)
6801 #define OFS_EUSCI_A3_UART_MCTLW (0x00000008)
6802 #define OFS_EUSCI_A3_UART_RXBUF (0x0000000C)
6803 #define OFS_EUSCI_A3_UART_STATW (0x0000000A)
6804 #define OFS_EUSCI_A3_UART_TXBUF (0x0000000E)
6805 #define OFS_EUSCI_B0_I2C_ADDMASK (0x0000001E)
6806 #define OFS_EUSCI_B0_I2C_ADDRX (0x0000001C)
6807 #define OFS_EUSCI_B0_I2C_BRW (0x00000006)
6808 #define OFS_EUSCI_B0_I2C_CTLW0 (0x00000000)
6809 #define OFS_EUSCI_B0_I2C_CTLW1 (0x00000002)
6810 #define OFS_EUSCI_B0_I2C_I2COA0 (0x00000014)
6811 #define OFS_EUSCI_B0_I2C_I2COA1 (0x00000016)
6812 #define OFS_EUSCI_B0_I2C_I2COA2 (0x00000018)
6813 #define OFS_EUSCI_B0_I2C_I2COA3 (0x0000001A)
6814 #define OFS_EUSCI_B0_I2C_I2CSA (0x00000020)
6815 #define OFS_EUSCI_B0_I2C_IE (0x0000002A)
6816 #define OFS_EUSCI_B0_I2C_IFG (0x0000002C)
6817 #define OFS_EUSCI_B0_I2C_IV (0x0000002E)
6818 #define OFS_EUSCI_B0_I2C_RXBUF (0x0000000C)
6819 #define OFS_EUSCI_B0_I2C_STATW (0x00000008)
6820 #define OFS_EUSCI_B0_I2C_TBCNT (0x0000000A)
6821 #define OFS_EUSCI_B0_I2C_TXBUF (0x0000000E)
6822 #define OFS_EUSCI_B0_SPI_BRW (0x00000006)
6823 #define OFS_EUSCI_B0_SPI_CTLW0 (0x00000000)
6824 #define OFS_EUSCI_B0_SPI_IE (0x0000002A)
6825 #define OFS_EUSCI_B0_SPI_IFG (0x0000002C)
6826 #define OFS_EUSCI_B0_SPI_IV (0x0000002E)
6827 #define OFS_EUSCI_B0_SPI_RXBUF (0x0000000C)
6828 #define OFS_EUSCI_B0_SPI_STATW (0x00000008)
6829 #define OFS_EUSCI_B0_SPI_TXBUF (0x0000000E)
6830 #define OFS_EUSCI_B1_I2C_ADDMASK (0x0000001E)
6831 #define OFS_EUSCI_B1_I2C_ADDRX (0x0000001C)
6832 #define OFS_EUSCI_B1_I2C_BRW (0x00000006)
6833 #define OFS_EUSCI_B1_I2C_CTLW0 (0x00000000)
6834 #define OFS_EUSCI_B1_I2C_CTLW1 (0x00000002)
6835 #define OFS_EUSCI_B1_I2C_I2COA0 (0x00000014)
6836 #define OFS_EUSCI_B1_I2C_I2COA1 (0x00000016)
6837 #define OFS_EUSCI_B1_I2C_I2COA2 (0x00000018)
6838 #define OFS_EUSCI_B1_I2C_I2COA3 (0x0000001A)
6839 #define OFS_EUSCI_B1_I2C_I2CSA (0x00000020)
6840 #define OFS_EUSCI_B1_I2C_IE (0x0000002A)
6841 #define OFS_EUSCI_B1_I2C_IFG (0x0000002C)
6842 #define OFS_EUSCI_B1_I2C_IV (0x0000002E)
6843 #define OFS_EUSCI_B1_I2C_RXBUF (0x0000000C)
6844 #define OFS_EUSCI_B1_I2C_STATW (0x00000008)
6845 #define OFS_EUSCI_B1_I2C_TBCNT (0x0000000A)
6846 #define OFS_EUSCI_B1_I2C_TXBUF (0x0000000E)
6847 #define OFS_EUSCI_B1_SPI_BRW (0x00000006)
6848 #define OFS_EUSCI_B1_SPI_CTLW0 (0x00000000)
6849 #define OFS_EUSCI_B1_SPI_IE (0x0000002A)
6850 #define OFS_EUSCI_B1_SPI_IFG (0x0000002C)
6851 #define OFS_EUSCI_B1_SPI_IV (0x0000002E)
6852 #define OFS_EUSCI_B1_SPI_RXBUF (0x0000000C)
6853 #define OFS_EUSCI_B1_SPI_STATW (0x00000008)
6854 #define OFS_EUSCI_B1_SPI_TXBUF (0x0000000E)
6855 #define OFS_EUSCI_B2_I2C_ADDMASK (0x0000001E)
6856 #define OFS_EUSCI_B2_I2C_ADDRX (0x0000001C)
6857 #define OFS_EUSCI_B2_I2C_BRW (0x00000006)
6858 #define OFS_EUSCI_B2_I2C_CTLW0 (0x00000000)
6859 #define OFS_EUSCI_B2_I2C_CTLW1 (0x00000002)
6860 #define OFS_EUSCI_B2_I2C_I2COA0 (0x00000014)
6861 #define OFS_EUSCI_B2_I2C_I2COA1 (0x00000016)
6862 #define OFS_EUSCI_B2_I2C_I2COA2 (0x00000018)
6863 #define OFS_EUSCI_B2_I2C_I2COA3 (0x0000001A)
6864 #define OFS_EUSCI_B2_I2C_I2CSA (0x00000020)
6865 #define OFS_EUSCI_B2_I2C_IE (0x0000002A)
6866 #define OFS_EUSCI_B2_I2C_IFG (0x0000002C)
6867 #define OFS_EUSCI_B2_I2C_IV (0x0000002E)
6868 #define OFS_EUSCI_B2_I2C_RXBUF (0x0000000C)
6869 #define OFS_EUSCI_B2_I2C_STATW (0x00000008)
6870 #define OFS_EUSCI_B2_I2C_TBCNT (0x0000000A)
6871 #define OFS_EUSCI_B2_I2C_TXBUF (0x0000000E)
6872 #define OFS_EUSCI_B2_SPI_BRW (0x00000006)
6873 #define OFS_EUSCI_B2_SPI_CTLW0 (0x00000000)
6874 #define OFS_EUSCI_B2_SPI_IE (0x0000002A)
6875 #define OFS_EUSCI_B2_SPI_IFG (0x0000002C)
6876 #define OFS_EUSCI_B2_SPI_IV (0x0000002E)
6877 #define OFS_EUSCI_B2_SPI_RXBUF (0x0000000C)
6878 #define OFS_EUSCI_B2_SPI_STATW (0x00000008)
6879 #define OFS_EUSCI_B2_SPI_TXBUF (0x0000000E)
6880 #define OFS_EUSCI_B3_I2C_ADDMASK (0x0000001E)
6881 #define OFS_EUSCI_B3_I2C_ADDRX (0x0000001C)
6882 #define OFS_EUSCI_B3_I2C_BRW (0x00000006)
6883 #define OFS_EUSCI_B3_I2C_CTLW0 (0x00000000)
6884 #define OFS_EUSCI_B3_I2C_CTLW1 (0x00000002)
6885 #define OFS_EUSCI_B3_I2C_I2COA0 (0x00000014)
6886 #define OFS_EUSCI_B3_I2C_I2COA1 (0x00000016)
6887 #define OFS_EUSCI_B3_I2C_I2COA2 (0x00000018)
6888 #define OFS_EUSCI_B3_I2C_I2COA3 (0x0000001A)
6889 #define OFS_EUSCI_B3_I2C_I2CSA (0x00000020)
6890 #define OFS_EUSCI_B3_I2C_IE (0x0000002A)
6891 #define OFS_EUSCI_B3_I2C_IFG (0x0000002C)
6892 #define OFS_EUSCI_B3_I2C_IV (0x0000002E)
6893 #define OFS_EUSCI_B3_I2C_RXBUF (0x0000000C)
6894 #define OFS_EUSCI_B3_I2C_STATW (0x00000008)
6895 #define OFS_EUSCI_B3_I2C_TBCNT (0x0000000A)
6896 #define OFS_EUSCI_B3_I2C_TXBUF (0x0000000E)
6897 #define OFS_EUSCI_B3_SPI_BRW (0x00000006)
6898 #define OFS_EUSCI_B3_SPI_CTLW0 (0x00000000)
6899 #define OFS_EUSCI_B3_SPI_IE (0x0000002A)
6900 #define OFS_EUSCI_B3_SPI_IFG (0x0000002C)
6901 #define OFS_EUSCI_B3_SPI_IV (0x0000002E)
6902 #define OFS_EUSCI_B3_SPI_RXBUF (0x0000000C)
6903 #define OFS_EUSCI_B3_SPI_STATW (0x00000008)
6904 #define OFS_EUSCI_B3_SPI_TXBUF (0x0000000E)
6905 #define OFS_FLCTL_BMRK_CMP (0x000000DC)
6906 #define OFS_FLCTL_BMRK_CTLSTAT (0x000000D0)
6907 #define OFS_FLCTL_BMRK_DREAD (0x000000D8)
6908 #define OFS_FLCTL_BMRK_IFETCH (0x000000D4)
6909 #define OFS_FLCTL_ERASE_CTLSTAT (0x000000A0)
6910 #define OFS_FLCTL_ERASE_SECTADDR (0x000000A4)
6911 #define OFS_FLCTL_ERASE_TIMCTL (0x00000118)
6912 #define OFS_FLCTL_ERSVER_TIMCTL (0x0000010C)
6913 #define OFS_FLCTL_INFOWEPROT_BNK0 (0x000000B0)
6914 #define OFS_FLCTL_INFOWEPROT_BNK1 (0x000000C0)
6915 #define OFS_FLCTL_INTCLR (0x000000F8)
6916 #define OFS_FLCTL_INTEN (0x000000F4)
6917 #define OFS_FLCTL_INTFLAG (0x000000F0)
6918 #define OFS_FLCTL_INTSET (0x000000FC)
6919 #define OFS_FLCTL_LKGVER_TIMCTL (0x00000110)
6920 #define OFS_FLCTL_MASSERASE_TIMCTL (0x0000011C)
6921 #define OFS_FLCTL_PRGBRST_CTLSTAT (0x00000054)
6922 #define OFS_FLCTL_PRGBRST_DATA0_0 (0x00000060)
6923 #define OFS_FLCTL_PRGBRST_DATA0_1 (0x00000064)
6924 #define OFS_FLCTL_PRGBRST_DATA0_2 (0x00000068)
6925 #define OFS_FLCTL_PRGBRST_DATA0_3 (0x0000006C)
6926 #define OFS_FLCTL_PRGBRST_DATA1_0 (0x00000070)
6927 #define OFS_FLCTL_PRGBRST_DATA1_1 (0x00000074)
6928 #define OFS_FLCTL_PRGBRST_DATA1_2 (0x00000078)
6929 #define OFS_FLCTL_PRGBRST_DATA1_3 (0x0000007C)
6930 #define OFS_FLCTL_PRGBRST_DATA2_0 (0x00000080)
6931 #define OFS_FLCTL_PRGBRST_DATA2_1 (0x00000084)
6932 #define OFS_FLCTL_PRGBRST_DATA2_2 (0x00000088)
6933 #define OFS_FLCTL_PRGBRST_DATA2_3 (0x0000008C)
6934 #define OFS_FLCTL_PRGBRST_DATA3_0 (0x00000090)
6935 #define OFS_FLCTL_PRGBRST_DATA3_1 (0x00000094)
6936 #define OFS_FLCTL_PRGBRST_DATA3_2 (0x00000098)
6937 #define OFS_FLCTL_PRGBRST_DATA3_3 (0x0000009C)
6938 #define OFS_FLCTL_PRGBRST_STARTADDR (0x00000058)
6939 #define OFS_FLCTL_PRGVER_TIMCTL (0x00000108)
6940 #define OFS_FLCTL_PRG_CTLSTAT (0x00000050)
6941 #define OFS_FLCTL_PROGRAM_TIMCTL (0x00000114)
6942 #define OFS_FLCTL_PWRSTAT (0x00000000)
6943 #define OFS_FLCTL_RDBRST_CTLSTAT (0x00000020)
6944 #define OFS_FLCTL_RDBRST_FAILADDR (0x0000003C)
6945 #define OFS_FLCTL_RDBRST_FAILCNT (0x00000040)
6946 #define OFS_FLCTL_RDBRST_LEN (0x00000028)
6947 #define OFS_FLCTL_RDBRST_STARTADDR (0x00000024)
6948 #define OFS_FLCTL_RDCTL_BNK0 (0x00000010)
6949 #define OFS_FLCTL_RDCTL_BNK1 (0x00000014)
6950 #define OFS_FLCTL_READMARGIN_TIMCTL (0x00000104)
6951 #define OFS_FLCTL_READ_TIMCTL (0x00000100)
6952 #define OFS_FLCTL_USRWEPROT_BNK0 (0x000000B4)
6953 #define OFS_FLCTL_USRWEPROT_BNK1 (0x000000C4)
6954 #define OFS_FPB_CID0 (0x00000FF0)
6955 #define OFS_FPB_CID1 (0x00000FF4)
6956 #define OFS_FPB_CID2 (0x00000FF8)
6957 #define OFS_FPB_CID3 (0x00000FFC)
6958 #define OFS_FPB_FP_COMP0 (0x00000008)
6959 #define OFS_FPB_FP_COMP1 (0x0000000C)
6960 #define OFS_FPB_FP_COMP2 (0x00000010)
6961 #define OFS_FPB_FP_COMP3 (0x00000014)
6962 #define OFS_FPB_FP_COMP4 (0x00000018)
6963 #define OFS_FPB_FP_COMP5 (0x0000001C)
6964 #define OFS_FPB_FP_COMP6 (0x00000020)
6965 #define OFS_FPB_FP_COMP7 (0x00000024)
6966 #define OFS_FPB_FP_CTRL (0x00000000)
6967 #define OFS_FPB_FP_REMAP (0x00000004)
6968 #define OFS_FPB_PID0 (0x00000FE0)
6969 #define OFS_FPB_PID1 (0x00000FE4)
6970 #define OFS_FPB_PID2 (0x00000FE8)
6971 #define OFS_FPB_PID3 (0x00000FEC)
6972 #define OFS_FPB_PID4 (0x00000FD0)
6973 #define OFS_FPB_PID5 (0x00000FD4)
6974 #define OFS_FPB_PID6 (0x00000FD8)
6975 #define OFS_FPB_PID7 (0x00000FDC)
6976 #define OFS_FPU_CPACR (0x00000D88)
6977 #define OFS_FPU_FPCAR (0x00000F38)
6978 #define OFS_FPU_FPCCR (0x00000F34)
6979 #define OFS_FPU_FPDSCR (0x00000F3C)
6980 #define OFS_FPU_MVFR0 (0x00000F40)
6981 #define OFS_FPU_MVFR1 (0x00000F44)
6982 #define OFS_ITM_CID0 (0x00000FF0)
6983 #define OFS_ITM_CID1 (0x00000FF4)
6984 #define OFS_ITM_CID2 (0x00000FF8)
6985 #define OFS_ITM_CID3 (0x00000FFC)
6986 #define OFS_ITM_ITM_IMCR (0x00000F00)
6987 #define OFS_ITM_ITM_IWR (0x00000EF8)
6988 #define OFS_ITM_ITM_LAR (0x00000FB0)
6989 #define OFS_ITM_ITM_LSR (0x00000FB4)
6990 #define OFS_ITM_ITM_STIM0 (0x00000000)
6991 #define OFS_ITM_ITM_STIM1 (0x00000004)
6992 #define OFS_ITM_ITM_STIM10 (0x00000028)
6993 #define OFS_ITM_ITM_STIM11 (0x0000002C)
6994 #define OFS_ITM_ITM_STIM12 (0x00000030)
6995 #define OFS_ITM_ITM_STIM13 (0x00000034)
6996 #define OFS_ITM_ITM_STIM14 (0x00000038)
6997 #define OFS_ITM_ITM_STIM15 (0x0000003C)
6998 #define OFS_ITM_ITM_STIM16 (0x00000040)
6999 #define OFS_ITM_ITM_STIM17 (0x00000044)
7000 #define OFS_ITM_ITM_STIM18 (0x00000048)
7001 #define OFS_ITM_ITM_STIM19 (0x0000004C)
7002 #define OFS_ITM_ITM_STIM2 (0x00000008)
7003 #define OFS_ITM_ITM_STIM20 (0x00000050)
7004 #define OFS_ITM_ITM_STIM21 (0x00000054)
7005 #define OFS_ITM_ITM_STIM22 (0x00000058)
7006 #define OFS_ITM_ITM_STIM23 (0x0000005C)
7007 #define OFS_ITM_ITM_STIM24 (0x00000060)
7008 #define OFS_ITM_ITM_STIM25 (0x00000064)
7009 #define OFS_ITM_ITM_STIM26 (0x00000068)
7010 #define OFS_ITM_ITM_STIM27 (0x0000006C)
7011 #define OFS_ITM_ITM_STIM28 (0x00000070)
7012 #define OFS_ITM_ITM_STIM29 (0x00000074)
7013 #define OFS_ITM_ITM_STIM3 (0x0000000C)
7014 #define OFS_ITM_ITM_STIM30 (0x00000078)
7015 #define OFS_ITM_ITM_STIM31 (0x0000007C)
7016 #define OFS_ITM_ITM_STIM4 (0x00000010)
7017 #define OFS_ITM_ITM_STIM5 (0x00000014)
7018 #define OFS_ITM_ITM_STIM6 (0x00000018)
7019 #define OFS_ITM_ITM_STIM7 (0x0000001C)
7020 #define OFS_ITM_ITM_STIM8 (0x00000020)
7021 #define OFS_ITM_ITM_STIM9 (0x00000024)
7022 #define OFS_ITM_ITM_TCR (0x00000E80)
7023 #define OFS_ITM_ITM_TER (0x00000E00)
7024 #define OFS_ITM_ITM_TPR (0x00000E40)
7025 #define OFS_ITM_PID0 (0x00000FE0)
7026 #define OFS_ITM_PID1 (0x00000FE4)
7027 #define OFS_ITM_PID2 (0x00000FE8)
7028 #define OFS_ITM_PID3 (0x00000FEC)
7029 #define OFS_ITM_PID4 (0x00000FD0)
7030 #define OFS_ITM_PID5 (0x00000FD4)
7031 #define OFS_ITM_PID6 (0x00000FD8)
7032 #define OFS_ITM_PID7 (0x00000FDC)
7033 #define OFS_MPU_CTRL (0x00000D94)
7034 #define OFS_MPU_RASR (0x00000DA0)
7035 #define OFS_MPU_RASR_A1 (0x00000DA8)
7036 #define OFS_MPU_RASR_A2 (0x00000DB0)
7037 #define OFS_MPU_RASR_A3 (0x00000DB8)
7038 #define OFS_MPU_RBAR (0x00000D9C)
7039 #define OFS_MPU_RBAR_A1 (0x00000DA4)
7040 #define OFS_MPU_RBAR_A2 (0x00000DAC)
7041 #define OFS_MPU_RBAR_A3 (0x00000DB4)
7042 #define OFS_MPU_RNR (0x00000D98)
7043 #define OFS_MPU_TYPE (0x00000D90)
7044 #define OFS_P10DIR (OFS_P10_DIR)
7045 #define OFS_P10IE (OFS_P10_IE)
7046 #define OFS_P10IES (OFS_P10_IES)
7047 #define OFS_P10IFG (OFS_P10_IFG)
7048 #define OFS_P10IN (OFS_P10_IN)
7049 #define OFS_P10IV (OFS_P10_IV)
7050 #define OFS_P10OUT (OFS_P10_OUT)
7051 #define OFS_P10REN (OFS_P10_REN)
7052 #define OFS_P10SEL0 (OFS_P10_SEL0)
7053 #define OFS_P10SEL1 (OFS_P10_SEL1)
7054 #define OFS_P10_DIR (0x00000004)
7055 #define OFS_P10_DS (0x00000008)
7056 #define OFS_P10_IE (0x0000001A)
7057 #define OFS_P10_IES (0x00000018)
7058 #define OFS_P10_IFG (0x0000001C)
7059 #define OFS_P10_IN (0x00000000)
7060 #define OFS_P10_IV (0x0000001D)
7061 #define OFS_P10_OUT (0x00000002)
7062 #define OFS_P10_REN (0x00000006)
7063 #define OFS_P10_SEL0 (0x0000000A)
7064 #define OFS_P10_SEL1 (0x0000000C)
7065 #define OFS_P10_SELC (0x00000016)
7066 #define OFS_P1DIR (OFS_P1_DIR)
7067 #define OFS_P1IE (OFS_P1_IE)
7068 #define OFS_P1IES (OFS_P1_IES)
7069 #define OFS_P1IFG (OFS_P1_IFG)
7070 #define OFS_P1IN (OFS_P1_IN)
7071 #define OFS_P1IV (OFS_P1_IV)
7072 #define OFS_P1OUT (OFS_P1_OUT)
7073 #define OFS_P1REN (OFS_P1_REN)
7074 #define OFS_P1SEL0 (OFS_P1_SEL0)
7075 #define OFS_P1SEL1 (OFS_P1_SEL1)
7076 #define OFS_P1_DIR (0x00000004)
7077 #define OFS_P1_DS (0x00000008)
7078 #define OFS_P1_IE (0x0000001A)
7079 #define OFS_P1_IES (0x00000018)
7080 #define OFS_P1_IFG (0x0000001C)
7081 #define OFS_P1_IN (0x00000000)
7082 #define OFS_P1_IV (0x0000000E)
7083 #define OFS_P1_OUT (0x00000002)
7084 #define OFS_P1_REN (0x00000006)
7085 #define OFS_P1_SEL0 (0x0000000A)
7086 #define OFS_P1_SEL1 (0x0000000C)
7087 #define OFS_P1_SELC (0x00000016)
7088 #define OFS_P2DIR (OFS_P2_DIR)
7089 #define OFS_P2IE (OFS_P2_IE)
7090 #define OFS_P2IES (OFS_P2_IES)
7091 #define OFS_P2IFG (OFS_P2_IFG)
7092 #define OFS_P2IN (OFS_P2_IN)
7093 #define OFS_P2IV (OFS_P2_IV)
7094 #define OFS_P2OUT (OFS_P2_OUT)
7095 #define OFS_P2REN (OFS_P2_REN)
7096 #define OFS_P2SEL0 (OFS_P2_SEL0)
7097 #define OFS_P2SEL1 (OFS_P2_SEL1)
7098 #define OFS_P2_DIR (0x00000004)
7099 #define OFS_P2_DS (0x00000008)
7100 #define OFS_P2_IE (0x0000001A)
7101 #define OFS_P2_IES (0x00000018)
7102 #define OFS_P2_IFG (0x0000001C)
7103 #define OFS_P2_IN (0x00000000)
7104 #define OFS_P2_IV (0x0000001D)
7105 #define OFS_P2_OUT (0x00000002)
7106 #define OFS_P2_REN (0x00000006)
7107 #define OFS_P2_SEL0 (0x0000000A)
7108 #define OFS_P2_SEL1 (0x0000000C)
7109 #define OFS_P2_SELC (0x00000016)
7110 #define OFS_P3DIR (OFS_P3_DIR)
7111 #define OFS_P3IE (OFS_P3_IE)
7112 #define OFS_P3IES (OFS_P3_IES)
7113 #define OFS_P3IFG (OFS_P3_IFG)
7114 #define OFS_P3IN (OFS_P3_IN)
7115 #define OFS_P3IV (OFS_P3_IV)
7116 #define OFS_P3OUT (OFS_P3_OUT)
7117 #define OFS_P3REN (OFS_P3_REN)
7118 #define OFS_P3SEL0 (OFS_P3_SEL0)
7119 #define OFS_P3SEL1 (OFS_P3_SEL1)
7120 #define OFS_P3_DIR (0x00000004)
7121 #define OFS_P3_DS (0x00000008)
7122 #define OFS_P3_IE (0x0000001A)
7123 #define OFS_P3_IES (0x00000018)
7124 #define OFS_P3_IFG (0x0000001C)
7125 #define OFS_P3_IN (0x00000000)
7126 #define OFS_P3_IV (0x0000000E)
7127 #define OFS_P3_OUT (0x00000002)
7128 #define OFS_P3_REN (0x00000006)
7129 #define OFS_P3_SEL0 (0x0000000A)
7130 #define OFS_P3_SEL1 (0x0000000C)
7131 #define OFS_P3_SELC (0x00000016)
7132 #define OFS_P4DIR (OFS_P4_DIR)
7133 #define OFS_P4IE (OFS_P4_IE)
7134 #define OFS_P4IES (OFS_P4_IES)
7135 #define OFS_P4IFG (OFS_P4_IFG)
7136 #define OFS_P4IN (OFS_P4_IN)
7137 #define OFS_P4IV (OFS_P4_IV)
7138 #define OFS_P4OUT (OFS_P4_OUT)
7139 #define OFS_P4REN (OFS_P4_REN)
7140 #define OFS_P4SEL0 (OFS_P4_SEL0)
7141 #define OFS_P4SEL1 (OFS_P4_SEL1)
7142 #define OFS_P4_DIR (0x00000004)
7143 #define OFS_P4_DS (0x00000008)
7144 #define OFS_P4_IE (0x0000001A)
7145 #define OFS_P4_IES (0x00000018)
7146 #define OFS_P4_IFG (0x0000001C)
7147 #define OFS_P4_IN (0x00000000)
7148 #define OFS_P4_IV (0x0000001D)
7149 #define OFS_P4_OUT (0x00000002)
7150 #define OFS_P4_REN (0x00000006)
7151 #define OFS_P4_SEL0 (0x0000000A)
7152 #define OFS_P4_SEL1 (0x0000000C)
7153 #define OFS_P4_SELC (0x00000016)
7154 #define OFS_P5DIR (OFS_P5_DIR)
7155 #define OFS_P5IE (OFS_P5_IE)
7156 #define OFS_P5IES (OFS_P5_IES)
7157 #define OFS_P5IFG (OFS_P5_IFG)
7158 #define OFS_P5IN (OFS_P5_IN)
7159 #define OFS_P5IV (OFS_P5_IV)
7160 #define OFS_P5OUT (OFS_P5_OUT)
7161 #define OFS_P5REN (OFS_P5_REN)
7162 #define OFS_P5SEL0 (OFS_P5_SEL0)
7163 #define OFS_P5SEL1 (OFS_P5_SEL1)
7164 #define OFS_P5_DIR (0x00000004)
7165 #define OFS_P5_DS (0x00000008)
7166 #define OFS_P5_IE (0x0000001A)
7167 #define OFS_P5_IES (0x00000018)
7168 #define OFS_P5_IFG (0x0000001C)
7169 #define OFS_P5_IN (0x00000000)
7170 #define OFS_P5_IV (0x0000000E)
7171 #define OFS_P5_OUT (0x00000002)
7172 #define OFS_P5_REN (0x00000006)
7173 #define OFS_P5_SEL0 (0x0000000A)
7174 #define OFS_P5_SEL1 (0x0000000C)
7175 #define OFS_P5_SELC (0x00000016)
7176 #define OFS_P6DIR (OFS_P6_DIR)
7177 #define OFS_P6IE (OFS_P6_IE)
7178 #define OFS_P6IES (OFS_P6_IES)
7179 #define OFS_P6IFG (OFS_P6_IFG)
7180 #define OFS_P6IN (OFS_P6_IN)
7181 #define OFS_P6IV (OFS_P6_IV)
7182 #define OFS_P6OUT (OFS_P6_OUT)
7183 #define OFS_P6REN (OFS_P6_REN)
7184 #define OFS_P6SEL0 (OFS_P6_SEL0)
7185 #define OFS_P6SEL1 (OFS_P6_SEL1)
7186 #define OFS_P6_DIR (0x00000004)
7187 #define OFS_P6_DS (0x00000008)
7188 #define OFS_P6_IE (0x0000001A)
7189 #define OFS_P6_IES (0x00000018)
7190 #define OFS_P6_IFG (0x0000001C)
7191 #define OFS_P6_IN (0x00000000)
7192 #define OFS_P6_IV (0x0000001D)
7193 #define OFS_P6_OUT (0x00000002)
7194 #define OFS_P6_REN (0x00000006)
7195 #define OFS_P6_SEL0 (0x0000000A)
7196 #define OFS_P6_SEL1 (0x0000000C)
7197 #define OFS_P6_SELC (0x00000016)
7198 #define OFS_P7DIR (OFS_P7_DIR)
7199 #define OFS_P7IE (OFS_P7_IE)
7200 #define OFS_P7IES (OFS_P7_IES)
7201 #define OFS_P7IFG (OFS_P7_IFG)
7202 #define OFS_P7IN (OFS_P7_IN)
7203 #define OFS_P7IV (OFS_P7_IV)
7204 #define OFS_P7OUT (OFS_P7_OUT)
7205 #define OFS_P7REN (OFS_P7_REN)
7206 #define OFS_P7SEL0 (OFS_P7_SEL0)
7207 #define OFS_P7SEL1 (OFS_P7_SEL1)
7208 #define OFS_P7_DIR (0x00000004)
7209 #define OFS_P7_DS (0x00000008)
7210 #define OFS_P7_IE (0x0000001A)
7211 #define OFS_P7_IES (0x00000018)
7212 #define OFS_P7_IFG (0x0000001C)
7213 #define OFS_P7_IN (0x00000000)
7214 #define OFS_P7_IV (0x0000000E)
7215 #define OFS_P7_OUT (0x00000002)
7216 #define OFS_P7_REN (0x00000006)
7217 #define OFS_P7_SEL0 (0x0000000A)
7218 #define OFS_P7_SEL1 (0x0000000C)
7219 #define OFS_P7_SELC (0x00000016)
7220 #define OFS_P8DIR (OFS_P8_DIR)
7221 #define OFS_P8IE (OFS_P8_IE)
7222 #define OFS_P8IES (OFS_P8_IES)
7223 #define OFS_P8IFG (OFS_P8_IFG)
7224 #define OFS_P8IN (OFS_P8_IN)
7225 #define OFS_P8IV (OFS_P8_IV)
7226 #define OFS_P8OUT (OFS_P8_OUT)
7227 #define OFS_P8REN (OFS_P8_REN)
7228 #define OFS_P8SEL0 (OFS_P8_SEL0)
7229 #define OFS_P8SEL1 (OFS_P8_SEL1)
7230 #define OFS_P8_DIR (0x00000004)
7231 #define OFS_P8_DS (0x00000008)
7232 #define OFS_P8_IE (0x0000001A)
7233 #define OFS_P8_IES (0x00000018)
7234 #define OFS_P8_IFG (0x0000001C)
7235 #define OFS_P8_IN (0x00000000)
7236 #define OFS_P8_IV (0x0000001D)
7237 #define OFS_P8_OUT (0x00000002)
7238 #define OFS_P8_REN (0x00000006)
7239 #define OFS_P8_SEL0 (0x0000000A)
7240 #define OFS_P8_SEL1 (0x0000000C)
7241 #define OFS_P8_SELC (0x00000016)
7242 #define OFS_P9DIR (OFS_P9_DIR)
7243 #define OFS_P9IE (OFS_P9_IE)
7244 #define OFS_P9IES (OFS_P9_IES)
7245 #define OFS_P9IFG (OFS_P9_IFG)
7246 #define OFS_P9IN (OFS_P9_IN)
7247 #define OFS_P9IV (OFS_P9_IV)
7248 #define OFS_P9OUT (OFS_P9_OUT)
7249 #define OFS_P9REN (OFS_P9_REN)
7250 #define OFS_P9SEL0 (OFS_P9_SEL0)
7251 #define OFS_P9SEL1 (OFS_P9_SEL1)
7252 #define OFS_P9_DIR (0x00000004)
7253 #define OFS_P9_DS (0x00000008)
7254 #define OFS_P9_IE (0x0000001A)
7255 #define OFS_P9_IES (0x00000018)
7256 #define OFS_P9_IFG (0x0000001C)
7257 #define OFS_P9_IN (0x00000000)
7258 #define OFS_P9_IV (0x0000000E)
7259 #define OFS_P9_OUT (0x00000002)
7260 #define OFS_P9_REN (0x00000006)
7261 #define OFS_P9_SEL0 (0x0000000A)
7262 #define OFS_P9_SEL1 (0x0000000C)
7263 #define OFS_P9_SELC (0x00000016)
7264 #define OFS_PADIR (OFS_PA_DIR)
7265 #define OFS_PADIR_H (OFS_PADIR+1)
7266 #define OFS_PADIR_L (OFS_PADIR)
7267 #define OFS_PAIE (OFS_PA_IE)
7268 #define OFS_PAIES (OFS_PA_IES)
7269 #define OFS_PAIES_H (OFS_PAIES+1)
7270 #define OFS_PAIES_L (OFS_PAIES)
7271 #define OFS_PAIE_H (OFS_PAIE+1)
7272 #define OFS_PAIE_L (OFS_PAIE)
7273 #define OFS_PAIFG (OFS_PA_IFG)
7274 #define OFS_PAIFG_H (OFS_PAIFG+1)
7275 #define OFS_PAIFG_L (OFS_PAIFG)
7276 #define OFS_PAIN (OFS_PA_IN)
7277 #define OFS_PAIN_H (OFS_PAIN+1)
7278 #define OFS_PAIN_L (OFS_PAIN)
7279 #define OFS_PAOUT (OFS_PA_OUT)
7280 #define OFS_PAOUT_H (OFS_PAOUT+1)
7281 #define OFS_PAOUT_L (OFS_PAOUT)
7282 #define OFS_PAREN (OFS_PA_REN)
7283 #define OFS_PAREN_H (OFS_PAREN+1)
7284 #define OFS_PAREN_L (OFS_PAREN)
7285 #define OFS_PASEL0 (OFS_PA_SEL0)
7286 #define OFS_PASEL0_H (OFS_PASEL0+1)
7287 #define OFS_PASEL0_L (OFS_PASEL0)
7288 #define OFS_PASEL1 (OFS_PA_SEL1)
7289 #define OFS_PASEL1_H (OFS_PASEL1+1)
7290 #define OFS_PASEL1_L (OFS_PASEL1)
7291 #define OFS_PA_DIR (0x00000004)
7292 #define OFS_PA_DS (0x00000008)
7293 #define OFS_PA_IE (0x0000001A)
7294 #define OFS_PA_IES (0x00000018)
7295 #define OFS_PA_IFG (0x0000001C)
7296 #define OFS_PA_IN (0x00000000)
7297 #define OFS_PA_OUT (0x00000002)
7298 #define OFS_PA_REN (0x00000006)
7299 #define OFS_PA_SEL0 (0x0000000A)
7300 #define OFS_PA_SEL1 (0x0000000C)
7301 #define OFS_PA_SELC (0x00000016)
7302 #define OFS_PBDIR (OFS_PB_DIR)
7303 #define OFS_PBDIR_H (OFS_PBDIR+1)
7304 #define OFS_PBDIR_L (OFS_PBDIR)
7305 #define OFS_PBIE (OFS_PB_IE)
7306 #define OFS_PBIES (OFS_PB_IES)
7307 #define OFS_PBIES_H (OFS_PBIES+1)
7308 #define OFS_PBIES_L (OFS_PBIES)
7309 #define OFS_PBIE_H (OFS_PBIE+1)
7310 #define OFS_PBIE_L (OFS_PBIE)
7311 #define OFS_PBIFG (OFS_PB_IFG)
7312 #define OFS_PBIFG_H (OFS_PBIFG+1)
7313 #define OFS_PBIFG_L (OFS_PBIFG)
7314 #define OFS_PBIN (OFS_PB_IN)
7315 #define OFS_PBIN_H (OFS_PBIN+1)
7316 #define OFS_PBIN_L (OFS_PBIN)
7317 #define OFS_PBOUT (OFS_PB_OUT)
7318 #define OFS_PBOUT_H (OFS_PBOUT+1)
7319 #define OFS_PBOUT_L (OFS_PBOUT)
7320 #define OFS_PBREN (OFS_PB_REN)
7321 #define OFS_PBREN_H (OFS_PBREN+1)
7322 #define OFS_PBREN_L (OFS_PBREN)
7323 #define OFS_PBSEL0 (OFS_PB_SEL0)
7324 #define OFS_PBSEL0_H (OFS_PBSEL0+1)
7325 #define OFS_PBSEL0_L (OFS_PBSEL0)
7326 #define OFS_PBSEL1 (OFS_PB_SEL1)
7327 #define OFS_PBSEL1_H (OFS_PBSEL1+1)
7328 #define OFS_PBSEL1_L (OFS_PBSEL1)
7329 #define OFS_PB_DIR (0x00000004)
7330 #define OFS_PB_DS (0x00000008)
7331 #define OFS_PB_IE (0x0000001A)
7332 #define OFS_PB_IES (0x00000018)
7333 #define OFS_PB_IFG (0x0000001C)
7334 #define OFS_PB_IN (0x00000000)
7335 #define OFS_PB_OUT (0x00000002)
7336 #define OFS_PB_REN (0x00000006)
7337 #define OFS_PB_SEL0 (0x0000000A)
7338 #define OFS_PB_SEL1 (0x0000000C)
7339 #define OFS_PB_SELC (0x00000016)
7340 #define OFS_PCDIR (OFS_PC_DIR)
7341 #define OFS_PCDIR_H (OFS_PCDIR+1)
7342 #define OFS_PCDIR_L (OFS_PCDIR)
7343 #define OFS_PCIE (OFS_PC_IE)
7344 #define OFS_PCIES (OFS_PC_IES)
7345 #define OFS_PCIES_H (OFS_PCIES+1)
7346 #define OFS_PCIES_L (OFS_PCIES)
7347 #define OFS_PCIE_H (OFS_PCIE+1)
7348 #define OFS_PCIE_L (OFS_PCIE)
7349 #define OFS_PCIFG (OFS_PC_IFG)
7350 #define OFS_PCIFG_H (OFS_PCIFG+1)
7351 #define OFS_PCIFG_L (OFS_PCIFG)
7352 #define OFS_PCIN (OFS_PC_IN)
7353 #define OFS_PCIN_H (OFS_PCIN+1)
7354 #define OFS_PCIN_L (OFS_PCIN)
7355 #define OFS_PCM_CTL (0x00000004)
7356 #define OFS_PCM_INTCLR (0x00000010)
7357 #define OFS_PCM_INTEN (0x00000008)
7358 #define OFS_PCM_INTFLAG (0x0000000C)
7359 #define OFS_PCM_PMR (0x00000000)
7360 #define OFS_PCOUT (OFS_PC_OUT)
7361 #define OFS_PCOUT_H (OFS_PCOUT+1)
7362 #define OFS_PCOUT_L (OFS_PCOUT)
7363 #define OFS_PCREN (OFS_PC_REN)
7364 #define OFS_PCREN_H (OFS_PCREN+1)
7365 #define OFS_PCREN_L (OFS_PCREN)
7366 #define OFS_PCSEL0 (OFS_PC_SEL0)
7367 #define OFS_PCSEL0_H (OFS_PCSEL0+1)
7368 #define OFS_PCSEL0_L (OFS_PCSEL0)
7369 #define OFS_PCSEL1 (OFS_PC_SEL1)
7370 #define OFS_PCSEL1_H (OFS_PCSEL1+1)
7371 #define OFS_PCSEL1_L (OFS_PCSEL1)
7372 #define OFS_PC_DIR (0x00000004)
7373 #define OFS_PC_DS (0x00000008)
7374 #define OFS_PC_IE (0x0000001A)
7375 #define OFS_PC_IES (0x00000018)
7376 #define OFS_PC_IFG (0x0000001C)
7377 #define OFS_PC_IN (0x00000000)
7378 #define OFS_PC_OUT (0x00000002)
7379 #define OFS_PC_REN (0x00000006)
7380 #define OFS_PC_SEL0 (0x0000000A)
7381 #define OFS_PC_SEL1 (0x0000000C)
7382 #define OFS_PC_SELC (0x00000016)
7383 #define OFS_PDDIR (OFS_PD_DIR)
7384 #define OFS_PDDIR_H (OFS_PDDIR+1)
7385 #define OFS_PDDIR_L (OFS_PDDIR)
7386 #define OFS_PDIN (OFS_PD_IN)
7387 #define OFS_PDIN_H (OFS_PDIN+1)
7388 #define OFS_PDIN_L (OFS_PDIN)
7389 #define OFS_PDOUT (OFS_PD_OUT)
7390 #define OFS_PDOUT_H (OFS_PDOUT+1)
7391 #define OFS_PDOUT_L (OFS_PDOUT)
7392 #define OFS_PDREN (OFS_PD_REN)
7393 #define OFS_PDREN_H (OFS_PDREN+1)
7394 #define OFS_PDREN_L (OFS_PDREN)
7395 #define OFS_PDSEL0 (OFS_PD_SEL0)
7396 #define OFS_PDSEL0_H (OFS_PDSEL0+1)
7397 #define OFS_PDSEL0_L (OFS_PDSEL0)
7398 #define OFS_PDSEL1 (OFS_PD_SEL1)
7399 #define OFS_PDSEL1_H (OFS_PDSEL1+1)
7400 #define OFS_PDSEL1_L (OFS_PDSEL1)
7401 #define OFS_PD_DIR (0x00000004)
7402 #define OFS_PD_DS (0x00000008)
7403 #define OFS_PD_IE (0x0000001A)
7404 #define OFS_PD_IES (0x00000018)
7405 #define OFS_PD_IFG (0x0000001C)
7406 #define OFS_PD_IN (0x00000000)
7407 #define OFS_PD_OUT (0x00000002)
7408 #define OFS_PD_REN (0x00000006)
7409 #define OFS_PD_SEL0 (0x0000000A)
7410 #define OFS_PD_SEL1 (0x0000000C)
7411 #define OFS_PD_SELC (0x00000016)
7412 #define OFS_PEDIR (OFS_PE_DIR)
7413 #define OFS_PEDIR_H (OFS_PEDIR+1)
7414 #define OFS_PEDIR_L (OFS_PEDIR)
7415 #define OFS_PEIN (OFS_PE_IN)
7416 #define OFS_PEIN_H (OFS_PEIN+1)
7417 #define OFS_PEIN_L (OFS_PEIN)
7418 #define OFS_PEOUT (OFS_PE_OUT)
7419 #define OFS_PEOUT_H (OFS_PEOUT+1)
7420 #define OFS_PEOUT_L (OFS_PEOUT)
7421 #define OFS_PEREN (OFS_PE_REN)
7422 #define OFS_PEREN_H (OFS_PEREN+1)
7423 #define OFS_PEREN_L (OFS_PEREN)
7424 #define OFS_PESEL0 (OFS_PE_SEL0)
7425 #define OFS_PESEL0_H (OFS_PESEL0+1)
7426 #define OFS_PESEL0_L (OFS_PESEL0)
7427 #define OFS_PESEL1 (OFS_PE_SEL1)
7428 #define OFS_PESEL1_H (OFS_PESEL1+1)
7429 #define OFS_PESEL1_L (OFS_PESEL1)
7430 #define OFS_PE_DIR (0x00000004)
7431 #define OFS_PE_DS (0x00000008)
7432 #define OFS_PE_IE (0x0000001A)
7433 #define OFS_PE_IES (0x00000018)
7434 #define OFS_PE_IFG (0x0000001C)
7435 #define OFS_PE_IN (0x00000000)
7436 #define OFS_PE_OUT (0x00000002)
7437 #define OFS_PE_REN (0x00000006)
7438 #define OFS_PE_SEL0 (0x0000000A)
7439 #define OFS_PE_SEL1 (0x0000000C)
7440 #define OFS_PE_SELC (0x00000016)
7441 #define OFS_PJDIR (OFS_PJ_DIR)
7442 #define OFS_PJDIR_H (OFS_PJDIR+1)
7443 #define OFS_PJDIR_L (OFS_PJDIR)
7444 #define OFS_PJIN (OFS_PJ_IN)
7445 #define OFS_PJIN_H (OFS_PJIN+1)
7446 #define OFS_PJIN_L (OFS_PJIN)
7447 #define OFS_PJOUT (OFS_PJ_OUT)
7448 #define OFS_PJOUT_H (OFS_PJOUT+1)
7449 #define OFS_PJOUT_L (OFS_PJOUT)
7450 #define OFS_PJREN (OFS_PJ_REN)
7451 #define OFS_PJREN_H (OFS_PJREN+1)
7452 #define OFS_PJREN_L (OFS_PJREN)
7453 #define OFS_PJSEL0 (OFS_PJ_SEL0)
7454 #define OFS_PJSEL0_H (OFS_PJSEL0+1)
7455 #define OFS_PJSEL0_L (OFS_PJSEL0)
7456 #define OFS_PJSEL1 (OFS_PJ_SEL1)
7457 #define OFS_PJSEL1_H (OFS_PJSEL1+1)
7458 #define OFS_PJSEL1_L (OFS_PJSEL1)
7459 #define OFS_PJ_DIR (0x00000004)
7460 #define OFS_PJ_DS (0x00000008)
7461 #define OFS_PJ_IN (0x00000000)
7462 #define OFS_PJ_OUT (0x00000002)
7463 #define OFS_PJ_REN (0x00000006)
7464 #define OFS_PJ_SEL0 (0x0000000A)
7465 #define OFS_PJ_SEL1 (0x0000000C)
7466 #define OFS_PJ_SELC (0x00000016)
7467 #define OFS_PMAPCTL (0x0002)
7468 #define OFS_PMAPKEYID (0x0000)
7469 #define OFS_PMAP_CTL (0x00000002)
7470 #define OFS_PMAP_KEYID (0x00000000)
7471 #define OFS_PMAP_P1MAP0 (0x00000008)
7472 #define OFS_PMAP_P1MAP1 (0x00000009)
7473 #define OFS_PMAP_P1MAP2 (0x0000000A)
7474 #define OFS_PMAP_P1MAP3 (0x0000000B)
7475 #define OFS_PMAP_P1MAP4 (0x0000000C)
7476 #define OFS_PMAP_P1MAP5 (0x0000000D)
7477 #define OFS_PMAP_P1MAP6 (0x0000000E)
7478 #define OFS_PMAP_P1MAP7 (0x0000000F)
7479 #define OFS_PMAP_P2MAP0 (0x00000010)
7480 #define OFS_PMAP_P2MAP1 (0x00000011)
7481 #define OFS_PMAP_P2MAP2 (0x00000012)
7482 #define OFS_PMAP_P2MAP3 (0x00000013)
7483 #define OFS_PMAP_P2MAP4 (0x00000014)
7484 #define OFS_PMAP_P2MAP5 (0x00000015)
7485 #define OFS_PMAP_P2MAP6 (0x00000016)
7486 #define OFS_PMAP_P2MAP7 (0x00000017)
7487 #define OFS_PMAP_P3MAP0 (0x00000018)
7488 #define OFS_PMAP_P3MAP1 (0x00000019)
7489 #define OFS_PMAP_P3MAP2 (0x0000001A)
7490 #define OFS_PMAP_P3MAP3 (0x0000001B)
7491 #define OFS_PMAP_P3MAP4 (0x0000001C)
7492 #define OFS_PMAP_P3MAP5 (0x0000001D)
7493 #define OFS_PMAP_P3MAP6 (0x0000001E)
7494 #define OFS_PMAP_P3MAP7 (0x0000001F)
7495 #define OFS_PMAP_P4MAP0 (0x00000020)
7496 #define OFS_PMAP_P4MAP1 (0x00000021)
7497 #define OFS_PMAP_P4MAP2 (0x00000022)
7498 #define OFS_PMAP_P4MAP3 (0x00000023)
7499 #define OFS_PMAP_P4MAP4 (0x00000024)
7500 #define OFS_PMAP_P4MAP5 (0x00000025)
7501 #define OFS_PMAP_P4MAP6 (0x00000026)
7502 #define OFS_PMAP_P4MAP7 (0x00000027)
7503 #define OFS_PMAP_P5MAP0 (0x00000028)
7504 #define OFS_PMAP_P5MAP1 (0x00000029)
7505 #define OFS_PMAP_P5MAP2 (0x0000002A)
7506 #define OFS_PMAP_P5MAP3 (0x0000002B)
7507 #define OFS_PMAP_P5MAP4 (0x0000002C)
7508 #define OFS_PMAP_P5MAP5 (0x0000002D)
7509 #define OFS_PMAP_P5MAP6 (0x0000002E)
7510 #define OFS_PMAP_P5MAP7 (0x0000002F)
7511 #define OFS_PMAP_P6MAP0 (0x00000030)
7512 #define OFS_PMAP_P6MAP1 (0x00000031)
7513 #define OFS_PMAP_P6MAP2 (0x00000032)
7514 #define OFS_PMAP_P6MAP3 (0x00000033)
7515 #define OFS_PMAP_P6MAP4 (0x00000034)
7516 #define OFS_PMAP_P6MAP5 (0x00000035)
7517 #define OFS_PMAP_P6MAP6 (0x00000036)
7518 #define OFS_PMAP_P6MAP7 (0x00000037)
7519 #define OFS_PMAP_P7MAP0 (0x00000038)
7520 #define OFS_PMAP_P7MAP1 (0x00000039)
7521 #define OFS_PMAP_P7MAP2 (0x0000003A)
7522 #define OFS_PMAP_P7MAP3 (0x0000003B)
7523 #define OFS_PMAP_P7MAP4 (0x0000003C)
7524 #define OFS_PMAP_P7MAP5 (0x0000003D)
7525 #define OFS_PMAP_P7MAP6 (0x0000003E)
7526 #define OFS_PMAP_P7MAP7 (0x0000003F)
7527 #define OFS_PSS_CLRIFG (0x0000003C)
7528 #define OFS_PSS_DCDCCNFG1 (0x00000320)
7529 #define OFS_PSS_DCDCCNFG2 (0x00000324)
7530 #define OFS_PSS_DCDCCNFG3 (0x00000328)
7531 #define OFS_PSS_DFTATBBF (0x00000728)
7532 #define OFS_PSS_DFTATBUBF (0x0000072C)
7533 #define OFS_PSS_DFTCNFG (0x00000710)
7534 #define OFS_PSS_DFTCTRL1 (0x00000720)
7535 #define OFS_PSS_DFTCTRL2 (0x00000724)
7536 #define OFS_PSS_DOCMCTL (0x00000008)
7537 #define OFS_PSS_DOCMOUTR (0x0000000C)
7538 #define OFS_PSS_FLSHCNFG0 (0x0000030C)
7539 #define OFS_PSS_FLSHCNFG1 (0x00000310)
7540 #define OFS_PSS_IE (0x00000034)
7541 #define OFS_PSS_IFG (0x00000038)
7542 #define OFS_PSS_KEY (0x00000000)
7543 #define OFS_PSS_MISCCNFG (0x00000314)
7544 #define OFS_PSS_OPTEOP (0x0000033C)
7545 #define OFS_PSS_OSDLCNFG (0x0000031C)
7546 #define OFS_PSS_REFTRIM1 (0x00000300)
7547 #define OFS_PSS_REFTRIM2 (0x00000304)
7548 #define OFS_PSS_RSTFLG (0x00000330)
7549 #define OFS_PSS_SHCTR (0x0000032C)
7550 #define OFS_PSS_SVSCNFG (0x00000308)
7551 #define OFS_PSS_SVSMCTL (0x00000004)
7552 #define OFS_PSS_SVSMHTH01 (0x00000700)
7553 #define OFS_PSS_SVSMHTH23 (0x00000704)
7554 #define OFS_PSS_SVSMHTH45 (0x00000708)
7555 #define OFS_PSS_SVSMHTH67 (0x0000070C)
7556 #define OFS_PSS_VCOREPROG (0x00000318)
7557 #define OFS_REFCTL0 (OFS_REF_A_CTL0)
7558 #define OFS_REFCTL0_H (OFS_REFCTL0+1)
7559 #define OFS_REFCTL0_L (OFS_REFCTL0)
7560 #define OFS_REF_A_CTL0 (0x00000000)
7561 #define OFS_RSTCTL_HRDRESETCLR (0x00000008)
7562 #define OFS_RSTCTL_HRDRESETSET (0x0000000C)
7563 #define OFS_RSTCTL_HRDRESETSTAT (0x00000004)
7564 #define OFS_RSTCTL_PCMRSTCLR (0x0000010C)
7565 #define OFS_RSTCTL_PCMRSTSTAT (0x00000108)
7566 #define OFS_RSTCTL_PINRSTCLR (0x00000114)
7567 #define OFS_RSTCTL_PINRSTSTAT (0x00000110)
7568 #define OFS_RSTCTL_PSSRSTCLR (0x00000104)
7569 #define OFS_RSTCTL_PSSRSTSTAT (0x00000100)
7570 #define OFS_RSTCTL_RBTRSTCLR (0x0000011C)
7571 #define OFS_RSTCTL_RBTRSTSTAT (0x00000118)
7572 #define OFS_RSTCTL_RESETREQ (0x00000000)
7573 #define OFS_RSTCTL_SFTRESETCLR (0x00000014)
7574 #define OFS_RSTCTL_SFTRESETSET (0x00000018)
7575 #define OFS_RSTCTL_SFTRESETSTAT (0x00000010)
7576 #define OFS_RTCADOWDAY (0x001A)
7577 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
7578 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
7579 #define OFS_RTCAMINHR (0x0018)
7580 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
7581 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
7582 #define OFS_RTCCAP0CTL (0x0022)
7583 #define OFS_RTCCAP1CTL (0x0023)
7584 #define OFS_RTCCTL0 (0x0000)
7585 #define OFS_RTCCTL0_L OFS_RTCCTL0
7586 #define OFS_RTCCTL0_H OFS_RTCCTL0+1
7587 #define OFS_RTCCTL13 (0x0002)
7588 #define OFS_RTCCTL13_L OFS_RTCCTL13
7589 #define OFS_RTCCTL13_H OFS_RTCCTL13+1
7590 #define OFS_RTCDATE (0x0014)
7591 #define OFS_RTCDATE_L OFS_RTCDATE
7592 #define OFS_RTCDATE_H OFS_RTCDATE+1
7593 #define OFS_RTCDAYBAK0 (0x0033)
7594 #define OFS_RTCDAYBAK1 (0x003B)
7595 #define OFS_RTCHOURBAK0 (0x0032)
7596 #define OFS_RTCHOURBAK1 (0x003A)
7597 #define OFS_RTCIV (0x000E)
7598 #define OFS_RTCMINBAK0 (0x0031)
7599 #define OFS_RTCMINBAK1 (0x0039)
7600 #define OFS_RTCMONBAK0 (0x0034)
7601 #define OFS_RTCMONBAK1 (0x003C)
7602 #define OFS_RTCOCAL (0x0004)
7603 #define OFS_RTCPS (0x000C)
7604 #define OFS_RTCPS_L OFS_RTCPS
7605 #define OFS_RTCPS_H OFS_RTCPS+1
7606 #define OFS_RTCPS0CTL (0x0008)
7607 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
7608 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
7609 #define OFS_RTCPS1CTL (0x000A)
7610 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
7611 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
7612 #define OFS_RTCSECBAK0 (0x0030)
7613 #define OFS_RTCSECBAK1 (0x0038)
7614 #define OFS_RTCTCCTL0 (0x0020)
7615 #define OFS_RTCTCCTL1 (0x0021)
7616 #define OFS_RTCTCMP (0x0006)
7617 #define OFS_RTCTCMP_L OFS_RTCTCMP
7618 #define OFS_RTCTCMP_H OFS_RTCTCMP+1
7619 #define OFS_RTCTIM0 (0x0010)
7620 #define OFS_RTCTIM0_L OFS_RTCTIM0
7621 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
7622 #define OFS_RTCTIM1 (0x0012)
7623 #define OFS_RTCTIM1_L OFS_RTCTIM1
7624 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
7625 #define OFS_RTCYEAR (0x0016)
7626 #define OFS_RTCYEARBAK0 (0x0036)
7627 #define OFS_RTCYEARBAK1 (0x003E)
7628 #define OFS_RTC_C_ADAY (0x0000001B)
7629 #define OFS_RTC_C_ADOW (0x0000001A)
7630 #define OFS_RTC_C_AHOUR (0x00000019)
7631 #define OFS_RTC_C_AMIN (0x00000018)
7632 #define OFS_RTC_C_BCD2BIN (0x0000001E)
7633 #define OFS_RTC_C_BIN2BCD (0x0000001C)
7634 #define OFS_RTC_C_CTL0 (0x00000000)
7635 #define OFS_RTC_C_CTL1 (0x00000002)
7636 #define OFS_RTC_C_CTL3 (0x00000003)
7637 #define OFS_RTC_C_DAY (0x00000014)
7638 #define OFS_RTC_C_DOW (0x00000013)
7639 #define OFS_RTC_C_HOUR (0x00000012)
7640 #define OFS_RTC_C_IV (0x0000000E)
7641 #define OFS_RTC_C_MIN (0x00000011)
7642 #define OFS_RTC_C_MON (0x00000015)
7643 #define OFS_RTC_C_OCAL (0x00000004)
7644 #define OFS_RTC_C_PS0 (0x0000000C)
7645 #define OFS_RTC_C_PS0CTL (0x00000008)
7646 #define OFS_RTC_C_PS1 (0x0000000D)
7647 #define OFS_RTC_C_PS1CTL (0x0000000A)
7648 #define OFS_RTC_C_SEC (0x00000010)
7649 #define OFS_RTC_C_TCMP (0x00000006)
7650 #define OFS_RTC_C_YEAR (0x00000016)
7651 #define OFS_SCS_ACTLR (0x00000008)
7652 #define OFS_SCS_AFSR (0x00000D3C)
7653 #define OFS_SCS_AIRCR (0x00000D0C)
7654 #define OFS_SCS_BFAR (0x00000D38)
7655 #define OFS_SCS_CCR (0x00000D14)
7656 #define OFS_SCS_CFSR (0x00000D28)
7657 #define OFS_SCS_CID0 (0x00000FF0)
7658 #define OFS_SCS_CID1 (0x00000FF4)
7659 #define OFS_SCS_CID2 (0x00000FF8)
7660 #define OFS_SCS_CID3 (0x00000FFC)
7661 #define OFS_SCS_CPUID (0x00000D00)
7662 #define OFS_SCS_DCRDR (0x00000DF8)
7663 #define OFS_SCS_DCRSR (0x00000DF4)
7664 #define OFS_SCS_DEMCR (0x00000DFC)
7665 #define OFS_SCS_DFSR (0x00000D30)
7666 #define OFS_SCS_DHCSR (0x00000DF0)
7667 #define OFS_SCS_HFSR (0x00000D2C)
7668 #define OFS_SCS_ICSR (0x00000D04)
7669 #define OFS_SCS_ICTR (0x00000004)
7670 #define OFS_SCS_ID_AFR0 (0x00000D4C)
7671 #define OFS_SCS_ID_DFR0 (0x00000D48)
7672 #define OFS_SCS_ID_ISAR1 (0x00000D64)
7673 #define OFS_SCS_ID_ISAR2 (0x00000D68)
7674 #define OFS_SCS_ID_ISAR3 (0x00000D6C)
7675 #define OFS_SCS_ID_ISAR4 (0x00000D70)
7676 #define OFS_SCS_ID_MMFR0 (0x00000D50)
7677 #define OFS_SCS_ID_MMFR1 (0x00000D54)
7678 #define OFS_SCS_ID_MMFR2 (0x00000D58)
7679 #define OFS_SCS_ID_MMFR3 (0x00000D5C)
7680 #define OFS_SCS_ID_PFR0 (0x00000D40)
7681 #define OFS_SCS_ID_PFR1 (0x00000D44)
7682 #define OFS_SCS_ISAR0 (0x00000D60)
7683 #define OFS_SCS_MMFAR (0x00000D34)
7684 #define OFS_SCS_NVIC_IABR0 (0x00000300)
7685 #define OFS_SCS_NVIC_IABR1 (0x00000304)
7686 #define OFS_SCS_NVIC_ICER0 (0x00000180)
7687 #define OFS_SCS_NVIC_ICER1 (0x00000184)
7688 #define OFS_SCS_NVIC_ICPR0 (0x00000280)
7689 #define OFS_SCS_NVIC_ICPR1 (0x00000284)
7690 #define OFS_SCS_NVIC_IPR0 (0x00000400)
7691 #define OFS_SCS_NVIC_IPR1 (0x00000404)
7692 #define OFS_SCS_NVIC_IPR10 (0x00000428)
7693 #define OFS_SCS_NVIC_IPR11 (0x0000042C)
7694 #define OFS_SCS_NVIC_IPR12 (0x00000430)
7695 #define OFS_SCS_NVIC_IPR13 (0x00000434)
7696 #define OFS_SCS_NVIC_IPR14 (0x00000438)
7697 #define OFS_SCS_NVIC_IPR15 (0x0000043C)
7698 #define OFS_SCS_NVIC_IPR2 (0x00000408)
7699 #define OFS_SCS_NVIC_IPR3 (0x0000040C)
7700 #define OFS_SCS_NVIC_IPR4 (0x00000410)
7701 #define OFS_SCS_NVIC_IPR5 (0x00000414)
7702 #define OFS_SCS_NVIC_IPR6 (0x00000418)
7703 #define OFS_SCS_NVIC_IPR7 (0x0000041C)
7704 #define OFS_SCS_NVIC_IPR8 (0x00000420)
7705 #define OFS_SCS_NVIC_IPR9 (0x00000424)
7706 #define OFS_SCS_NVIC_ISER0 (0x00000100)
7707 #define OFS_SCS_NVIC_ISER1 (0x00000104)
7708 #define OFS_SCS_NVIC_ISPR0 (0x00000200)
7709 #define OFS_SCS_NVIC_ISPR1 (0x00000204)
7710 #define OFS_SCS_PID0 (0x00000FE0)
7711 #define OFS_SCS_PID1 (0x00000FE4)
7712 #define OFS_SCS_PID2 (0x00000FE8)
7713 #define OFS_SCS_PID3 (0x00000FEC)
7714 #define OFS_SCS_PID4 (0x00000FD0)
7715 #define OFS_SCS_PID5 (0x00000FD4)
7716 #define OFS_SCS_PID6 (0x00000FD8)
7717 #define OFS_SCS_PID7 (0x00000FDC)
7718 #define OFS_SCS_SCR (0x00000D10)
7719 #define OFS_SCS_SHCSR (0x00000D24)
7720 #define OFS_SCS_SHPR1 (0x00000D18)
7721 #define OFS_SCS_SHPR2 (0x00000D1C)
7722 #define OFS_SCS_SHPR3 (0x00000D20)
7723 #define OFS_SCS_STCR (0x0000001C)
7724 #define OFS_SCS_STCSR (0x00000010)
7725 #define OFS_SCS_STCVR (0x00000018)
7726 #define OFS_SCS_STIR (0x00000F00)
7727 #define OFS_SCS_STRVR (0x00000014)
7728 #define OFS_SCS_VTOR (0x00000D08)
7729 #define OFS_SYSCTL_DIOGLTFLTCTL (0x00000030)
7730 #define OFS_SYSCTL_FLUSER_SIZE (0x00000020)
7731 #define OFS_SYSCTL_NMI_CTLSTAT (0x00000004)
7732 #define OFS_SYSCTL_PERI_HALTCTL (0x0000000C)
7733 #define OFS_SYSCTL_REBOOT_CTL (0x00000000)
7734 #define OFS_SYSCTL_SECDATA_UNLOCK (0x00000040)
7735 #define OFS_SYSCTL_SRAM_BANKEN (0x00000014)
7736 #define OFS_SYSCTL_SRAM_BANKRET (0x00000018)
7737 #define OFS_SYSCTL_SRAM_SIZE (0x00000010)
7738 #define OFS_SYSCTL_WDT_RSTCTL (0x00000008)
7739 #define OFS_T32BGLOAD1 (0x00000018)
7740 #define OFS_T32BGLOAD2 (0x00000038)
7741 #define OFS_T32CONTROL1 (0x00000008)
7742 #define OFS_T32CONTROL2 (0x00000028)
7743 #define OFS_T32INTCLR1 (0x0000000C)
7744 #define OFS_T32INTCLR2 (0x0000002C)
7745 #define OFS_T32LOAD1 (0x00000000)
7746 #define OFS_T32LOAD2 (0x00000020)
7747 #define OFS_T32MIS1 (0x00000014)
7748 #define OFS_T32MIS2 (0x00000034)
7749 #define OFS_T32RIS1 (0x00000010)
7750 #define OFS_T32RIS2 (0x00000030)
7751 #define OFS_T32VALUE1 (0x00000004)
7752 #define OFS_T32VALUE2 (0x00000024)
7753 #define OFS_T32_BGLOAD1 (0x00000018)
7754 #define OFS_T32_BGLOAD2 (0x00000038)
7755 #define OFS_T32_CONTROL1 (0x00000008)
7756 #define OFS_T32_CONTROL2 (0x00000028)
7757 #define OFS_T32_INTCLR1 (0x0000000C)
7758 #define OFS_T32_INTCLR2 (0x0000002C)
7759 #define OFS_T32_LOAD1 (0x00000000)
7760 #define OFS_T32_LOAD2 (0x00000020)
7761 #define OFS_T32_MIS1 (0x00000014)
7762 #define OFS_T32_MIS2 (0x00000034)
7763 #define OFS_T32_RIS1 (0x00000010)
7764 #define OFS_T32_RIS2 (0x00000030)
7765 #define OFS_T32_VALUE1 (0x00000004)
7766 #define OFS_T32_VALUE2 (0x00000024)
7767 #define OFS_TA0_CCR0 (0x00000012)
7768 #define OFS_TA0_CCR1 (0x00000014)
7769 #define OFS_TA0_CCR2 (0x00000016)
7770 #define OFS_TA0_CCR3 (0x00000018)
7771 #define OFS_TA0_CCR4 (0x0000001A)
7772 #define OFS_TA0_CCR5 (0x0000001C)
7773 #define OFS_TA0_CCR6 (0x0000001E)
7774 #define OFS_TA0_CCTL0 (0x00000002)
7775 #define OFS_TA0_CCTL1 (0x00000004)
7776 #define OFS_TA0_CCTL2 (0x00000006)
7777 #define OFS_TA0_CCTL3 (0x00000008)
7778 #define OFS_TA0_CCTL4 (0x0000000A)
7779 #define OFS_TA0_CCTL5 (0x0000000C)
7780 #define OFS_TA0_CCTL6 (0x0000000E)
7781 #define OFS_TA0_CTL (0x00000000)
7782 #define OFS_TA0_EX0 (0x00000020)
7783 #define OFS_TA0_IV (0x0000002E)
7784 #define OFS_TA0_R (0x00000010)
7785 #define OFS_TA1_CCR0 (0x00000012)
7786 #define OFS_TA1_CCR1 (0x00000014)
7787 #define OFS_TA1_CCR2 (0x00000016)
7788 #define OFS_TA1_CCR3 (0x00000018)
7789 #define OFS_TA1_CCR4 (0x0000001A)
7790 #define OFS_TA1_CCR5 (0x0000001C)
7791 #define OFS_TA1_CCR6 (0x0000001E)
7792 #define OFS_TA1_CCTL0 (0x00000002)
7793 #define OFS_TA1_CCTL1 (0x00000004)
7794 #define OFS_TA1_CCTL2 (0x00000006)
7795 #define OFS_TA1_CCTL3 (0x00000008)
7796 #define OFS_TA1_CCTL4 (0x0000000A)
7797 #define OFS_TA1_CCTL5 (0x0000000C)
7798 #define OFS_TA1_CCTL6 (0x0000000E)
7799 #define OFS_TA1_CTL (0x00000000)
7800 #define OFS_TA1_EX0 (0x00000020)
7801 #define OFS_TA1_IV (0x0000002E)
7802 #define OFS_TA1_R (0x00000010)
7803 #define OFS_TA2_CCR0 (0x00000012)
7804 #define OFS_TA2_CCR1 (0x00000014)
7805 #define OFS_TA2_CCR2 (0x00000016)
7806 #define OFS_TA2_CCR3 (0x00000018)
7807 #define OFS_TA2_CCR4 (0x0000001A)
7808 #define OFS_TA2_CCR5 (0x0000001C)
7809 #define OFS_TA2_CCR6 (0x0000001E)
7810 #define OFS_TA2_CCTL0 (0x00000002)
7811 #define OFS_TA2_CCTL1 (0x00000004)
7812 #define OFS_TA2_CCTL2 (0x00000006)
7813 #define OFS_TA2_CCTL3 (0x00000008)
7814 #define OFS_TA2_CCTL4 (0x0000000A)
7815 #define OFS_TA2_CCTL5 (0x0000000C)
7816 #define OFS_TA2_CCTL6 (0x0000000E)
7817 #define OFS_TA2_CTL (0x00000000)
7818 #define OFS_TA2_EX0 (0x00000020)
7819 #define OFS_TA2_IV (0x0000002E)
7820 #define OFS_TA2_R (0x00000010)
7821 #define OFS_TA3_CCR0 (0x00000012)
7822 #define OFS_TA3_CCR1 (0x00000014)
7823 #define OFS_TA3_CCR2 (0x00000016)
7824 #define OFS_TA3_CCR3 (0x00000018)
7825 #define OFS_TA3_CCR4 (0x0000001A)
7826 #define OFS_TA3_CCR5 (0x0000001C)
7827 #define OFS_TA3_CCR6 (0x0000001E)
7828 #define OFS_TA3_CCTL0 (0x00000002)
7829 #define OFS_TA3_CCTL1 (0x00000004)
7830 #define OFS_TA3_CCTL2 (0x00000006)
7831 #define OFS_TA3_CCTL3 (0x00000008)
7832 #define OFS_TA3_CCTL4 (0x0000000A)
7833 #define OFS_TA3_CCTL5 (0x0000000C)
7834 #define OFS_TA3_CCTL6 (0x0000000E)
7835 #define OFS_TA3_CTL (0x00000000)
7836 #define OFS_TA3_EX0 (0x00000020)
7837 #define OFS_TA3_IV (0x0000002E)
7838 #define OFS_TA3_R (0x00000010)
7839 #define OFS_TAxCCR0 (OFS_TA0_CCR0)
7840 #define OFS_TAxCCR1 (OFS_TA0_CCR1)
7841 #define OFS_TAxCCR2 (OFS_TA0_CCR2)
7842 #define OFS_TAxCCR3 (OFS_TA0_CCR3)
7843 #define OFS_TAxCCR4 (OFS_TA0_CCR4)
7844 #define OFS_TAxCCR5 (OFS_TA0_CCR5)
7845 #define OFS_TAxCCR6 (OFS_TA0_CCR6)
7846 #define OFS_TAxCCTL0 (OFS_TA0_CCTL0)
7847 #define OFS_TAxCCTL1 (OFS_TA0_CCTL1)
7848 #define OFS_TAxCCTL2 (OFS_TA0_CCTL2)
7849 #define OFS_TAxCCTL3 (OFS_TA0_CCTL3)
7850 #define OFS_TAxCCTL4 (OFS_TA0_CCTL4)
7851 #define OFS_TAxCCTL5 (OFS_TA0_CCTL5)
7852 #define OFS_TAxCCTL6 (OFS_TA0_CCTL6)
7853 #define OFS_TAxCTL (OFS_TA0_CTL)
7854 #define OFS_TAxEX0 (OFS_TA0_EX0)
7855 #define OFS_TAxIV (OFS_TA0_IV)
7856 #define OFS_TAxR (OFS_TA0_R)
7857 #define OFS_UCAxABCTL (0x0010)
7858 #define OFS_UCAxBR0 (0x0006)
7859 #define OFS_UCAxBR0__SPI (0x0006)
7860 #define OFS_UCAxBR1 (0x0007)
7861 #define OFS_UCAxBR1__SPI (0x0007)
7862 #define OFS_UCAxBRW (0x0006)
7863 #define OFS_UCAxBRW__SPI (0x0006)
7864 #define OFS_UCAxCTL0 (0x0001)
7865 #define OFS_UCAxCTL0__SPI (0x0001)
7866 #define OFS_UCAxCTL1 (0x0000)
7867 #define OFS_UCAxCTL1__SPI (0x0000)
7868 #define OFS_UCAxCTLW0 (0x0000)
7869 #define OFS_UCAxCTLW0__SPI (0x0000)
7870 #define OFS_UCAxCTLW1 (0x0002)
7871 #define OFS_UCAxIE (0x001A)
7872 #define OFS_UCAxIE__SPI (0x001A)
7873 #define OFS_UCAxIE__UART (0x001A)
7874 #define OFS_UCAxIFG (0x001C)
7875 #define OFS_UCAxIFG__SPI (0x001C)
7876 #define OFS_UCAxIFG__UART (0x001C)
7877 #define OFS_UCAxIRCTL (0x0012)
7878 #define OFS_UCAxIRRCTL (0x0013)
7879 #define OFS_UCAxIRTCTL (0x0012)
7880 #define OFS_UCAxIV (0x001E)
7881 #define OFS_UCAxIV__SPI (0x001E)
7882 #define OFS_UCAxMCTLW (0x0008)
7883 #define OFS_UCAxRXBUF (0x000C)
7884 #define OFS_UCAxRXBUF__SPI (0x000C)
7885 #define OFS_UCAxSTATW (0x000A)
7886 #define OFS_UCAxSTATW__SPI (0x000A)
7887 #define OFS_UCAxTXBUF (0x000E)
7888 #define OFS_UCAxTXBUF__SPI (0x000E)
7889 #define OFS_UCBxADDMASK (0x001E)
7890 #define OFS_UCBxADDRX (0x001C)
7891 #define OFS_UCBxBCNT__I2C (0x0009)
7892 #define OFS_UCBxBR0 (0x0006)
7893 #define OFS_UCBxBR0__SPI (0x0006)
7894 #define OFS_UCBxBR1 (0x0007)
7895 #define OFS_UCBxBR1__SPI (0x0007)
7896 #define OFS_UCBxBRW (0x0006)
7897 #define OFS_UCBxBRW__SPI (0x0006)
7898 #define OFS_UCBxCTL0 (0x0001)
7899 #define OFS_UCBxCTL0__SPI (0x0001)
7900 #define OFS_UCBxCTL1 (0x0000)
7901 #define OFS_UCBxCTL1__SPI (0x0000)
7902 #define OFS_UCBxCTLW0 (0x0000)
7903 #define OFS_UCBxCTLW0__SPI (0x0000)
7904 #define OFS_UCBxCTLW1 (0x0002)
7905 #define OFS_UCBxI2COA0 (0x0014)
7906 #define OFS_UCBxI2COA1 (0x0016)
7907 #define OFS_UCBxI2COA2 (0x0018)
7908 #define OFS_UCBxI2COA3 (0x001A)
7909 #define OFS_UCBxI2CSA (0x0020)
7910 #define OFS_UCBxIE (0x002A)
7911 #define OFS_UCBxIE__I2C (0x002A)
7912 #define OFS_UCBxIE__SPI (0x002A)
7913 #define OFS_UCBxIFG (0x002C)
7914 #define OFS_UCBxIFG__I2C (0x002C)
7915 #define OFS_UCBxIFG__SPI (0x002C)
7916 #define OFS_UCBxIV (0x002E)
7917 #define OFS_UCBxIV__SPI (0x002E)
7918 #define OFS_UCBxRXBUF (0x000C)
7919 #define OFS_UCBxRXBUF__SPI (0x000C)
7920 #define OFS_UCBxSTATW (0x0008)
7921 #define OFS_UCBxSTATW__I2C (0x0008)
7922 #define OFS_UCBxSTATW__SPI (0x0008)
7923 #define OFS_UCBxSTAT__I2C (0x0008)
7924 #define OFS_UCBxTBCNT (0x000A)
7925 #define OFS_UCBxTXBUF (0x000E)
7926 #define OFS_UCBxTXBUF__SPI (0x000E)
7927 #define OFS_UDMA_ALTBASE (0x0000000C)
7928 #define OFS_UDMA_ALTCLR (0x00000034)
7929 #define OFS_UDMA_ALTSET (0x00000030)
7930 #define OFS_UDMA_CFG (0x00000004)
7931 #define OFS_UDMA_CTLBASE (0x00000008)
7932 #define OFS_UDMA_ENACLR (0x0000002C)
7933 #define OFS_UDMA_ENASET (0x00000028)
7934 #define OFS_UDMA_ERRCLR (0x0000004C)
7935 #define OFS_UDMA_PCELL_ID_0 (0x00000FF0)
7936 #define OFS_UDMA_PCELL_ID_1 (0x00000FF4)
7937 #define OFS_UDMA_PCELL_ID_2 (0x00000FF8)
7938 #define OFS_UDMA_PCELL_ID_3 (0x00000FFC)
7939 #define OFS_UDMA_PERIPH_ID_0 (0x00000FE0)
7940 #define OFS_UDMA_PERIPH_ID_1 (0x00000FE4)
7941 #define OFS_UDMA_PERIPH_ID_2 (0x00000FE8)
7942 #define OFS_UDMA_PERIPH_ID_3 (0x00000FEC)
7943 #define OFS_UDMA_PERIPH_ID_4 (0x00000FD0)
7944 #define OFS_UDMA_PRIOCLR (0x0000003C)
7945 #define OFS_UDMA_PRIOSET (0x00000038)
7946 #define OFS_UDMA_REQMASKCLR (0x00000024)
7947 #define OFS_UDMA_REQMASKSET (0x00000020)
7948 #define OFS_UDMA_STAT (0x00000000)
7949 #define OFS_UDMA_SWREQ (0x00000014)
7950 #define OFS_UDMA_USEBURSTCLR (0x0000001C)
7951 #define OFS_UDMA_USEBURSTSET (0x00000018)
7952 #define OFS_UDMA_WAITSTAT (0x00000010)
7953 #define OFS_WDTCTL (OFS_WDT_A_CTL)
7954 #define OFS_WDTCTL_H (OFS_WDTCTL+1)
7955 #define OFS_WDTCTL_L (OFS_WDTCTL)
7956 #define OFS_WDT_A_CTL (0x0000000C)
7957 #define OUTMOD0 (0x0020)
7958 #define OUTMOD1 (0x0040)
7959 #define OUTMOD2 (0x0080)
7960 #define P10IV_NONE (0x0000)
7961 #define P10IV_P10IFG0 (0x0002)
7962 #define P10IV_P10IFG1 (0x0004)
7963 #define P10IV_P10IFG2 (0x0006)
7964 #define P10IV_P10IFG3 (0x0008)
7965 #define P10IV_P10IFG4 (0x000A)
7966 #define P10IV_P10IFG5 (0x000C)
7967 #define P10IV_P10IFG6 (0x000E)
7968 #define P10IV_P10IFG7 (0x0010)
7969 #define P10_DIR (HWREG8(0x40004C85))
7970 #define P10_DS (HWREG8(0x40004C89))
7971 #define P10_IE (HWREG8(0x40004C9B))
7972 #define P10_IES (HWREG8(0x40004C99))
7973 #define P10_IFG (HWREG8(0x40004C9D))
7974 #define P10_IN (HWREG8(0x40004C81))
7975 #define P10_IV (HWREG8(0x40004C9E))
7976 #define P10_OUT (HWREG8(0x40004C83))
7977 #define P10_REN (HWREG8(0x40004C87))
7978 #define P10_SEL0 (HWREG8(0x40004C8B))
7979 #define P10_SEL1 (HWREG8(0x40004C8D))
7980 #define P10_SELC (HWREG8(0x40004C97))
7981 #define P1IV_NONE (0x0000)
7982 #define P1IV_P1IFG0 (0x0002)
7983 #define P1IV_P1IFG1 (0x0004)
7984 #define P1IV_P1IFG2 (0x0006)
7985 #define P1IV_P1IFG3 (0x0008)
7986 #define P1IV_P1IFG4 (0x000A)
7987 #define P1IV_P1IFG5 (0x000C)
7988 #define P1IV_P1IFG6 (0x000E)
7989 #define P1IV_P1IFG7 (0x0010)
7990 #define P1MAP0 (PMAP_P1MAP0)
7991 #define P1MAP1 (PMAP_P1MAP1)
7992 #define P1MAP2 (PMAP_P1MAP2)
7993 #define P1MAP3 (PMAP_P1MAP3)
7994 #define P1MAP4 (PMAP_P1MAP4)
7995 #define P1MAP5 (PMAP_P1MAP5)
7996 #define P1MAP6 (PMAP_P1MAP6)
7997 #define P1MAP7 (PMAP_P1MAP7)
7998 #define P1_DIR (HWREG8(0x40004C04))
7999 #define P1_DS (HWREG8(0x40004C08))
8000 #define P1_IE (HWREG8(0x40004C1A))
8001 #define P1_IES (HWREG8(0x40004C18))
8002 #define P1_IFG (HWREG8(0x40004C1C))
8003 #define P1_IN (HWREG8(0x40004C00))
8004 #define P1_IV (HWREG8(0x40004C0E))
8005 #define P1_OUT (HWREG8(0x40004C02))
8006 #define P1_REN (HWREG8(0x40004C06))
8007 #define P1_SEL0 (HWREG8(0x40004C0A))
8008 #define P1_SEL1 (HWREG8(0x40004C0C))
8009 #define P1_SELC (HWREG8(0x40004C16))
8010 #define P2IV_NONE (0x0000)
8011 #define P2IV_P2IFG0 (0x0002)
8012 #define P2IV_P2IFG1 (0x0004)
8013 #define P2IV_P2IFG2 (0x0006)
8014 #define P2IV_P2IFG3 (0x0008)
8015 #define P2IV_P2IFG4 (0x000A)
8016 #define P2IV_P2IFG5 (0x000C)
8017 #define P2IV_P2IFG6 (0x000E)
8018 #define P2IV_P2IFG7 (0x0010)
8019 #define P2MAP0 (PMAP_P2MAP0)
8020 #define P2MAP1 (PMAP_P2MAP1)
8021 #define P2MAP2 (PMAP_P2MAP2)
8022 #define P2MAP3 (PMAP_P2MAP3)
8023 #define P2MAP4 (PMAP_P2MAP4)
8024 #define P2MAP5 (PMAP_P2MAP5)
8025 #define P2MAP6 (PMAP_P2MAP6)
8026 #define P2MAP7 (PMAP_P2MAP7)
8027 #define P2_DIR (HWREG8(0x40004C05))
8028 #define P2_DS (HWREG8(0x40004C09))
8029 #define P2_IE (HWREG8(0x40004C1B))
8030 #define P2_IES (HWREG8(0x40004C19))
8031 #define P2_IFG (HWREG8(0x40004C1D))
8032 #define P2_IN (HWREG8(0x40004C01))
8033 #define P2_IV (HWREG8(0x40004C1E))
8034 #define P2_OUT (HWREG8(0x40004C03))
8035 #define P2_REN (HWREG8(0x40004C07))
8036 #define P2_SEL0 (HWREG8(0x40004C0B))
8037 #define P2_SEL1 (HWREG8(0x40004C0D))
8038 #define P2_SELC (HWREG8(0x40004C17))
8039 #define P3IV_NONE (0x0000)
8040 #define P3IV_P3IFG0 (0x0002)
8041 #define P3IV_P3IFG1 (0x0004)
8042 #define P3IV_P3IFG2 (0x0006)
8043 #define P3IV_P3IFG3 (0x0008)
8044 #define P3IV_P3IFG4 (0x000A)
8045 #define P3IV_P3IFG5 (0x000C)
8046 #define P3IV_P3IFG6 (0x000E)
8047 #define P3IV_P3IFG7 (0x0010)
8048 #define P3MAP0 (PMAP_P3MAP0)
8049 #define P3MAP1 (PMAP_P3MAP1)
8050 #define P3MAP2 (PMAP_P3MAP2)
8051 #define P3MAP3 (PMAP_P3MAP3)
8052 #define P3MAP4 (PMAP_P3MAP4)
8053 #define P3MAP5 (PMAP_P3MAP5)
8054 #define P3MAP6 (PMAP_P3MAP6)
8055 #define P3MAP7 (PMAP_P3MAP7)
8056 #define P3_DIR (HWREG8(0x40004C24))
8057 #define P3_DS (HWREG8(0x40004C28))
8058 #define P3_IE (HWREG8(0x40004C3A))
8059 #define P3_IES (HWREG8(0x40004C38))
8060 #define P3_IFG (HWREG8(0x40004C3C))
8061 #define P3_IN (HWREG8(0x40004C20))
8062 #define P3_IV (HWREG8(0x40004C2E))
8063 #define P3_OUT (HWREG8(0x40004C22))
8064 #define P3_REN (HWREG8(0x40004C26))
8065 #define P3_SEL0 (HWREG8(0x40004C2A))
8066 #define P3_SEL1 (HWREG8(0x40004C2C))
8067 #define P3_SELC (HWREG8(0x40004C36))
8068 #define P4IV_NONE (0x0000)
8069 #define P4IV_P4IFG0 (0x0002)
8070 #define P4IV_P4IFG1 (0x0004)
8071 #define P4IV_P4IFG2 (0x0006)
8072 #define P4IV_P4IFG3 (0x0008)
8073 #define P4IV_P4IFG4 (0x000A)
8074 #define P4IV_P4IFG5 (0x000C)
8075 #define P4IV_P4IFG6 (0x000E)
8076 #define P4IV_P4IFG7 (0x0010)
8077 #define P4MAP0 (PMAP_P4MAP0)
8078 #define P4MAP1 (PMAP_P4MAP1)
8079 #define P4MAP2 (PMAP_P4MAP2)
8080 #define P4MAP3 (PMAP_P4MAP3)
8081 #define P4MAP4 (PMAP_P4MAP4)
8082 #define P4MAP5 (PMAP_P4MAP5)
8083 #define P4MAP6 (PMAP_P4MAP6)
8084 #define P4MAP7 (PMAP_P4MAP7)
8085 #define P4_DIR (HWREG8(0x40004C25))
8086 #define P4_DS (HWREG8(0x40004C29))
8087 #define P4_IE (HWREG8(0x40004C3B))
8088 #define P4_IES (HWREG8(0x40004C39))
8089 #define P4_IFG (HWREG8(0x40004C3D))
8090 #define P4_IN (HWREG8(0x40004C21))
8091 #define P4_IV (HWREG8(0x40004C3E))
8092 #define P4_OUT (HWREG8(0x40004C23))
8093 #define P4_REN (HWREG8(0x40004C27))
8094 #define P4_SEL0 (HWREG8(0x40004C2B))
8095 #define P4_SEL1 (HWREG8(0x40004C2D))
8096 #define P4_SELC (HWREG8(0x40004C37))
8097 #define P5IV_NONE (0x0000)
8098 #define P5IV_P5IFG0 (0x0002)
8099 #define P5IV_P5IFG1 (0x0004)
8100 #define P5IV_P5IFG2 (0x0006)
8101 #define P5IV_P5IFG3 (0x0008)
8102 #define P5IV_P5IFG4 (0x000A)
8103 #define P5IV_P5IFG5 (0x000C)
8104 #define P5IV_P5IFG6 (0x000E)
8105 #define P5IV_P5IFG7 (0x0010)
8106 #define P5MAP0 (PMAP_P5MAP0)
8107 #define P5MAP1 (PMAP_P5MAP1)
8108 #define P5MAP2 (PMAP_P5MAP2)
8109 #define P5MAP3 (PMAP_P5MAP3)
8110 #define P5MAP4 (PMAP_P5MAP4)
8111 #define P5MAP5 (PMAP_P5MAP5)
8112 #define P5MAP6 (PMAP_P5MAP6)
8113 #define P5MAP7 (PMAP_P5MAP7)
8114 #define P5_DIR (HWREG8(0x40004C44))
8115 #define P5_DS (HWREG8(0x40004C48))
8116 #define P5_IE (HWREG8(0x40004C5A))
8117 #define P5_IES (HWREG8(0x40004C58))
8118 #define P5_IFG (HWREG8(0x40004C5C))
8119 #define P5_IN (HWREG8(0x40004C40))
8120 #define P5_IV (HWREG8(0x40004C4E))
8121 #define P5_OUT (HWREG8(0x40004C42))
8122 #define P5_REN (HWREG8(0x40004C46))
8123 #define P5_SEL0 (HWREG8(0x40004C4A))
8124 #define P5_SEL1 (HWREG8(0x40004C4C))
8125 #define P5_SELC (HWREG8(0x40004C56))
8126 #define P6IV_NONE (0x0000)
8127 #define P6IV_P6IFG0 (0x0002)
8128 #define P6IV_P6IFG1 (0x0004)
8129 #define P6IV_P6IFG2 (0x0006)
8130 #define P6IV_P6IFG3 (0x0008)
8131 #define P6IV_P6IFG4 (0x000A)
8132 #define P6IV_P6IFG5 (0x000C)
8133 #define P6IV_P6IFG6 (0x000E)
8134 #define P6IV_P6IFG7 (0x0010)
8135 #define P6_DIR (HWREG8(0x40004C45))
8136 #define P6_DS (HWREG8(0x40004C49))
8137 #define P6_IE (HWREG8(0x40004C5B))
8138 #define P6_IES (HWREG8(0x40004C59))
8139 #define P6_IFG (HWREG8(0x40004C5D))
8140 #define P6_IN (HWREG8(0x40004C41))
8141 #define P6_IV (HWREG8(0x40004C5E))
8142 #define P6_OUT (HWREG8(0x40004C43))
8143 #define P6_REN (HWREG8(0x40004C47))
8144 #define P6_SEL0 (HWREG8(0x40004C4B))
8145 #define P6_SEL1 (HWREG8(0x40004C4D))
8146 #define P6_SELC (HWREG8(0x40004C57))
8147 #define P7IV_NONE (0x0000)
8148 #define P7IV_P7IFG0 (0x0002)
8149 #define P7IV_P7IFG1 (0x0004)
8150 #define P7IV_P7IFG2 (0x0006)
8151 #define P7IV_P7IFG3 (0x0008)
8152 #define P7IV_P7IFG4 (0x000A)
8153 #define P7IV_P7IFG5 (0x000C)
8154 #define P7IV_P7IFG6 (0x000E)
8155 #define P7IV_P7IFG7 (0x0010)
8156 #define P7_DIR (HWREG8(0x40004C64))
8157 #define P7_DS (HWREG8(0x40004C68))
8158 #define P7_IE (HWREG8(0x40004C7A))
8159 #define P7_IES (HWREG8(0x40004C78))
8160 #define P7_IFG (HWREG8(0x40004C7C))
8161 #define P7_IN (HWREG8(0x40004C60))
8162 #define P7_IV (HWREG8(0x40004C6E))
8163 #define P7_OUT (HWREG8(0x40004C62))
8164 #define P7_REN (HWREG8(0x40004C66))
8165 #define P7_SEL0 (HWREG8(0x40004C6A))
8166 #define P7_SEL1 (HWREG8(0x40004C6C))
8167 #define P7_SELC (HWREG8(0x40004C76))
8168 #define P8IV_NONE (0x0000)
8169 #define P8IV_P8IFG0 (0x0002)
8170 #define P8IV_P8IFG1 (0x0004)
8171 #define P8IV_P8IFG2 (0x0006)
8172 #define P8IV_P8IFG3 (0x0008)
8173 #define P8IV_P8IFG4 (0x000A)
8174 #define P8IV_P8IFG5 (0x000C)
8175 #define P8IV_P8IFG6 (0x000E)
8176 #define P8IV_P8IFG7 (0x0010)
8177 #define P8_DIR (HWREG8(0x40004C65))
8178 #define P8_DS (HWREG8(0x40004C69))
8179 #define P8_IE (HWREG8(0x40004C7B))
8180 #define P8_IES (HWREG8(0x40004C79))
8181 #define P8_IFG (HWREG8(0x40004C7D))
8182 #define P8_IN (HWREG8(0x40004C61))
8183 #define P8_IV (HWREG8(0x40004C7E))
8184 #define P8_OUT (HWREG8(0x40004C63))
8185 #define P8_REN (HWREG8(0x40004C67))
8186 #define P8_SEL0 (HWREG8(0x40004C6B))
8187 #define P8_SEL1 (HWREG8(0x40004C6D))
8188 #define P8_SELC (HWREG8(0x40004C77))
8189 #define P9IV_NONE (0x0000)
8190 #define P9IV_P9IFG0 (0x0002)
8191 #define P9IV_P9IFG1 (0x0004)
8192 #define P9IV_P9IFG2 (0x0006)
8193 #define P9IV_P9IFG3 (0x0008)
8194 #define P9IV_P9IFG4 (0x000A)
8195 #define P9IV_P9IFG5 (0x000C)
8196 #define P9IV_P9IFG6 (0x000E)
8197 #define P9IV_P9IFG7 (0x0010)
8198 #define P9_DIR (HWREG8(0x40004C84))
8199 #define P9_DS (HWREG8(0x40004C88))
8200 #define P9_IE (HWREG8(0x40004C9A))
8201 #define P9_IES (HWREG8(0x40004C98))
8202 #define P9_IFG (HWREG8(0x40004C9C))
8203 #define P9_IN (HWREG8(0x40004C80))
8204 #define P9_IV (HWREG8(0x40004C8E))
8205 #define P9_OUT (HWREG8(0x40004C82))
8206 #define P9_REN (HWREG8(0x40004C86))
8207 #define P9_SEL0 (HWREG8(0x40004C8A))
8208 #define P9_SEL1 (HWREG8(0x40004C8C))
8209 #define P9_SELC (HWREG8(0x40004C96))
8210 #define PADIR_H (HWREG8_H(PADIR))
8211 #define PADIR_L (HWREG8_L(PADIR))
8212 #define PAIES_H (HWREG8_H(PAIES))
8213 #define PAIES_L (HWREG8_L(PAIES))
8214 #define PAIE_H (HWREG8_H(PAIE))
8215 #define PAIE_L (HWREG8_L(PAIE))
8216 #define PAIFG_H (HWREG8_H(PAIFG))
8217 #define PAIFG_L (HWREG8_L(PAIFG))
8218 #define PAIN_H (HWREG8_H(PAIN))
8219 #define PAIN_L (HWREG8_L(PAIN))
8220 #define PAOUT_H (HWREG8_H(PAOUT))
8221 #define PAOUT_L (HWREG8_L(PAOUT))
8222 #define PAREN_H (HWREG8_H(PAREN))
8223 #define PAREN_L (HWREG8_L(PAREN))
8224 #define PASEL0_H (HWREG8_H(PASEL0))
8225 #define PASEL0_L (HWREG8_L(PASEL0))
8226 #define PASEL1_H (HWREG8_H(PASEL1))
8227 #define PASEL1_L (HWREG8_L(PASEL1))
8228 #define PA_DIR (HWREG16(0x40004C04))
8229 #define PA_DS (HWREG16(0x40004C08))
8230 #define PA_IE (HWREG16(0x40004C1A))
8231 #define PA_IES (HWREG16(0x40004C18))
8232 #define PA_IFG (HWREG16(0x40004C1C))
8233 #define PA_IN (HWREG16(0x40004C00))
8234 #define PA_OUT (HWREG16(0x40004C02))
8235 #define PA_REN (HWREG16(0x40004C06))
8236 #define PA_SEL0 (HWREG16(0x40004C0A))
8237 #define PA_SEL1 (HWREG16(0x40004C0C))
8238 #define PA_SELC (HWREG16(0x40004C16))
8239 #define PBDIR_H (HWREG8_H(PBDIR))
8240 #define PBDIR_L (HWREG8_L(PBDIR))
8241 #define PBIES_H (HWREG8_H(PBIES))
8242 #define PBIES_L (HWREG8_L(PBIES))
8243 #define PBIE_H (HWREG8_H(PBIE))
8244 #define PBIE_L (HWREG8_L(PBIE))
8245 #define PBIFG_H (HWREG8_H(PBIFG))
8246 #define PBIFG_L (HWREG8_L(PBIFG))
8247 #define PBIN_H (HWREG8_H(PBIN))
8248 #define PBIN_L (HWREG8_L(PBIN))
8249 #define PBOUT_H (HWREG8_H(PBOUT))
8250 #define PBOUT_L (HWREG8_L(PBOUT))
8251 #define PBREN_H (HWREG8_H(PBREN))
8252 #define PBREN_L (HWREG8_L(PBREN))
8253 #define PBSEL0_H (HWREG8_H(PBSEL0))
8254 #define PBSEL0_L (HWREG8_L(PBSEL0))
8255 #define PBSEL1_H (HWREG8_H(PBSEL1))
8256 #define PBSEL1_L (HWREG8_L(PBSEL1))
8257 #define PB_DIR (HWREG16(0x40004C24))
8258 #define PB_DS (HWREG16(0x40004C28))
8259 #define PB_IE (HWREG16(0x40004C3A))
8260 #define PB_IES (HWREG16(0x40004C38))
8261 #define PB_IFG (HWREG16(0x40004C3C))
8262 #define PB_IN (HWREG16(0x40004C20))
8263 #define PB_OUT (HWREG16(0x40004C22))
8264 #define PB_REN (HWREG16(0x40004C26))
8265 #define PB_SEL0 (HWREG16(0x40004C2A))
8266 #define PB_SEL1 (HWREG16(0x40004C2C))
8267 #define PB_SELC (HWREG16(0x40004C36))
8268 #define PCDIR_H (HWREG8_H(PCDIR))
8269 #define PCDIR_L (HWREG8_L(PCDIR))
8270 #define PCIES_H (HWREG8_H(PCIES))
8271 #define PCIES_L (HWREG8_L(PCIES))
8272 #define PCIE_H (HWREG8_H(PCIE))
8273 #define PCIE_L (HWREG8_L(PCIE))
8274 #define PCIFG_H (HWREG8_H(PCIFG))
8275 #define PCIFG_L (HWREG8_L(PCIFG))
8276 #define PCIN_H (HWREG8_H(PCIN))
8277 #define PCIN_L (HWREG8_L(PCIN))
8278 #define PCM_CTL (HWREG32(0x40010004))
8279 #define PCM_CTL_FORCE_DSL_SD_ENTRY (0x00000004)
8280 #define PCM_CTL_KEY_VAL (0x695A0000)
8281 #define PCM_CTL_KEY__M (0xffff0000)
8282 #define PCM_CTL_LOCKRTC (0x00000002)
8283 #define PCM_CTL_LOCKRTC__0 (0x00000000)
8284 #define PCM_CTL_LOCKRTC__1 (0x00000002)
8285 #define PCM_CTL_LOCKSD (0x00000001)
8286 #define PCM_CTL_LOCKSD__0 (0x00000000)
8287 #define PCM_CTL_LOCKSD__1 (0x00000001)
8288 #define PCM_CTL_PMR_BUSY (0x00000100)
8289 #define PCM_INTCLR (HWREG32(0x40010010))
8290 #define PCM_INTCLR_CLR_AM_INVALID_TR (0x00000004)
8291 #define PCM_INTCLR_CLR_AM_INVALID_TR__0 (0x00000000)
8292 #define PCM_INTCLR_CLR_AM_INVALID_TR__0_NO_EFFECT (0x00000000)
8293 #define PCM_INTCLR_CLR_AM_INVALID_TR__1 (0x00000004)
8294 #define PCM_INTCLR_CLR_AM_INVALID_TR__1_CLEAR_FLAG (0x00000004)
8295 #define PCM_INTCLR_CLR_DCDC_ERROR (0x00000040)
8296 #define PCM_INTCLR_CLR_DCDC_ERROR__0 (0x00000000)
8297 #define PCM_INTCLR_CLR_DCDC_ERROR__0_NO_EFFECT (0x00000000)
8298 #define PCM_INTCLR_CLR_DCDC_ERROR__1 (0x00000040)
8299 #define PCM_INTCLR_CLR_DCDC_ERROR__1_CLEAR_FLAG (0x00000040)
8300 #define PCM_INTCLR_CLR_SM_INVALID_CLK (0x00000002)
8301 #define PCM_INTCLR_CLR_SM_INVALID_CLK__0 (0x00000000)
8302 #define PCM_INTCLR_CLR_SM_INVALID_CLK__0_NO_EFFECT (0x00000000)
8303 #define PCM_INTCLR_CLR_SM_INVALID_CLK__1 (0x00000002)
8304 #define PCM_INTCLR_CLR_SM_INVALID_CLK__1_CLEAR_FLAG (0x00000002)
8305 #define PCM_INTCLR_CLR_SM_INVALID_TR (0x00000001)
8306 #define PCM_INTCLR_CLR_SM_INVALID_TR__0 (0x00000000)
8307 #define PCM_INTCLR_CLR_SM_INVALID_TR__0_NO_EFFECT (0x00000000)
8308 #define PCM_INTCLR_CLR_SM_INVALID_TR__1 (0x00000001)
8309 #define PCM_INTCLR_CLR_SM_INVALID_TR__1_CLEAR_FLAG (0x00000001)
8310 #define PCM_INTEN (HWREG32(0x40010008))
8311 #define PCM_INTEN_EN_AM_INVALID_TR (0x00000004)
8312 #define PCM_INTEN_EN_AM_INVALID_TR__0 (0x00000000)
8313 #define PCM_INTEN_EN_AM_INVALID_TR__0_DISABLED (0x00000000)
8314 #define PCM_INTEN_EN_AM_INVALID_TR__1 (0x00000004)
8315 #define PCM_INTEN_EN_AM_INVALID_TR__1_ENABLED (0x00000004)
8316 #define PCM_INTEN_EN_DCDC_ERROR (0x00000040)
8317 #define PCM_INTEN_EN_DCDC_ERROR__0 (0x00000000)
8318 #define PCM_INTEN_EN_DCDC_ERROR__0_DISABLED (0x00000000)
8319 #define PCM_INTEN_EN_DCDC_ERROR__1 (0x00000040)
8320 #define PCM_INTEN_EN_DCDC_ERROR__1_ENABLED (0x00000040)
8321 #define PCM_INTEN_EN_SM_INVALID_CLK (0x00000002)
8322 #define PCM_INTEN_EN_SM_INVALID_CLK__0 (0x00000000)
8323 #define PCM_INTEN_EN_SM_INVALID_CLK__0_DISABLED (0x00000000)
8324 #define PCM_INTEN_EN_SM_INVALID_CLK__1 (0x00000002)
8325 #define PCM_INTEN_EN_SM_INVALID_CLK__1_ENABLED (0x00000002)
8326 #define PCM_INTEN_EN_SM_INVALID_TR (0x00000001)
8327 #define PCM_INTEN_EN_SM_INVALID_TR__0 (0x00000000)
8328 #define PCM_INTEN_EN_SM_INVALID_TR__0_DISABLED (0x00000000)
8329 #define PCM_INTEN_EN_SM_INVALID_TR__1 (0x00000001)
8330 #define PCM_INTEN_EN_SM_INVALID_TR__1_ENABLED (0x00000001)
8331 #define PCM_INTFLAG (HWREG32(0x4001000C))
8332 #define PCM_INTFLAG_AM_INVALID_TR (0x00000004)
8333 #define PCM_INTFLAG_DCDC_ERROR (0x00000040)
8334 #define PCM_INTFLAG_SM_INVALID_CLK (0x00000002)
8335 #define PCM_INTFLAG_SM_INVALID_TR (0x00000001)
8336 #define PCM_PMR (HWREG32(0x40010000))
8337 #define PCM_PMR_AMR__0 (0x00000000)
8338 #define PCM_PMR_AMR__0_AM0_LDO (0x00000000)
8339 #define PCM_PMR_AMR__1 (0x00000001)
8340 #define PCM_PMR_AMR__1_AM1_LDO (0x00000001)
8341 #define PCM_PMR_AMR__4 (0x00000004)
8342 #define PCM_PMR_AMR__4_AM0_DCDC (0x00000004)
8343 #define PCM_PMR_AMR__5 (0x00000005)
8344 #define PCM_PMR_AMR__5_AM1_DCDC (0x00000005)
8345 #define PCM_PMR_AMR__8 (0x00000008)
8346 #define PCM_PMR_AMR__8_AM0_LPR (0x00000008)
8347 #define PCM_PMR_AMR__9 (0x00000009)
8348 #define PCM_PMR_AMR__9_AM1_LPR (0x00000009)
8349 #define PCM_PMR_AMR__M (0x0000000f)
8350 #define PCM_PMR_CPM__0 (0x00000000)
8351 #define PCM_PMR_CPM__0_AM0_LDO (0x00000000)
8352 #define PCM_PMR_CPM__1 (0x00000100)
8353 #define PCM_PMR_CPM__16 (0x00001000)
8354 #define PCM_PMR_CPM__16_SL0_LDO (0x00001000)
8355 #define PCM_PMR_CPM__17 (0x00001100)
8356 #define PCM_PMR_CPM__17_SL1_LDO (0x00001100)
8357 #define PCM_PMR_CPM__1_AM1_LDO (0x00000100)
8358 #define PCM_PMR_CPM__20 (0x00001400)
8359 #define PCM_PMR_CPM__20_SL0_DCDC (0x00001400)
8360 #define PCM_PMR_CPM__21 (0x00001500)
8361 #define PCM_PMR_CPM__21_SL1_DCDC (0x00001500)
8362 #define PCM_PMR_CPM__24 (0x00001800)
8363 #define PCM_PMR_CPM__24_SL0_LPR (0x00001800)
8364 #define PCM_PMR_CPM__25 (0x00001900)
8365 #define PCM_PMR_CPM__25_SL1_LPR (0x00001900)
8366 #define PCM_PMR_CPM__32 (0x00002000)
8367 #define PCM_PMR_CPM__32_DSL (0x00002000)
8368 #define PCM_PMR_CPM__4 (0x00000400)
8369 #define PCM_PMR_CPM__4_AM0_DCDC (0x00000400)
8370 #define PCM_PMR_CPM__5 (0x00000500)
8371 #define PCM_PMR_CPM__5_AM1_DCDC (0x00000500)
8372 #define PCM_PMR_CPM__63 (0x00003f00)
8373 #define PCM_PMR_CPM__63_AM_DEFAULT (0x00003f00)
8374 #define PCM_PMR_CPM__8 (0x00000800)
8375 #define PCM_PMR_CPM__8_AM0_LPR (0x00000800)
8376 #define PCM_PMR_CPM__9 (0x00000900)
8377 #define PCM_PMR_CPM__9_AM1_LPR (0x00000900)
8378 #define PCM_PMR_CPM__M (0x00003f00)
8379 #define PCM_PMR_KEY_VAL (0x695A0000)
8380 #define PCM_PMR_KEY__M (0xffff0000)
8381 #define PCM_PMR_SDR__0 (0x00000000)
8382 #define PCM_PMR_SDR__10 (0x000000a0)
8383 #define PCM_PMR_SDR__12 (0x000000c0)
8384 #define PCM_PMR_SDR__M (0x000000f0)
8385 #define PCOUT_H (HWREG8_H(PCOUT))
8386 #define PCOUT_L (HWREG8_L(PCOUT))
8387 #define PCREN_H (HWREG8_H(PCREN))
8388 #define PCREN_L (HWREG8_L(PCREN))
8389 #define PCSEL0_H (HWREG8_H(PCSEL0))
8390 #define PCSEL0_L (HWREG8_L(PCSEL0))
8391 #define PCSEL1_H (HWREG8_H(PCSEL1))
8392 #define PCSEL1_L (HWREG8_L(PCSEL1))
8393 #define PC_DIR (HWREG16(0x40004C44))
8394 #define PC_DS (HWREG16(0x40004C48))
8395 #define PC_IE (HWREG16(0x40004C5A))
8396 #define PC_IES (HWREG16(0x40004C58))
8397 #define PC_IFG (HWREG16(0x40004C5C))
8398 #define PC_IN (HWREG16(0x40004C40))
8399 #define PC_OUT (HWREG16(0x40004C42))
8400 #define PC_REN (HWREG16(0x40004C46))
8401 #define PC_SEL0 (HWREG16(0x40004C4A))
8402 #define PC_SEL1 (HWREG16(0x40004C4C))
8403 #define PC_SELC (HWREG16(0x40004C56))
8404 #define PDDIR_H (HWREG8_H(PDDIR))
8405 #define PDDIR_L (HWREG8_L(PDDIR))
8406 #define PDIN_H (HWREG8_H(PDIN))
8407 #define PDIN_L (HWREG8_L(PDIN))
8408 #define PDOUT_H (HWREG8_H(PDOUT))
8409 #define PDOUT_L (HWREG8_L(PDOUT))
8410 #define PDREN_H (HWREG8_H(PDREN))
8411 #define PDREN_L (HWREG8_L(PDREN))
8412 #define PDSEL0_H (HWREG8_H(PDSEL0))
8413 #define PDSEL0_L (HWREG8_L(PDSEL0))
8414 #define PDSEL1_H (HWREG8_H(PDSEL1))
8415 #define PDSEL1_L (HWREG8_L(PDSEL1))
8416 #define PD_DIR (HWREG16(0x40004C64))
8417 #define PD_DS (HWREG16(0x40004C68))
8418 #define PD_IE (HWREG16(0x40004C7A))
8419 #define PD_IES (HWREG16(0x40004C78))
8420 #define PD_IFG (HWREG16(0x40004C7C))
8421 #define PD_IN (HWREG16(0x40004C60))
8422 #define PD_OUT (HWREG16(0x40004C62))
8423 #define PD_REN (HWREG16(0x40004C66))
8424 #define PD_SEL0 (HWREG16(0x40004C6A))
8425 #define PD_SEL1 (HWREG16(0x40004C6C))
8426 #define PD_SELC (HWREG16(0x40004C76))
8427 #define PEDIR_H (HWREG8_H(PEDIR))
8428 #define PEDIR_L (HWREG8_L(PEDIR))
8429 #define PEIN_H (HWREG8_H(PEIN))
8430 #define PEIN_L (HWREG8_L(PEIN))
8431 #define PEOUT_H (HWREG8_H(PEOUT))
8432 #define PEOUT_L (HWREG8_L(PEOUT))
8433 #define PERCNTSEL__0 (0x00000000)
8434 #define PERCNTSEL__1 (0x00000100)
8435 #define PEREN_H (HWREG8_H(PEREN))
8436 #define PEREN_L (HWREG8_L(PEREN))
8437 #define PESEL0_H (HWREG8_H(PESEL0))
8438 #define PESEL0_L (HWREG8_L(PESEL0))
8439 #define PESEL1_H (HWREG8_H(PESEL1))
8440 #define PESEL1_L (HWREG8_L(PESEL1))
8441 #define PE_DIR (HWREG16(0x40004C84))
8442 #define PE_DS (HWREG16(0x40004C88))
8443 #define PE_IE (HWREG16(0x40004C9A))
8444 #define PE_IES (HWREG16(0x40004C98))
8445 #define PE_IFG (HWREG16(0x40004C9C))
8446 #define PE_IN (HWREG16(0x40004C80))
8447 #define PE_OUT (HWREG16(0x40004C82))
8448 #define PE_REN (HWREG16(0x40004C86))
8449 #define PE_SEL0 (HWREG16(0x40004C8A))
8450 #define PE_SEL1 (HWREG16(0x40004C8C))
8451 #define PE_SELC (HWREG16(0x40004C96))
8452 #define PJDIR_H (HWREG8_H(PJDIR))
8453 #define PJDIR_L (HWREG8_L(PJDIR))
8454 #define PJIN_H (HWREG8_H(PJIN))
8455 #define PJIN_L (HWREG8_L(PJIN))
8456 #define PJOUT_H (HWREG8_H(PJOUT))
8457 #define PJOUT_L (HWREG8_L(PJOUT))
8458 #define PJREN_H (HWREG8_H(PJREN))
8459 #define PJREN_L (HWREG8_L(PJREN))
8460 #define PJSEL0_H (HWREG8_H(PJSEL0))
8461 #define PJSEL0_L (HWREG8_L(PJSEL0))
8462 #define PJSEL1_H (HWREG8_H(PJSEL1))
8463 #define PJSEL1_L (HWREG8_L(PJSEL1))
8464 #define PJ_DIR (HWREG16(0x40004D24))
8465 #define PJ_DS (HWREG8(0x40004D28))
8466 #define PJ_IN (HWREG16(0x40004D20))
8467 #define PJ_OUT (HWREG16(0x40004D22))
8468 #define PJ_REN (HWREG16(0x40004D26))
8469 #define PJ_SEL0 (HWREG16(0x40004D2A))
8470 #define PJ_SEL1 (HWREG16(0x40004D2C))
8471 #define PJ_SELC (HWREG16(0x40004D36))
8472 #define PMAPCTL_H (HWREG8_H(PMAPCTL))
8473 #define PMAPCTL_L (HWREG8_L(PMAPCTL))
8474 #define PMAPKEY (0x2D52)
8475 #define PMAPKEYID_H (HWREG8_H(PMAPKEYID))
8476 #define PMAPKEYID_L (HWREG8_L(PMAPKEYID))
8477 #define PMAPLOCKED_L (0x0001)
8478 #define PMAPPW (0x2D52)
8479 #define PMAPPWD (PMAPKEYID)
8480 #define PMAPRECFG_L (0x0002)
8481 #define PMAP_CTL (HWREG16(0x40005002))
8482 #define PMAP_CTL_LOCKED (0x0001)
8483 #define PMAP_CTL_LOCKED__0 (0x0000)
8484 #define PMAP_CTL_LOCKED__1 (0x0001)
8485 #define PMAP_CTL_RECFG (0x0002)
8486 #define PMAP_CTL_RECFG__0 (0x0000)
8487 #define PMAP_CTL_RECFG__1 (0x0002)
8488 #define PMAP_KEYID (HWREG16(0x40005000))
8489 #define PMAP_P1MAP0 (HWREG8(0x40005008))
8490 #define PMAP_P1MAP1 (HWREG8(0x40005009))
8491 #define PMAP_P1MAP2 (HWREG8(0x4000500A))
8492 #define PMAP_P1MAP3 (HWREG8(0x4000500B))
8493 #define PMAP_P1MAP4 (HWREG8(0x4000500C))
8494 #define PMAP_P1MAP5 (HWREG8(0x4000500D))
8495 #define PMAP_P1MAP6 (HWREG8(0x4000500E))
8496 #define PMAP_P1MAP7 (HWREG8(0x4000500F))
8497 #define PMAP_P2MAP0 (HWREG8(0x40005010))
8498 #define PMAP_P2MAP1 (HWREG8(0x40005011))
8499 #define PMAP_P2MAP2 (HWREG8(0x40005012))
8500 #define PMAP_P2MAP3 (HWREG8(0x40005013))
8501 #define PMAP_P2MAP4 (HWREG8(0x40005014))
8502 #define PMAP_P2MAP5 (HWREG8(0x40005015))
8503 #define PMAP_P2MAP6 (HWREG8(0x40005016))
8504 #define PMAP_P2MAP7 (HWREG8(0x40005017))
8505 #define PMAP_P3MAP0 (HWREG8(0x40005018))
8506 #define PMAP_P3MAP1 (HWREG8(0x40005019))
8507 #define PMAP_P3MAP2 (HWREG8(0x4000501A))
8508 #define PMAP_P3MAP3 (HWREG8(0x4000501B))
8509 #define PMAP_P3MAP4 (HWREG8(0x4000501C))
8510 #define PMAP_P3MAP5 (HWREG8(0x4000501D))
8511 #define PMAP_P3MAP6 (HWREG8(0x4000501E))
8512 #define PMAP_P3MAP7 (HWREG8(0x4000501F))
8513 #define PMAP_P4MAP0 (HWREG8(0x40005020))
8514 #define PMAP_P4MAP1 (HWREG8(0x40005021))
8515 #define PMAP_P4MAP2 (HWREG8(0x40005022))
8516 #define PMAP_P4MAP3 (HWREG8(0x40005023))
8517 #define PMAP_P4MAP4 (HWREG8(0x40005024))
8518 #define PMAP_P4MAP5 (HWREG8(0x40005025))
8519 #define PMAP_P4MAP6 (HWREG8(0x40005026))
8520 #define PMAP_P4MAP7 (HWREG8(0x40005027))
8521 #define PMAP_P5MAP0 (HWREG8(0x40005028))
8522 #define PMAP_P5MAP1 (HWREG8(0x40005029))
8523 #define PMAP_P5MAP2 (HWREG8(0x4000502A))
8524 #define PMAP_P5MAP3 (HWREG8(0x4000502B))
8525 #define PMAP_P5MAP4 (HWREG8(0x4000502C))
8526 #define PMAP_P5MAP5 (HWREG8(0x4000502D))
8527 #define PMAP_P5MAP6 (HWREG8(0x4000502E))
8528 #define PMAP_P5MAP7 (HWREG8(0x4000502F))
8529 #define PMAP_P6MAP0 (HWREG8(0x40005030))
8530 #define PMAP_P6MAP1 (HWREG8(0x40005031))
8531 #define PMAP_P6MAP2 (HWREG8(0x40005032))
8532 #define PMAP_P6MAP3 (HWREG8(0x40005033))
8533 #define PMAP_P6MAP4 (HWREG8(0x40005034))
8534 #define PMAP_P6MAP5 (HWREG8(0x40005035))
8535 #define PMAP_P6MAP6 (HWREG8(0x40005036))
8536 #define PMAP_P6MAP7 (HWREG8(0x40005037))
8537 #define PMAP_P7MAP0 (HWREG8(0x40005038))
8538 #define PMAP_P7MAP1 (HWREG8(0x40005039))
8539 #define PMAP_P7MAP2 (HWREG8(0x4000503A))
8540 #define PMAP_P7MAP3 (HWREG8(0x4000503B))
8541 #define PMAP_P7MAP4 (HWREG8(0x4000503C))
8542 #define PMAP_P7MAP5 (HWREG8(0x4000503D))
8543 #define PMAP_P7MAP6 (HWREG8(0x4000503E))
8544 #define PMAP_P7MAP7 (HWREG8(0x4000503F))
8545 #define PSS_CLRIFG (HWREG32(0x4001083C))
8546 #define PSS_CLRIFG_CLRSVSLVLRIFG (0x00000001)
8547 #define PSS_CLRIFG_CLRSVSLVLRIFG__0 (0x00000000)
8548 #define PSS_CLRIFG_CLRSVSLVLRIFG__0_NO_EFFECT (0x00000000)
8549 #define PSS_CLRIFG_CLRSVSLVLRIFG__1 (0x00000001)
8550 #define PSS_CLRIFG_CLRSVSMHIFG (0x00000002)
8551 #define PSS_CLRIFG_CLRSVSMHIFG__0 (0x00000000)
8552 #define PSS_CLRIFG_CLRSVSMHIFG__0_NO_EFFECT (0x00000000)
8553 #define PSS_CLRIFG_CLRSVSMHIFG__1 (0x00000002)
8554 #define PSS_DCDCCNFG1 (HWREG32(0x40010B20))
8555 #define PSS_DCDCCNFG2 (HWREG32(0x40010B24))
8556 #define PSS_DCDCCNFG3 (HWREG32(0x40010B28))
8557 #define PSS_DFTATBBF (HWREG32(0x40010F28))
8558 #define PSS_DFTATBBF_ATBBFDCDC (0x00000002)
8559 #define PSS_DFTATBBF_ATBBFFLSH (0x00000004)
8560 #define PSS_DFTATBBF_ATBBFGEN (0x00000001)
8561 #define PSS_DFTATBBF_BG0P6SNSBF (0x00800000)
8562 #define PSS_DFTATBBF_BG1P2SNSBF (0x00400000)
8563 #define PSS_DFTATBBF_BGINTSNSBF (0x00008000)
8564 #define PSS_DFTATBBF_BUFCALBF (0x00000008)
8565 #define PSS_DFTATBBF_LDOINTSNSBF (0x00000010)
8566 #define PSS_DFTATBBF_PRERF0P6SNSBF (0x00080000)
8567 #define PSS_DFTATBBF_PRERFVCSNSBF (0x00200000)
8568 #define PSS_DFTATBBF_RF0P6SNSBF (0x80000000)
8569 #define PSS_DFTATBBF_RFVCSNSBF (0x40000000)
8570 #define PSS_DFTATBBF_UNUSED__M (0x00007fe0)
8571 #define PSS_DFTATBUBF (HWREG32(0x40010F2C))
8572 #define PSS_DFTATBUBF_ATBUBFDCDC (0x00000002)
8573 #define PSS_DFTATBUBF_ATBUBFFLSH (0x00000004)
8574 #define PSS_DFTATBUBF_ATBUBFGEN (0x00000001)
8575 #define PSS_DFTATBUBF_BG0P6SNSUBF (0x00800000)
8576 #define PSS_DFTATBUBF_BG1P2SNSUBF (0x00400000)
8577 #define PSS_DFTATBUBF_BGINTSNSUBF (0x00008000)
8578 #define PSS_DFTATBUBF_BUFCALUBF (0x00000008)
8579 #define PSS_DFTATBUBF_DBGLDOCT0 (0x20000000)
8580 #define PSS_DFTATBUBF_DBGLDOCT1 (0x40000000)
8581 #define PSS_DFTATBUBF_DBGLDOCT2 (0x80000000)
8582 #define PSS_DFTATBUBF_LDOINTSNSUBF (0x00000010)
8583 #define PSS_DFTATBUBF_PRERF0P6SNSUBF (0x00080000)
8584 #define PSS_DFTATBUBF_PRERFVCSNSUBF (0x00200000)
8585 #define PSS_DFTATBUBF_REFCTFRC (0x00004000)
8586 #define PSS_DFTATBUBF_REFGNDSNS (0x00001000)
8587 #define PSS_DFTATBUBF_SVSLIPFRC (0x00000400)
8588 #define PSS_DFTATBUBF_SVSLVCCDIVSNS (0x00000200)
8589 #define PSS_DFTATBUBF_SVSMHIPFRC (0x00002000)
8590 #define PSS_DFTATBUBF_SVSMHVCCDIVSNS (0x00000800)
8591 #define PSS_DFTATBUBF_UNUSED__M (0x000001e0)
8592 #define PSS_DFTCNFG (HWREG32(0x40010F10))
8593 #define PSS_DFTCNFG_LOCAL_TP0_MUX_SEL__M (0x000f0000)
8594 #define PSS_DFTCNFG_LOCAL_TP1_MUX_SEL__M (0x00f00000)
8595 #define PSS_DFTCNFG_LOCAL_TP2_MUX_SEL__M (0x0f000000)
8596 #define PSS_DFTCNFG_LOCAL_TP3_MUX_SEL__M (0xf0000000)
8597 #define PSS_DFTCTRL1 (HWREG32(0x40010F20))
8598 #define PSS_DFTCTRL1_BG_DIS (0x40000000)
8599 #define PSS_DFTCTRL1_CORE_LPM_LDO_DIS (0x00800000)
8600 #define PSS_DFTCTRL1_CORE_LPM_LDO_NO_HIZ_EN (0x04000000)
8601 #define PSS_DFTCTRL1_DCDC_EN (0x00400000)
8602 #define PSS_DFTCTRL1_DCDC_MNK_COMP_EN (0x00200000)
8603 #define PSS_DFTCTRL1_DCDC_TRISTATE_DIS (0x00100000)
8604 #define PSS_DFTCTRL1_DFT_MODE (0x80000000)
8605 #define PSS_DFTCTRL1_DIS_DFT_FL_IREF (0x00000010)
8606 #define PSS_DFTCTRL1_DIS_DFT_FL_LDO (0x00000004)
8607 #define PSS_DFTCTRL1_DIS_DFT_FL_VREF (0x00000008)
8608 #define PSS_DFTCTRL1_DIS_DFT_RHS (0x00000001)
8609 #define PSS_DFTCTRL1_DIS_DFT_RLS (0x00000002)
8610 #define PSS_DFTCTRL1_FLASH_IREF_DIS (0x00002000)
8611 #define PSS_DFTCTRL1_FLASH_LDO_DIS (0x00010000)
8612 #define PSS_DFTCTRL1_FLASH_LDO_TRISTATE_EN (0x00004000)
8613 #define PSS_DFTCTRL1_FLASH_LPM_LDO_EN (0x00008000)
8614 #define PSS_DFTCTRL1_FLASH_VREF_DIS (0x00001000)
8615 #define PSS_DFTCTRL1_LONG_DLY_REQ (0x00000200)
8616 #define PSS_DFTCTRL1_LPM_FAST_OSC_EN (0x00000800)
8617 #define PSS_DFTCTRL1_LPM_SLOW_OSC_EN (0x00000400)
8618 #define PSS_DFTCTRL1_REF_LPM_EN (0x00080000)
8619 #define PSS_DFTCTRL1_REF_SMPL_DIS (0x00040000)
8620 #define PSS_DFTCTRL1_REF_STDBY_EN (0x00020000)
8621 #define PSS_DFTCTRL1_SHORT_DLY_REQ (0x00000100)
8622 #define PSS_DFTCTRL1_SVSL_DIS (0x02000000)
8623 #define PSS_DFTCTRL1_SVSL_LPM_EN (0x01000000)
8624 #define PSS_DFTCTRL1_SVSMH_DIS (0x20000000)
8625 #define PSS_DFTCTRL1_SVSMH_LPM_EN (0x10000000)
8626 #define PSS_DFTCTRL1_VCORE_LDO_DIS (0x08000000)
8627 #define PSS_DFTCTRL2 (HWREG32(0x40010F24))
8628 #define PSS_DFTCTRL2_BG_MOD_OVRDE (0x00010000)
8629 #define PSS_DFTCTRL2_DCDC_BIAS_RDY_OVRDE (0x02000000)
8630 #define PSS_DFTCTRL2_FLASH_IREF_BIAS_RDY_OVRDE (0x00040000)
8631 #define PSS_DFTCTRL2_FLASH_LDO_BIAS_RDY_OVRDE (0x00100000)
8632 #define PSS_DFTCTRL2_FLASH_LDO_PGOOD_OVRDE (0x00080000)
8633 #define PSS_DFTCTRL2_FLASH_VREF_BIAS_RDY_OVRDE (0x00020000)
8634 #define PSS_DFTCTRL2_LDO_BIAS_RDY_OVRDE (0x10000000)
8635 #define PSS_DFTCTRL2_LDO_LPM_BIAS_RDY_OVRDE (0x04000000)
8636 #define PSS_DFTCTRL2_MNK_COMP_OK_OVRDE (0x00200000)
8637 #define PSS_DFTCTRL2_REF_OK_OVRDE (0x80000000)
8638 #define PSS_DFTCTRL2_SVSL_BIAS_RDY_OVRDE (0x00400000)
8639 #define PSS_DFTCTRL2_SVSMH_BIAS_RDY_OVRDE (0x40000000)
8640 #define PSS_DFTCTRL2_SVSMH_LP_OVRDE (0x00008000)
8641 #define PSS_DFTCTRL2_SVS_LP_OVRDE (0x00004000)
8642 #define PSS_DFTCTRL2_TRIM_DONE_OVRDE (0x00800000)
8643 #define PSS_DFTCTRL2_TRIM_SET_OVRDE (0x01000000)
8644 #define PSS_DFTCTRL2_VCC_OK_OVRDE (0x20000000)
8645 #define PSS_DFTCTRL2_VCORE_OK_OVRDE (0x08000000)
8646 #define PSS_DOCMCTL (HWREG32(0x40010808))
8647 #define PSS_DOCMCTL_DOCMCM__0 (0x00000000)
8648 #define PSS_DOCMCTL_DOCMCM__0_TBD (0x00000000)
8649 #define PSS_DOCMCTL_DOCMCM__1 (0x00000008)
8650 #define PSS_DOCMCTL_DOCMCM__1_TBD (0x00000008)
8651 #define PSS_DOCMCTL_DOCMCM__M (0x000001f8)
8652 #define PSS_DOCMCTL_DOCMON (0x00000001)
8653 #define PSS_DOCMCTL_DOCMON__0 (0x00000000)
8654 #define PSS_DOCMCTL_DOCMON__0_DISABLE_DOCM (0x00000000)
8655 #define PSS_DOCMCTL_DOCMON__1 (0x00000001)
8656 #define PSS_DOCMCTL_DOCMON__1_ENABLE_DOCM (0x00000001)
8657 #define PSS_DOCMCTL_DOCMSAMP (0x00000002)
8658 #define PSS_DOCMCTL_DOCMSAMP__0 (0x00000000)
8659 #define PSS_DOCMCTL_DOCMSAMP__1 (0x00000002)
8660 #define PSS_DOCMOUTR (HWREG32(0x4001080C))
8661 #define PSS_DOCMOUTR_DOCMOUT__M (0x0000003f)
8662 #define PSS_FLSHCNFG0 (HWREG32(0x40010B0C))
8663 #define PSS_FLSHCNFG1 (HWREG32(0x40010B10))
8664 #define PSS_FLSHCNFG1_FLLDOCNFG__M (0xffff0000)
8665 #define PSS_FLSHCNFG1_FLLDOPRG__M (0x00000f00)
8666 #define PSS_FLSHCNFG1_IREFFLTREN (0x00000080)
8667 #define PSS_FLSHCNFG1_IRFFLCNFG__M (0x00000070)
8668 #define PSS_FLSHCNFG1_VRFFLCNFG__M (0x0000000f)
8669 #define PSS_IE (HWREG32(0x40010834))
8670 #define PSS_IE_SVSLVLRIE (0x00000001)
8671 #define PSS_IE_SVSLVLRIE__0 (0x00000000)
8672 #define PSS_IE_SVSLVLRIE__1 (0x00000001)
8673 #define PSS_IE_SVSMHIE (0x00000002)
8674 #define PSS_IE_SVSMHIE__0 (0x00000000)
8675 #define PSS_IE_SVSMHIE__1 (0x00000002)
8676 #define PSS_IFG (HWREG32(0x40010838))
8677 #define PSS_IFG_SVSLVLRIFG (0x00000001)
8678 #define PSS_IFG_SVSLVLRIFG__0 (0x00000000)
8679 #define PSS_IFG_SVSLVLRIFG__1 (0x00000001)
8680 #define PSS_IFG_SVSMHIFG (0x00000002)
8681 #define PSS_IFG_SVSMHIFG__0 (0x00000000)
8682 #define PSS_IFG_SVSMHIFG__1 (0x00000002)
8683 #define PSS_KEY (HWREG32(0x40010800))
8684 #define PSS_KEY_KEY__M (0x0000ffff)
8685 #define PSS_MISCCNFG (HWREG32(0x40010B14))
8686 #define PSS_OPTEOP (HWREG32(0x40010B3C))
8687 #define PSS_OSDLCNFG (HWREG32(0x40010B1C))
8688 #define PSS_REFTRIM1 (HWREG32(0x40010B00))
8689 #define PSS_REFTRIM2 (HWREG32(0x40010B04))
8690 #define PSS_RSTFLG (HWREG32(0x40010B30))
8691 #define PSS_SHCTR (HWREG32(0x40010B2C))
8692 #define PSS_SVSCNFG (HWREG32(0x40010B08))
8693 #define PSS_SVSMCTL (HWREG32(0x40010804))
8694 #define PSS_SVSMCTL_DCDC_FORCE (0x00000400)
8695 #define PSS_SVSMCTL_DCDC_FORCE__0 (0x00000000)
8696 #define PSS_SVSMCTL_DCDC_FORCE__1 (0x00000400)
8697 #define PSS_SVSMCTL_SVMHOE (0x00000040)
8698 #define PSS_SVSMCTL_SVMHOE__0 (0x00000000)
8699 #define PSS_SVSMCTL_SVMHOE__1 (0x00000040)
8700 #define PSS_SVSMCTL_SVMHOUTPOLAL (0x00000080)
8701 #define PSS_SVSMCTL_SVMHOUTPOLAL__0 (0x00000000)
8702 #define PSS_SVSMCTL_SVMHOUTPOLAL__1 (0x00000080)
8703 #define PSS_SVSMCTL_SVSLLP (0x00000200)
8704 #define PSS_SVSMCTL_SVSLLP__0 (0x00000000)
8705 #define PSS_SVSMCTL_SVSLLP__1 (0x00000200)
8706 #define PSS_SVSMCTL_SVSLOFF (0x00000100)
8707 #define PSS_SVSMCTL_SVSLOFF__0 (0x00000000)
8708 #define PSS_SVSMCTL_SVSLOFF__0_THE_SVSL_IS_ON (0x00000000)
8709 #define PSS_SVSMCTL_SVSLOFF__1 (0x00000100)
8710 #define PSS_SVSMCTL_SVSLOFF__1_THE_SVSL_IS_OFF (0x00000100)
8711 #define PSS_SVSMCTL_SVSMHLP (0x00000002)
8712 #define PSS_SVSMCTL_SVSMHLP__0 (0x00000000)
8713 #define PSS_SVSMCTL_SVSMHLP__1 (0x00000002)
8714 #define PSS_SVSMCTL_SVSMHOFF (0x00000001)
8715 #define PSS_SVSMCTL_SVSMHOFF__0 (0x00000000)
8716 #define PSS_SVSMCTL_SVSMHOFF__0_THE_SVSMH_IS_ON (0x00000000)
8717 #define PSS_SVSMCTL_SVSMHOFF__1 (0x00000001)
8718 #define PSS_SVSMCTL_SVSMHS (0x00000004)
8719 #define PSS_SVSMCTL_SVSMHS__0 (0x00000000)
8720 #define PSS_SVSMCTL_SVSMHS__1 (0x00000004)
8721 #define PSS_SVSMCTL_SVSMHTH__M (0x00000038)
8722 #define PSS_SVSMHTH01 (HWREG32(0x40010F00))
8723 #define PSS_SVSMHTH23 (HWREG32(0x40010F04))
8724 #define PSS_SVSMHTH45 (HWREG32(0x40010F08))
8725 #define PSS_SVSMHTH67 (HWREG32(0x40010F0C))
8726 #define PSS_VCOREPROG (HWREG32(0x40010B18))
8727 #define REFBGACT_H (0x0002)
8728 #define REFBGOT_L (0x0080)
8729 #define REFBGRDY_H (0x0020)
8730 #define REFCNTPS__0 (0x00000000)
8731 #define REFCNTPS__1 (0x00000008)
8732 #define REFCNTPS__2 (0x00000010)
8733 #define REFCNTPS__3 (0x00000018)
8734 #define REFCNTPS__4 (0x00000020)
8735 #define REFCNTPS__5 (0x00000028)
8736 #define REFCNTPS__6 (0x00000030)
8737 #define REFCNTPS__7 (0x00000038)
8738 #define REFCNTSEL__0 (0x00000000)
8739 #define REFCNTSEL__1 (0x00000001)
8740 #define REFCNTSEL__2 (0x00000002)
8741 #define REFCNTSEL__3 (0x00000003)
8742 #define REFGENACT_H (0x0001)
8743 #define REFGENBUSY_H (0x0004)
8744 #define REFGENOT_L (0x0040)
8745 #define REFGENRDY_H (0x0010)
8746 #define REFON_L (0x0001)
8747 #define REFOUT_L (0x0002)
8748 #define REFTCOFF_L (0x0008)
8749 #define REFVSEL0 (0x0010)
8750 #define REFVSEL0_L (0x0010)
8751 #define REFVSEL1 (0x0020)
8752 #define REFVSEL1_L (0x0020)
8753 #define REFVSEL_2 (0x0020)
8754 #define REF_A_CTL0 (HWREG16(0x40003000))
8755 #define REF_A_CTL0_BGACT (0x0200)
8756 #define REF_A_CTL0_BGACT__0 (0x0000)
8757 #define REF_A_CTL0_BGACT__1 (0x0200)
8758 #define REF_A_CTL0_BGMODE (0x0800)
8759 #define REF_A_CTL0_BGMODE__0 (0x0000)
8760 #define REF_A_CTL0_BGMODE__0_STATIC_MODE (0x0000)
8761 #define REF_A_CTL0_BGMODE__1 (0x0800)
8762 #define REF_A_CTL0_BGMODE__1_SAMPLED_MODE (0x0800)
8763 #define REF_A_CTL0_BGOT (0x0080)
8764 #define REF_A_CTL0_BGOT__0 (0x0000)
8765 #define REF_A_CTL0_BGOT__0_NO_TRIGGER (0x0000)
8766 #define REF_A_CTL0_BGOT__1 (0x0080)
8767 #define REF_A_CTL0_BGRDY (0x2000)
8768 #define REF_A_CTL0_BGRDY__0 (0x0000)
8769 #define REF_A_CTL0_BGRDY__1 (0x2000)
8770 #define REF_A_CTL0_GENACT (0x0100)
8771 #define REF_A_CTL0_GENACT__0 (0x0000)
8772 #define REF_A_CTL0_GENACT__1 (0x0100)
8773 #define REF_A_CTL0_GENBUSY (0x0400)
8774 #define REF_A_CTL0_GENBUSY__0 (0x0000)
8775 #define REF_A_CTL0_GENBUSY__1 (0x0400)
8776 #define REF_A_CTL0_GENOT (0x0040)
8777 #define REF_A_CTL0_GENOT__0 (0x0000)
8778 #define REF_A_CTL0_GENOT__0_NO_TRIGGER (0x0000)
8779 #define REF_A_CTL0_GENOT__1 (0x0040)
8780 #define REF_A_CTL0_GENRDY (0x1000)
8781 #define REF_A_CTL0_GENRDY__0 (0x0000)
8782 #define REF_A_CTL0_GENRDY__1 (0x1000)
8783 #define REF_A_CTL0_ON (0x0001)
8784 #define REF_A_CTL0_ON__0 (0x0000)
8785 #define REF_A_CTL0_ON__1 (0x0001)
8786 #define REF_A_CTL0_OUT (0x0002)
8787 #define REF_A_CTL0_OUT__0 (0x0000)
8788 #define REF_A_CTL0_OUT__1 (0x0002)
8789 #define REF_A_CTL0_TCOFF (0x0008)
8790 #define REF_A_CTL0_TCOFF__0 (0x0000)
8791 #define REF_A_CTL0_TCOFF__1 (0x0008)
8792 #define REF_A_CTL0_VSEL__0 (0x0000)
8793 #define REF_A_CTL0_VSEL__1 (0x0010)
8794 #define REF_A_CTL0_VSEL__3 (0x0030)
8795 #define REF_A_CTL0_VSEL__M (0x0030)
8796 #define RSTCTL_RESETREQ_RSTKEY__M (0x0000ff00)
8797 #define RT0IP0 (0x0004)
8798 #define RT0IP0_L (0x00000004)
8799 #define RT0IP1 (0x0008)
8800 #define RT0IP1_L (0x00000008)
8801 #define RT0IP2 (0x0010)
8802 #define RT0IP2_L (0x00000010)
8803 #define RT0PSDIV0 (0x0800)
8804 #define RT0PSDIV0_H (0x00000008)
8805 #define RT0PSDIV1 (0x1000)
8806 #define RT0PSDIV1_H (0x00000010)
8807 #define RT0PSDIV2 (0x2000)
8808 #define RT0PSDIV2_H (0x00000020)
8809 #define RT0PSHOLD (0x0100)
8810 #define RT0PSHOLD_H (0x00000001)
8811 #define RT0PSIE_L (0x00000002)
8812 #define RT0PSIFG_L (0x00000001)
8813 #define RT1IP0 (0x0004)
8814 #define RT1IP0_L (0x00000004)
8815 #define RT1IP1 (0x0008)
8816 #define RT1IP1_L (0x00000008)
8817 #define RT1IP2 (0x0010)
8818 #define RT1IP2_L (0x00000010)
8819 #define RT1PSDIV0 (0x0800)
8820 #define RT1PSDIV0_H (0x00000008)
8821 #define RT1PSDIV1 (0x1000)
8822 #define RT1PSDIV1_H (0x00000010)
8823 #define RT1PSDIV2 (0x2000)
8824 #define RT1PSDIV2_H (0x00000020)
8825 #define RT1PSHOLD (0x0100)
8826 #define RT1PSHOLD_H (0x00000001)
8827 #define RT1PSIE_L (0x00000002)
8828 #define RT1PSIFG_L (0x00000001)
8829 #define RT1SSEL0 (0x4000)
8830 #define RT1SSEL0_H (0x00000040)
8831 #define RT1SSEL1 (0x8000)
8832 #define RT1SSEL1_H (0x00000080)
8833 #define RTCAIE_L (0x00000020)
8834 #define RTCAIFG_L (0x00000002)
8835 #define RTCBCD_L (0x00000080)
8836 #define RTCCALF0 (0x0100)
8837 #define RTCCALF0_H (0x00000001)
8838 #define RTCCALF1 (0x0200)
8839 #define RTCCALF1_H (0x00000002)
8840 #define RTCCAP0CTL (RTC_CAP0CTL)
8841 #define RTCCAP1CTL (RTC_CAP1CTL)
8842 #define RTCCAPDIR (0x0020)
8843 #define RTCCAPIE (0x0002)
8844 #define RTCCAPIFG (0x0001)
8845 #define RTCCAPIN (0x0010)
8846 #define RTCCAPOUT (0x0040)
8847 #define RTCDAYBAK0 (RTC_DAYBAK0)
8848 #define RTCDAYBAK1 (RTC_DAYBAK1)
8849 #define RTCHOLD_L (0x00000040)
8850 #define RTCHOURBAK0 (RTC_HOURBAK0)
8851 #define RTCHOURBAK1 (RTC_HOURBAK1)
8852 #define RTCIV_NONE (0x0000)
8853 #define RTCIV_RT0PSIFG (0x000C)
8854 #define RTCIV_RT1PSIFG (0x000E)
8855 #define RTCIV_RTCAIFG (0x000A)
8856 #define RTCIV_RTCCAPIFG (0x0004)
8857 #define RTCIV_RTCOFIFG (0x0002)
8858 #define RTCIV_RTCRDYIFG (0x0006)
8859 #define RTCIV_RTCTEVIFG (0x0008)
8860 #define RTCKEY (0xA500)
8861 #define RTCKEY_H (0xA5)
8862 #define RTCKEY_VAL (0xA500)
8863 #define RTCMINBAK0 (RTC_MINBAK0)
8864 #define RTCMINBAK1 (RTC_MINBAK1)
8865 #define RTCMODE_L (0x00000020)
8866 #define RTCMONBAK0 (RTC_MONBAK0)
8867 #define RTCMONBAK1 (RTC_MONBAK1)
8868 #define RTCOCAL0 (0x0001)
8869 #define RTCOCAL0_L (0x00000001)
8870 #define RTCOCAL1 (0x0002)
8871 #define RTCOCAL1_L (0x00000002)
8872 #define RTCOCAL2 (0x0004)
8873 #define RTCOCAL2_L (0x00000004)
8874 #define RTCOCAL3 (0x0008)
8875 #define RTCOCAL3_L (0x00000008)
8876 #define RTCOCAL4 (0x0010)
8877 #define RTCOCAL4_L (0x00000010)
8878 #define RTCOCAL5 (0x0020)
8879 #define RTCOCAL5_L (0x00000020)
8880 #define RTCOCAL6 (0x0040)
8881 #define RTCOCAL6_L (0x00000040)
8882 #define RTCOCAL7 (0x0080)
8883 #define RTCOCAL7_L (0x00000080)
8884 #define RTCOCALS_H (0x00000080)
8885 #define RTCOFIE_L (0x00000080)
8886 #define RTCOFIFG_L (0x00000008)
8887 #define RTCRDYIE_L (0x00000010)
8888 #define RTCRDYIFG_L (0x00000001)
8889 #define RTCRDY_L (0x00000010)
8890 #define RTCREN (0x0008)
8891 #define RTCSECBAK0 (RTC_SECBAK0)
8892 #define RTCSECBAK1 (RTC_SECBAK1)
8893 #define RTCSSEL0 (0x0004)
8894 #define RTCSSEL0_L (0x00000004)
8895 #define RTCSSEL1 (0x0008)
8896 #define RTCSSEL1_L (0x00000008)
8897 #define RTCSSEL_1 (0x0004)
8898 #define RTCSSEL_2 (0x0008)
8899 #define RTCSSEL_3 (0x000C)
8900 #define RTCSSEL_ACLK (0x0000)
8901 #define RTCSSEL_RT1PS (0x0008)
8902 #define RTCSSEL_SMCLK (0x0004)
8903 #define RTCTCCTL0 (RTC_TCCTL0)
8904 #define RTCTCCTL1 (RTC_TCCTL1)
8905 #define RTCTCMP0 (0x0001)
8906 #define RTCTCMP0_L (0x00000001)
8907 #define RTCTCMP1 (0x0002)
8908 #define RTCTCMP1_L (0x00000002)
8909 #define RTCTCMP2 (0x0004)
8910 #define RTCTCMP2_L (0x00000004)
8911 #define RTCTCMP3 (0x0008)
8912 #define RTCTCMP3_L (0x00000008)
8913 #define RTCTCMP4 (0x0010)
8914 #define RTCTCMP4_L (0x00000010)
8915 #define RTCTCMP5 (0x0020)
8916 #define RTCTCMP5_L (0x00000020)
8917 #define RTCTCMP6 (0x0040)
8918 #define RTCTCMP6_L (0x00000040)
8919 #define RTCTCMP7 (0x0080)
8920 #define RTCTCMP7_L (0x00000080)
8921 #define RTCTCMPS_H (0x00000080)
8922 #define RTCTCOK_H (0x00000020)
8923 #define RTCTCRDY_H (0x00000040)
8924 #define RTCTEV0 (0x0001)
8925 #define RTCTEV0_L (0x00000001)
8926 #define RTCTEV1 (0x0002)
8927 #define RTCTEV1_L (0x00000002)
8928 #define RTCTEVIE_L (0x00000040)
8929 #define RTCTEVIFG_L (0x00000004)
8930 #define RTCTEV_0000 (0x0002)
8931 #define RTCTEV_1200 (0x0003)
8932 #define RTCTEV_HOUR (0x0001)
8933 #define RTCTEV_MIN (0x0000)
8934 #define RTCYEARBAK0 (RTC_YEARBAK0)
8935 #define RTCYEARBAK1 (RTC_YEARBAK1)
8936 #define RTCYEAR_H (HWREG8_H(RTCYEAR))
8937 #define RTCYEAR_L (HWREG8_L(RTCYEAR))
8938 #define RTC_CTL0_KEY_VAL (0xA500)
8940 #define RTC_C_ADAY_AE (0x0080)
8941 #define RTC_C_ADAY_DAY_OF_MONTH__M (0x001f)
8943 #define RTC_C_ADOW_AE (0x0080)
8944 #define RTC_C_ADOW_DAY_OF_WEEK__M (0x0007)
8946 #define RTC_C_AHOUR_AE (0x0080)
8947 #define RTC_C_AHOUR_HOURS__M (0x001f)
8949 #define RTC_C_AMIN_AE (0x0080)
8950 #define RTC_C_AMIN_MINUTES__M (0x003f)
8951 #define RTC_C_BCD2BIN (HWREG16(0x4000441E))
8952 #define RTC_C_BIN2BCD (HWREG16(0x4000441C))
8953 #define RTC_C_CTL0 (HWREG16(0x40004400))
8954 #define RTC_C_CTL0_AIE (0x0020)
8955 #define RTC_C_CTL0_AIE__0 (0x0000)
8956 #define RTC_C_CTL0_AIE__1 (0x0020)
8957 #define RTC_C_CTL0_AIFG (0x0002)
8958 #define RTC_C_CTL0_AIFG__0 (0x0000)
8959 #define RTC_C_CTL0_AIFG__1 (0x0002)
8960 #define RTC_C_CTL0_KEY__M (0xff00)
8961 #define RTC_C_CTL0_OFIE (0x0080)
8962 #define RTC_C_CTL0_OFIE__0 (0x0000)
8963 #define RTC_C_CTL0_OFIE__1 (0x0080)
8964 #define RTC_C_CTL0_OFIFG (0x0008)
8965 #define RTC_C_CTL0_OFIFG__0 (0x0000)
8966 #define RTC_C_CTL0_OFIFG__1 (0x0008)
8967 #define RTC_C_CTL0_RDYIE (0x0010)
8968 #define RTC_C_CTL0_RDYIE__0 (0x0000)
8969 #define RTC_C_CTL0_RDYIE__1 (0x0010)
8970 #define RTC_C_CTL0_RDYIFG (0x0001)
8971 #define RTC_C_CTL0_RDYIFG__0 (0x0000)
8972 #define RTC_C_CTL0_RDYIFG__1 (0x0001)
8973 #define RTC_C_CTL0_TEVIE (0x0040)
8974 #define RTC_C_CTL0_TEVIE__0 (0x0000)
8975 #define RTC_C_CTL0_TEVIE__1 (0x0040)
8976 #define RTC_C_CTL0_TEVIFG (0x0004)
8977 #define RTC_C_CTL0_TEVIFG__0 (0x0000)
8978 #define RTC_C_CTL0_TEVIFG__1 (0x0004)
8980 #define RTC_C_CTL1_BCD (0x0080)
8981 #define RTC_C_CTL1_BCD__0 (0x0000)
8982 #define RTC_C_CTL1_BCD__1 (0x0080)
8983 #define RTC_C_CTL1_HOLD (0x0040)
8984 #define RTC_C_CTL1_HOLD__0 (0x0000)
8985 #define RTC_C_CTL1_HOLD__1 (0x0040)
8986 #define RTC_C_CTL1_MODE (0x0020)
8987 #define RTC_C_CTL1_MODE__1 (0x0020)
8988 #define RTC_C_CTL1_RDY (0x0010)
8989 #define RTC_C_CTL1_RDY__0 (0x0000)
8990 #define RTC_C_CTL1_RDY__1 (0x0010)
8991 #define RTC_C_CTL1_SSEL__0 (0x0000)
8992 #define RTC_C_CTL1_SSEL__0_BCLK (0x0000)
8993 #define RTC_C_CTL1_SSEL__1 (0x0004)
8994 #define RTC_C_CTL1_SSEL__2 (0x0008)
8995 #define RTC_C_CTL1_SSEL__3 (0x000c)
8996 #define RTC_C_CTL1_SSEL__M (0x000c)
8997 #define RTC_C_CTL1_TEV__M (0x0003)
8999 #define RTC_C_CTL3_CALF__0 (0x0000)
9000 #define RTC_C_CTL3_CALF__1 (0x0001)
9001 #define RTC_C_CTL3_CALF__1_512_HZ (0x0001)
9002 #define RTC_C_CTL3_CALF__2 (0x0002)
9003 #define RTC_C_CTL3_CALF__2_256_HZ (0x0002)
9004 #define RTC_C_CTL3_CALF__3 (0x0003)
9005 #define RTC_C_CTL3_CALF__3_1_HZ (0x0003)
9006 #define RTC_C_CTL3_CALF__M (0x0003)
9008 #define RTC_C_DAY_DAY_OF_MONTH__M (0x001f)
9010 #define RTC_C_DOW_DAY_OF_WEEK__M (0x0007)
9012 #define RTC_C_HOUR_HOURS__M (0x001f)
9013 #define RTC_C_IV (HWREG16(0x4000440E))
9015 #define RTC_C_MIN_MINUTES__M (0x003f)
9017 #define RTC_C_MON_MONTH__M (0x000f)
9018 #define RTC_C_OCAL (HWREG16(0x40004404))
9019 #define RTC_C_OCAL_OCALS (0x8000)
9020 #define RTC_C_OCAL_OCALS__0 (0x0000)
9021 #define RTC_C_OCAL_OCALS__1 (0x8000)
9022 #define RTC_C_OCAL_OCAL__M (0x00ff)
9023 #define RTC_C_PS0 (HWREG8(0x4000440C))
9024 #define RTC_C_PS0CTL (HWREG16(0x40004408))
9025 #define RTC_C_PS0CTL_RT0IP__0 (0x0000)
9026 #define RTC_C_PS0CTL_RT0IP__0_DIVIDE_BY_2 (0x0000)
9027 #define RTC_C_PS0CTL_RT0IP__1 (0x0004)
9028 #define RTC_C_PS0CTL_RT0IP__1_DIVIDE_BY_4 (0x0004)
9029 #define RTC_C_PS0CTL_RT0IP__2 (0x0008)
9030 #define RTC_C_PS0CTL_RT0IP__2_DIVIDE_BY_8 (0x0008)
9031 #define RTC_C_PS0CTL_RT0IP__3 (0x000c)
9032 #define RTC_C_PS0CTL_RT0IP__3_DIVIDE_BY_16 (0x000c)
9033 #define RTC_C_PS0CTL_RT0IP__4 (0x0010)
9034 #define RTC_C_PS0CTL_RT0IP__4_DIVIDE_BY_32 (0x0010)
9035 #define RTC_C_PS0CTL_RT0IP__5 (0x0014)
9036 #define RTC_C_PS0CTL_RT0IP__5_DIVIDE_BY_64 (0x0014)
9037 #define RTC_C_PS0CTL_RT0IP__6 (0x0018)
9038 #define RTC_C_PS0CTL_RT0IP__6_DIVIDE_BY_128 (0x0018)
9039 #define RTC_C_PS0CTL_RT0IP__7 (0x001c)
9040 #define RTC_C_PS0CTL_RT0IP__7_DIVIDE_BY_256 (0x001c)
9041 #define RTC_C_PS0CTL_RT0IP__M (0x001c)
9042 #define RTC_C_PS0CTL_RT0PSIE (0x0002)
9043 #define RTC_C_PS0CTL_RT0PSIE__0 (0x0000)
9044 #define RTC_C_PS0CTL_RT0PSIE__1 (0x0002)
9045 #define RTC_C_PS0CTL_RT0PSIFG (0x0001)
9046 #define RTC_C_PS0CTL_RT0PSIFG__0 (0x0000)
9047 #define RTC_C_PS0CTL_RT0PSIFG__1 (0x0001)
9048 #define RTC_C_PS1 (HWREG8(0x4000440D))
9049 #define RTC_C_PS1CTL (HWREG16(0x4000440A))
9050 #define RTC_C_PS1CTL_RT1IP__0 (0x0000)
9051 #define RTC_C_PS1CTL_RT1IP__0_DIVIDE_BY_2 (0x0000)
9052 #define RTC_C_PS1CTL_RT1IP__1 (0x0004)
9053 #define RTC_C_PS1CTL_RT1IP__1_DIVIDE_BY_4 (0x0004)
9054 #define RTC_C_PS1CTL_RT1IP__2 (0x0008)
9055 #define RTC_C_PS1CTL_RT1IP__2_DIVIDE_BY_8 (0x0008)
9056 #define RTC_C_PS1CTL_RT1IP__3 (0x000c)
9057 #define RTC_C_PS1CTL_RT1IP__3_DIVIDE_BY_16 (0x000c)
9058 #define RTC_C_PS1CTL_RT1IP__4 (0x0010)
9059 #define RTC_C_PS1CTL_RT1IP__4_DIVIDE_BY_32 (0x0010)
9060 #define RTC_C_PS1CTL_RT1IP__5 (0x0014)
9061 #define RTC_C_PS1CTL_RT1IP__5_DIVIDE_BY_64 (0x0014)
9062 #define RTC_C_PS1CTL_RT1IP__6 (0x0018)
9063 #define RTC_C_PS1CTL_RT1IP__6_DIVIDE_BY_128 (0x0018)
9064 #define RTC_C_PS1CTL_RT1IP__7 (0x001c)
9065 #define RTC_C_PS1CTL_RT1IP__7_DIVIDE_BY_256 (0x001c)
9066 #define RTC_C_PS1CTL_RT1IP__M (0x001c)
9067 #define RTC_C_PS1CTL_RT1PSIE (0x0002)
9068 #define RTC_C_PS1CTL_RT1PSIE__0 (0x0000)
9069 #define RTC_C_PS1CTL_RT1PSIE__1 (0x0002)
9070 #define RTC_C_PS1CTL_RT1PSIFG (0x0001)
9071 #define RTC_C_PS1CTL_RT1PSIFG__0 (0x0000)
9072 #define RTC_C_PS1CTL_RT1PSIFG__1 (0x0001)
9074 #define RTC_C_SEC_SECONDS__M (0x003f)
9075 #define RTC_C_TCMP (HWREG16(0x40004406))
9076 #define RTC_C_TCMP_TCMPS (0x8000)
9077 #define RTC_C_TCMP_TCMPS__0 (0x0000)
9078 #define RTC_C_TCMP_TCMPS__1 (0x8000)
9079 #define RTC_C_TCMP_TCMP__M (0x00ff)
9080 #define RTC_C_TCMP_TCOK (0x2000)
9081 #define RTC_C_TCMP_TCOK__0 (0x0000)
9082 #define RTC_C_TCMP_TCOK__1 (0x2000)
9083 #define RTC_C_TCMP_TCRDY (0x4000)
9084 #define RTC_C_YEAR (HWREG16(0x40004416))
9085 #define RTC_C_YEAR_YEAR_HIGH_BYTE__M (0x0f00)
9086 #define RTC_C_YEAR_YEAR_LOW_BYTE__M (0x00ff)
9087 #define RTC_NONE (0x0000)
9088 #define RTC_RT0PSIFG (0x000C)
9089 #define RTC_RT1PSIFG (0x000E)
9090 #define RTC_RTCAIFG (0x000A)
9091 #define RTC_RTCOFIFG (0x0002)
9092 #define RTC_RTCRDYIFG (0x0006)
9093 #define RTC_RTCTEVIFG (0x0008)
9094 #define SCS_AIRCR_ENDIANESS__0 (0x00000000)
9095 #define SCS_AIRCR_ENDIANESS__0_LITTLE_ENDIAN (0x00000000)
9096 #define SCS_AIRCR_ENDIANESS__1 (0x00008000)
9097 #define SCS_AIRCR_ENDIANESS__1_BIG_ENDIAN (0x00008000)
9098 #define SCS_AIRCR_PRIGROUP__M (0x00000700)
9099 #define SCS_AIRCR_VECTKEY__M (0xffff0000)
9100 #define SCS_CCR_STKALIGN__0 (0x00000000)
9101 #define SCS_CCR_STKALIGN__1 (0x00000200)
9102 #define SCS_CPUID_CONSTANT__M (0x000f0000)
9103 #define SCS_CPUID_IMPLEMENTER__M (0xff000000)
9104 #define SCS_CPUID_PARTNO__M (0x0000fff0)
9105 #define SCS_CPUID_REVISION__M (0x0000000f)
9106 #define SCS_CPUID_VARIANT__M (0x00f00000)
9107 #define SCS_DCRSR_REGSEL__0 (0x00000000)
9108 #define SCS_DCRSR_REGSEL__0_R0 (0x00000000)
9109 #define SCS_DCRSR_REGSEL__0_R11 (0x00000000)
9110 #define SCS_DCRSR_REGSEL__1 (0x00000001)
9111 #define SCS_DCRSR_REGSEL__10 (0x0000000a)
9112 #define SCS_DCRSR_REGSEL__10_R10 (0x0000000a)
9113 #define SCS_DCRSR_REGSEL__12 (0x0000000c)
9114 #define SCS_DCRSR_REGSEL__12_R12 (0x0000000c)
9115 #define SCS_DCRSR_REGSEL__13 (0x0000000d)
9116 #define SCS_DCRSR_REGSEL__13_CURRENT_SP (0x0000000d)
9117 #define SCS_DCRSR_REGSEL__14 (0x0000000e)
9118 #define SCS_DCRSR_REGSEL__14_LR (0x0000000e)
9119 #define SCS_DCRSR_REGSEL__15 (0x0000000f)
9120 #define SCS_DCRSR_REGSEL__16 (0x00000010)
9121 #define SCS_DCRSR_REGSEL__17 (0x00000011)
9122 #define SCS_DCRSR_REGSEL__17_MSP__MAIN_SP (0x00000011)
9123 #define SCS_DCRSR_REGSEL__18 (0x00000012)
9124 #define SCS_DCRSR_REGSEL__18_PSP__PROCESS_SP (0x00000012)
9125 #define SCS_DCRSR_REGSEL__1_R1 (0x00000001)
9126 #define SCS_DCRSR_REGSEL__2 (0x00000002)
9127 #define SCS_DCRSR_REGSEL__20 (0x00000014)
9128 #define SCS_DCRSR_REGSEL__2_R2 (0x00000002)
9129 #define SCS_DCRSR_REGSEL__3 (0x00000003)
9130 #define SCS_DCRSR_REGSEL__3_R3 (0x00000003)
9131 #define SCS_DCRSR_REGSEL__4 (0x00000004)
9132 #define SCS_DCRSR_REGSEL__4_R4 (0x00000004)
9133 #define SCS_DCRSR_REGSEL__5 (0x00000005)
9134 #define SCS_DCRSR_REGSEL__5_R5 (0x00000005)
9135 #define SCS_DCRSR_REGSEL__6 (0x00000006)
9136 #define SCS_DCRSR_REGSEL__6_R6 (0x00000006)
9137 #define SCS_DCRSR_REGSEL__7 (0x00000007)
9138 #define SCS_DCRSR_REGSEL__7_R7 (0x00000007)
9139 #define SCS_DCRSR_REGSEL__8 (0x00000008)
9140 #define SCS_DCRSR_REGSEL__8_R8 (0x00000008)
9141 #define SCS_DCRSR_REGSEL__9 (0x00000009)
9142 #define SCS_DCRSR_REGSEL__9_R9 (0x00000009)
9143 #define SCS_DCRSR_REGSEL__M (0x0000001f)
9144 #define SCS_DEMCR_MON_REQ__0 (0x00000000)
9145 #define SCS_DEMCR_MON_REQ__1 (0x00080000)
9146 #define SCS_DFSR_BKPT__0 (0x00000000)
9147 #define SCS_DFSR_BKPT__1 (0x00000002)
9148 #define SCS_DFSR_DWTTRAP__0 (0x00000000)
9149 #define SCS_DFSR_DWTTRAP__0_NO_DWT_MATCH (0x00000000)
9150 #define SCS_DFSR_DWTTRAP__1 (0x00000004)
9151 #define SCS_DFSR_DWTTRAP__1_DWT_MATCH (0x00000004)
9152 #define SCS_DFSR_EXTERNAL__0 (0x00000000)
9153 #define SCS_DFSR_EXTERNAL__1 (0x00000010)
9154 #define SCS_DFSR_HALTED__0 (0x00000000)
9155 #define SCS_DFSR_HALTED__0_NO_HALT_REQUEST (0x00000000)
9156 #define SCS_DFSR_HALTED__1 (0x00000001)
9157 #define SCS_DFSR_VCATCH__0 (0x00000000)
9158 #define SCS_DFSR_VCATCH__1 (0x00000008)
9159 #define SCS_ICSR_ISRPENDING__0 (0x00000000)
9160 #define SCS_ICSR_ISRPENDING__1 (0x00400000)
9161 #define SCS_ICSR_ISRPREEMPT__0 (0x00000000)
9162 #define SCS_ICSR_ISRPREEMPT__1 (0x00800000)
9163 #define SCS_ICSR_NMIPENDSET__0 (0x00000000)
9164 #define SCS_ICSR_NMIPENDSET__1 (0x80000000)
9165 #define SCS_ICSR_NMIPENDSET__1_SET_PENDING_NMI (0x80000000)
9166 #define SCS_ICSR_PENDSTCLR__0 (0x00000000)
9167 #define SCS_ICSR_PENDSTCLR__1 (0x02000000)
9168 #define SCS_ICSR_PENDSTSET__0 (0x00000000)
9169 #define SCS_ICSR_PENDSTSET__1 (0x04000000)
9170 #define SCS_ICSR_PENDSVCLR__0 (0x00000000)
9171 #define SCS_ICSR_PENDSVCLR__1 (0x08000000)
9172 #define SCS_ICSR_PENDSVSET__0 (0x00000000)
9173 #define SCS_ICSR_PENDSVSET__1 (0x10000000)
9174 #define SCS_ICSR_VECTACTIVE__M (0x000001ff)
9175 #define SCS_ICSR_VECTPENDING__M (0x0003f000)
9176 #define SCS_ICTR_INTLINESNUM__M (0x0000001f)
9177 #define SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL__0 (0x00000000)
9178 #define SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL__0_NOT_SUPPORTED (0x00000000)
9179 #define SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL__1 (0x00100000)
9180 #define SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL__M (0x00f00000)
9181 #define SCS_ID_ISAR1_ETEND_INSRS__0 (0x00000000)
9182 #define SCS_ID_ISAR1_ETEND_INSRS__1 (0x00001000)
9183 #define SCS_ID_ISAR1_ETEND_INSRS__2 (0x00002000)
9184 #define SCS_ID_ISAR1_ETEND_INSRS__2_N_A (0x00002000)
9185 #define SCS_ID_ISAR1_ETEND_INSRS__M (0x0000f000)
9186 #define SCS_ID_ISAR1_IFTHEN_INSTRS__0 (0x00000000)
9187 #define SCS_ID_ISAR1_IFTHEN_INSTRS__1 (0x00010000)
9188 #define SCS_ID_ISAR1_IFTHEN_INSTRS__M (0x000f0000)
9189 #define SCS_ID_ISAR1_IMMEDIATE_INSTRS__0 (0x00000000)
9190 #define SCS_ID_ISAR1_IMMEDIATE_INSTRS__1 (0x00100000)
9191 #define SCS_ID_ISAR1_IMMEDIATE_INSTRS__M (0x00f00000)
9192 #define SCS_ID_ISAR1_INTERWORK_INSTRS__0 (0x00000000)
9193 #define SCS_ID_ISAR1_INTERWORK_INSTRS__1 (0x01000000)
9194 #define SCS_ID_ISAR1_INTERWORK_INSTRS__2 (0x02000000)
9195 #define SCS_ID_ISAR1_INTERWORK_INSTRS__3 (0x03000000)
9196 #define SCS_ID_ISAR1_INTERWORK_INSTRS__3_N_A (0x03000000)
9197 #define SCS_ID_ISAR1_INTERWORK_INSTRS__M (0x0f000000)
9198 #define SCS_ID_ISAR2_LOADSTORE_INSTRS__0 (0x00000000)
9199 #define SCS_ID_ISAR2_LOADSTORE_INSTRS__1 (0x00000001)
9200 #define SCS_ID_ISAR2_LOADSTORE_INSTRS__1_ADDS_LDRD_STRD (0x00000001)
9201 #define SCS_ID_ISAR2_LOADSTORE_INSTRS__M (0x0000000f)
9202 #define SCS_ID_ISAR2_MEMHINT_INSTRS__0 (0x00000000)
9203 #define SCS_ID_ISAR2_MEMHINT_INSTRS__1 (0x00000010)
9204 #define SCS_ID_ISAR2_MEMHINT_INSTRS__1_ADDS_PLD (0x00000010)
9205 #define SCS_ID_ISAR2_MEMHINT_INSTRS__2 (0x00000020)
9206 #define SCS_ID_ISAR2_MEMHINT_INSTRS__3 (0x00000030)
9207 #define SCS_ID_ISAR2_MEMHINT_INSTRS__3_ADDS_PLI (0x00000030)
9208 #define SCS_ID_ISAR2_MEMHINT_INSTRS__M (0x000000f0)
9209 #define SCS_ID_ISAR2_MULTIACCESSINT_INSTRS__0 (0x00000000)
9210 #define SCS_ID_ISAR2_MULTIACCESSINT_INSTRS__1 (0x00000100)
9211 #define SCS_ID_ISAR2_MULTIACCESSINT_INSTRS__2 (0x00000200)
9212 #define SCS_ID_ISAR2_MULTIACCESSINT_INSTRS__M (0x00000f00)
9213 #define SCS_ID_ISAR2_MULTS_INSTRS__0 (0x00000000)
9214 #define SCS_ID_ISAR2_MULTS_INSTRS__1 (0x00010000)
9215 #define SCS_ID_ISAR2_MULTS_INSTRS__2 (0x00020000)
9216 #define SCS_ID_ISAR2_MULTS_INSTRS__2_N_A (0x00020000)
9217 #define SCS_ID_ISAR2_MULTS_INSTRS__3 (0x00030000)
9218 #define SCS_ID_ISAR2_MULTS_INSTRS__3_N_A (0x00030000)
9219 #define SCS_ID_ISAR2_MULTS_INSTRS__M (0x000f0000)
9220 #define SCS_ID_ISAR2_MULTU_INSTRS__0 (0x00000000)
9221 #define SCS_ID_ISAR2_MULTU_INSTRS__1 (0x00100000)
9222 #define SCS_ID_ISAR2_MULTU_INSTRS__2 (0x00200000)
9223 #define SCS_ID_ISAR2_MULTU_INSTRS__2_N_A (0x00200000)
9224 #define SCS_ID_ISAR2_MULTU_INSTRS__M (0x00f00000)
9225 #define SCS_ID_ISAR2_MULT_INSTRS__0 (0x00000000)
9226 #define SCS_ID_ISAR2_MULT_INSTRS__1 (0x00001000)
9227 #define SCS_ID_ISAR2_MULT_INSTRS__1_ADDS_MLA (0x00001000)
9228 #define SCS_ID_ISAR2_MULT_INSTRS__2 (0x00002000)
9229 #define SCS_ID_ISAR2_MULT_INSTRS__2_ADDS_MLS (0x00002000)
9230 #define SCS_ID_ISAR2_MULT_INSTRS__M (0x0000f000)
9231 #define SCS_ID_ISAR2_REVERSAL_INSTRS__0 (0x00000000)
9232 #define SCS_ID_ISAR2_REVERSAL_INSTRS__1 (0x10000000)
9233 #define SCS_ID_ISAR2_REVERSAL_INSTRS__2 (0x20000000)
9234 #define SCS_ID_ISAR2_REVERSAL_INSTRS__2_ADDS_RBIT (0x20000000)
9235 #define SCS_ID_ISAR2_REVERSAL_INSTRS__M (0xf0000000)
9236 #define SCS_ID_ISAR3_SATRUATE_INSTRS__0 (0x00000000)
9237 #define SCS_ID_ISAR3_SATRUATE_INSTRS__1 (0x00000001)
9238 #define SCS_ID_ISAR3_SATRUATE_INSTRS__1_N_A (0x00000001)
9239 #define SCS_ID_ISAR3_SATRUATE_INSTRS__M (0x0000000f)
9240 #define SCS_ID_ISAR3_SIMD_INSTRS__0 (0x00000000)
9241 #define SCS_ID_ISAR3_SIMD_INSTRS__1 (0x00000010)
9242 #define SCS_ID_ISAR3_SIMD_INSTRS__3 (0x00000030)
9243 #define SCS_ID_ISAR3_SIMD_INSTRS__3_N_A (0x00000030)
9244 #define SCS_ID_ISAR3_SIMD_INSTRS__M (0x000000f0)
9245 #define SCS_ID_ISAR3_SVC_INSTRS__0 (0x00000000)
9246 #define SCS_ID_ISAR3_SVC_INSTRS__1 (0x00000100)
9247 #define SCS_ID_ISAR3_SVC_INSTRS__1_ADDS_SVC__SWI (0x00000100)
9248 #define SCS_ID_ISAR3_SVC_INSTRS__M (0x00000f00)
9249 #define SCS_ID_ISAR3_SYNCPRIM_INSTRS__0 (0x00000000)
9250 #define SCS_ID_ISAR3_SYNCPRIM_INSTRS__1 (0x00001000)
9251 #define SCS_ID_ISAR3_SYNCPRIM_INSTRS__2 (0x00002000)
9252 #define SCS_ID_ISAR3_SYNCPRIM_INSTRS__M (0x0000f000)
9253 #define SCS_ID_ISAR3_TABBRANCH_INSTRS__0 (0x00000000)
9254 #define SCS_ID_ISAR3_TABBRANCH_INSTRS__1 (0x00010000)
9255 #define SCS_ID_ISAR3_TABBRANCH_INSTRS__1_ADDS_TBB__TBH (0x00010000)
9256 #define SCS_ID_ISAR3_TABBRANCH_INSTRS__M (0x000f0000)
9257 #define SCS_ID_ISAR3_THUMBCOPY_INSTRS__0 (0x00000000)
9258 #define SCS_ID_ISAR3_THUMBCOPY_INSTRS__1 (0x00100000)
9259 #define SCS_ID_ISAR3_THUMBCOPY_INSTRS__M (0x00f00000)
9260 #define SCS_ID_ISAR3_TRUENOP_INSTRS__0 (0x00000000)
9261 #define SCS_ID_ISAR3_TRUENOP_INSTRS__1 (0x01000000)
9262 #define SCS_ID_ISAR3_TRUENOP_INSTRS__M (0x0f000000)
9263 #define SCS_ID_ISAR4_BARRIER_INSTRS__0 (0x00000000)
9264 #define SCS_ID_ISAR4_BARRIER_INSTRS__1 (0x00010000)
9265 #define SCS_ID_ISAR4_BARRIER_INSTRS__M (0x000f0000)
9266 #define SCS_ID_ISAR4_PSR_M_INSTRS__0 (0x00000000)
9267 #define SCS_ID_ISAR4_PSR_M_INSTRS__1 (0x01000000)
9268 #define SCS_ID_ISAR4_PSR_M_INSTRS__M (0x0f000000)
9269 #define SCS_ID_ISAR4_SYNCPRIM_INSTRS_FRAC__0 (0x00000000)
9270 #define SCS_ID_ISAR4_SYNCPRIM_INSTRS_FRAC__3 (0x00300000)
9271 #define SCS_ID_ISAR4_SYNCPRIM_INSTRS_FRAC__M (0x00f00000)
9272 #define SCS_ID_ISAR4_UNPRIV_INSTRS__0 (0x00000000)
9273 #define SCS_ID_ISAR4_UNPRIV_INSTRS__1 (0x00000001)
9274 #define SCS_ID_ISAR4_UNPRIV_INSTRS__2 (0x00000002)
9275 #define SCS_ID_ISAR4_UNPRIV_INSTRS__M (0x0000000f)
9276 #define SCS_ID_ISAR4_WITHSHIFTS_INSTRS__0 (0x00000000)
9277 #define SCS_ID_ISAR4_WITHSHIFTS_INSTRS__1 (0x00000010)
9278 #define SCS_ID_ISAR4_WITHSHIFTS_INSTRS__3 (0x00000030)
9279 #define SCS_ID_ISAR4_WITHSHIFTS_INSTRS__4 (0x00000040)
9280 #define SCS_ID_ISAR4_WITHSHIFTS_INSTRS__M (0x000000f0)
9281 #define SCS_ID_ISAR4_WRITEBACK_INSTRS__0 (0x00000000)
9282 #define SCS_ID_ISAR4_WRITEBACK_INSTRS__1 (0x00000100)
9283 #define SCS_ID_ISAR4_WRITEBACK_INSTRS__M (0x00000f00)
9284 #define SCS_ID_MMFR0_AUILIARY_REGISTER_SUPPORT__0 (0x00000000)
9285 #define SCS_ID_MMFR0_AUILIARY_REGISTER_SUPPORT__0_NOT_SUPPORTED (0x00000000)
9286 #define SCS_ID_MMFR0_AUILIARY_REGISTER_SUPPORT__1 (0x00100000)
9287 #define SCS_ID_MMFR0_AUILIARY_REGISTER_SUPPORT__M (0x00f00000)
9288 #define SCS_ID_MMFR0_CACHE_COHERENCE_SUPPORT__0 (0x00000000)
9289 #define SCS_ID_MMFR0_CACHE_COHERENCE_SUPPORT__1 (0x00000100)
9290 #define SCS_ID_MMFR0_CACHE_COHERENCE_SUPPORT__2 (0x00000200)
9291 #define SCS_ID_MMFR0_CACHE_COHERENCE_SUPPORT__3 (0x00000300)
9292 #define SCS_ID_MMFR0_CACHE_COHERENCE_SUPPORT__M (0x00000f00)
9293 #define SCS_ID_MMFR0_OUTER_NON_SHARABLE_SUPPORT__0 (0x00000000)
9294 #define SCS_ID_MMFR0_OUTER_NON_SHARABLE_SUPPORT__1 (0x00001000)
9295 #define SCS_ID_MMFR0_OUTER_NON_SHARABLE_SUPPORT__M (0x0000f000)
9296 #define SCS_ID_MMFR0_PMSA_SUPPORT__0 (0x00000000)
9297 #define SCS_ID_MMFR0_PMSA_SUPPORT__0_NOT_SUPPORTED (0x00000000)
9298 #define SCS_ID_MMFR0_PMSA_SUPPORT__1 (0x00000010)
9299 #define SCS_ID_MMFR0_PMSA_SUPPORT__2 (0x00000020)
9300 #define SCS_ID_MMFR0_PMSA_SUPPORT__3 (0x00000030)
9301 #define SCS_ID_MMFR0_PMSA_SUPPORT__M (0x000000f0)
9302 #define SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING__0 (0x00000000)
9303 #define SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING__0_NOT_SUPPORTED (0x00000000)
9304 #define SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING__1 (0x01000000)
9305 #define SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING__M (0x0f000000)
9306 #define SCS_ID_PFR0_STATE0__0 (0x00000000)
9307 #define SCS_ID_PFR0_STATE0__0_NO_ARM_ENCODING (0x00000000)
9308 #define SCS_ID_PFR0_STATE0__1 (0x00000001)
9309 #define SCS_ID_PFR0_STATE0__1_N_A (0x00000001)
9310 #define SCS_ID_PFR0_STATE0__M (0x0000000f)
9311 #define SCS_ID_PFR0_STATE1__0 (0x00000000)
9312 #define SCS_ID_PFR0_STATE1__0_N_A (0x00000000)
9313 #define SCS_ID_PFR0_STATE1__1 (0x00000010)
9314 #define SCS_ID_PFR0_STATE1__1_N_A (0x00000010)
9315 #define SCS_ID_PFR0_STATE1__2 (0x00000020)
9316 #define SCS_ID_PFR0_STATE1__3 (0x00000030)
9317 #define SCS_ID_PFR0_STATE1__M (0x000000f0)
9318 #define SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL__0 (0x00000000)
9319 #define SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL__0_NOT_SUPPORTED (0x00000000)
9320 #define SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL__2 (0x00000200)
9321 #define SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL__M (0x00000f00)
9322 #define SCS_ISAR0_BITCOUNT_INSTRS__0 (0x00000000)
9323 #define SCS_ISAR0_BITCOUNT_INSTRS__1 (0x00000010)
9324 #define SCS_ISAR0_BITCOUNT_INSTRS__1_ADDS_CLZ (0x00000010)
9325 #define SCS_ISAR0_BITCOUNT_INSTRS__M (0x000000f0)
9326 #define SCS_ISAR0_BITFIELD_INSTRS__0 (0x00000000)
9327 #define SCS_ISAR0_BITFIELD_INSTRS__1 (0x00000100)
9328 #define SCS_ISAR0_BITFIELD_INSTRS__M (0x00000f00)
9329 #define SCS_ISAR0_CMPBRANCH_INSTRS__0 (0x00000000)
9330 #define SCS_ISAR0_CMPBRANCH_INSTRS__1 (0x00001000)
9331 #define SCS_ISAR0_CMPBRANCH_INSTRS__1_ADDS_CB_N_Z (0x00001000)
9332 #define SCS_ISAR0_CMPBRANCH_INSTRS__M (0x0000f000)
9333 #define SCS_ISAR0_COPROC_INSTRS__0 (0x00000000)
9334 #define SCS_ISAR0_COPROC_INSTRS__1 (0x00010000)
9335 #define SCS_ISAR0_COPROC_INSTRS__2 (0x00020000)
9336 #define SCS_ISAR0_COPROC_INSTRS__3 (0x00030000)
9337 #define SCS_ISAR0_COPROC_INSTRS__4 (0x00040000)
9338 #define SCS_ISAR0_COPROC_INSTRS__M (0x000f0000)
9339 #define SCS_ISAR0_DEBUG_INSTRS__0 (0x00000000)
9340 #define SCS_ISAR0_DEBUG_INSTRS__1 (0x00100000)
9341 #define SCS_ISAR0_DEBUG_INSTRS__1_ADDS_BKPT (0x00100000)
9342 #define SCS_ISAR0_DEBUG_INSTRS__M (0x00f00000)
9343 #define SCS_ISAR0_DIVIDE_INSTRS__0 (0x00000000)
9344 #define SCS_ISAR0_DIVIDE_INSTRS__1 (0x01000000)
9345 #define SCS_ISAR0_DIVIDE_INSTRS__M (0x0f000000)
9346 #define SCS_NVIC_IPR0_PRI_0__M (0x000000ff)
9347 #define SCS_NVIC_IPR0_PRI_1__M (0x0000ff00)
9348 #define SCS_NVIC_IPR0_PRI_2__M (0x00ff0000)
9349 #define SCS_NVIC_IPR0_PRI_3__M (0xff000000)
9350 #define SCS_NVIC_IPR10_PRI_40__M (0x000000ff)
9351 #define SCS_NVIC_IPR10_PRI_41__M (0x0000ff00)
9352 #define SCS_NVIC_IPR10_PRI_42__M (0x00ff0000)
9353 #define SCS_NVIC_IPR10_PRI_43__M (0xff000000)
9354 #define SCS_NVIC_IPR11_PRI_44__M (0x000000ff)
9355 #define SCS_NVIC_IPR11_PRI_45__M (0x0000ff00)
9356 #define SCS_NVIC_IPR11_PRI_46__M (0x00ff0000)
9357 #define SCS_NVIC_IPR11_PRI_47__M (0xff000000)
9358 #define SCS_NVIC_IPR12_PRI_48__M (0x000000ff)
9359 #define SCS_NVIC_IPR12_PRI_49__M (0x0000ff00)
9360 #define SCS_NVIC_IPR12_PRI_50__M (0x00ff0000)
9361 #define SCS_NVIC_IPR12_PRI_51__M (0xff000000)
9362 #define SCS_NVIC_IPR13_PRI_52__M (0x000000ff)
9363 #define SCS_NVIC_IPR13_PRI_53__M (0x0000ff00)
9364 #define SCS_NVIC_IPR13_PRI_54__M (0x00ff0000)
9365 #define SCS_NVIC_IPR13_PRI_55__M (0xff000000)
9366 #define SCS_NVIC_IPR14_PRI_56__M (0x000000ff)
9367 #define SCS_NVIC_IPR14_PRI_57__M (0x0000ff00)
9368 #define SCS_NVIC_IPR14_PRI_58__M (0x00ff0000)
9369 #define SCS_NVIC_IPR14_PRI_59__M (0xff000000)
9370 #define SCS_NVIC_IPR15_PRI_60__M (0x000000ff)
9371 #define SCS_NVIC_IPR15_PRI_61__M (0x0000ff00)
9372 #define SCS_NVIC_IPR15_PRI_62__M (0x00ff0000)
9373 #define SCS_NVIC_IPR15_PRI_63__M (0xff000000)
9374 #define SCS_NVIC_IPR1_PRI_4__M (0x000000ff)
9375 #define SCS_NVIC_IPR1_PRI_5__M (0x0000ff00)
9376 #define SCS_NVIC_IPR1_PRI_6__M (0x00ff0000)
9377 #define SCS_NVIC_IPR1_PRI_7__M (0xff000000)
9378 #define SCS_NVIC_IPR2_PRI_10__M (0x00ff0000)
9379 #define SCS_NVIC_IPR2_PRI_11__M (0xff000000)
9380 #define SCS_NVIC_IPR2_PRI_8__M (0x000000ff)
9381 #define SCS_NVIC_IPR2_PRI_9__M (0x0000ff00)
9382 #define SCS_NVIC_IPR3_PRI_12__M (0x000000ff)
9383 #define SCS_NVIC_IPR3_PRI_13__M (0x0000ff00)
9384 #define SCS_NVIC_IPR3_PRI_14__M (0x00ff0000)
9385 #define SCS_NVIC_IPR3_PRI_15__M (0xff000000)
9386 #define SCS_NVIC_IPR4_PRI_16__M (0x000000ff)
9387 #define SCS_NVIC_IPR4_PRI_17__M (0x0000ff00)
9388 #define SCS_NVIC_IPR4_PRI_18__M (0x00ff0000)
9389 #define SCS_NVIC_IPR4_PRI_19__M (0xff000000)
9390 #define SCS_NVIC_IPR5_PRI_20__M (0x000000ff)
9391 #define SCS_NVIC_IPR5_PRI_21__M (0x0000ff00)
9392 #define SCS_NVIC_IPR5_PRI_22__M (0x00ff0000)
9393 #define SCS_NVIC_IPR5_PRI_23__M (0xff000000)
9394 #define SCS_NVIC_IPR6_PRI_24__M (0x000000ff)
9395 #define SCS_NVIC_IPR6_PRI_25__M (0x0000ff00)
9396 #define SCS_NVIC_IPR6_PRI_26__M (0x00ff0000)
9397 #define SCS_NVIC_IPR6_PRI_27__M (0xff000000)
9398 #define SCS_NVIC_IPR7_PRI_28__M (0x000000ff)
9399 #define SCS_NVIC_IPR7_PRI_29__M (0x0000ff00)
9400 #define SCS_NVIC_IPR7_PRI_30__M (0x00ff0000)
9401 #define SCS_NVIC_IPR7_PRI_31__M (0xff000000)
9402 #define SCS_NVIC_IPR8_PRI_32__M (0x000000ff)
9403 #define SCS_NVIC_IPR8_PRI_33__M (0x0000ff00)
9404 #define SCS_NVIC_IPR8_PRI_34__M (0x00ff0000)
9405 #define SCS_NVIC_IPR8_PRI_35__M (0xff000000)
9406 #define SCS_NVIC_IPR9_PRI_36__M (0x000000ff)
9407 #define SCS_NVIC_IPR9_PRI_37__M (0x0000ff00)
9408 #define SCS_NVIC_IPR9_PRI_38__M (0x00ff0000)
9409 #define SCS_NVIC_IPR9_PRI_39__M (0xff000000)
9410 #define SCS_SCR_SLEEPDEEP__0 (0x00000000)
9411 #define SCS_SCR_SLEEPDEEP__1 (0x00000004)
9412 #define SCS_SCR_SLEEPONEXIT__0 (0x00000000)
9413 #define SCS_SCR_SLEEPONEXIT__1 (0x00000002)
9414 #define SCS_SHCSR_BUSFAULTACT__0 (0x00000000)
9415 #define SCS_SHCSR_BUSFAULTACT__0_NOT_ACTIVE (0x00000000)
9416 #define SCS_SHCSR_BUSFAULTACT__1 (0x00000002)
9417 #define SCS_SHCSR_BUSFAULTACT__1_ACTIVE (0x00000002)
9418 #define SCS_SHCSR_BUSFAULTENA__0 (0x00000000)
9419 #define SCS_SHCSR_BUSFAULTENA__0_DISABLED (0x00000000)
9420 #define SCS_SHCSR_BUSFAULTENA__1 (0x00020000)
9421 #define SCS_SHCSR_BUSFAULTENA__1_ENABLED (0x00020000)
9422 #define SCS_SHCSR_BUSFAULTPENDED__0 (0x00000000)
9423 #define SCS_SHCSR_BUSFAULTPENDED__0_NOT_PENDED (0x00000000)
9424 #define SCS_SHCSR_BUSFAULTPENDED__1 (0x00004000)
9425 #define SCS_SHCSR_BUSFAULTPENDED__1_PENDED (0x00004000)
9426 #define SCS_SHCSR_MEMFAULTACT__0 (0x00000000)
9427 #define SCS_SHCSR_MEMFAULTACT__0_NOT_ACTIVE (0x00000000)
9428 #define SCS_SHCSR_MEMFAULTACT__1 (0x00000001)
9429 #define SCS_SHCSR_MEMFAULTACT__1_ACTIVE (0x00000001)
9430 #define SCS_SHCSR_MEMFAULTENA__0 (0x00000000)
9431 #define SCS_SHCSR_MEMFAULTENA__0_DISABLED (0x00000000)
9432 #define SCS_SHCSR_MEMFAULTENA__1 (0x00010000)
9433 #define SCS_SHCSR_MEMFAULTENA__1_ENABLED (0x00010000)
9434 #define SCS_SHCSR_MEMFAULTPENDED__0 (0x00000000)
9435 #define SCS_SHCSR_MEMFAULTPENDED__0_NOT_PENDED (0x00000000)
9436 #define SCS_SHCSR_MEMFAULTPENDED__1 (0x00002000)
9437 #define SCS_SHCSR_MEMFAULTPENDED__1_PENDED (0x00002000)
9438 #define SCS_SHCSR_MONITORACT__0 (0x00000000)
9439 #define SCS_SHCSR_MONITORACT__0_NOT_ACTIVE (0x00000000)
9440 #define SCS_SHCSR_MONITORACT__1 (0x00000100)
9441 #define SCS_SHCSR_MONITORACT__1_ACTIVE (0x00000100)
9442 #define SCS_SHCSR_PENDSVACT__0 (0x00000000)
9443 #define SCS_SHCSR_PENDSVACT__0_NOT_ACTIVE (0x00000000)
9444 #define SCS_SHCSR_PENDSVACT__1 (0x00000400)
9445 #define SCS_SHCSR_PENDSVACT__1_ACTIVE (0x00000400)
9446 #define SCS_SHCSR_SVCALLACT__0 (0x00000000)
9447 #define SCS_SHCSR_SVCALLACT__0_NOT_ACTIVE (0x00000000)
9448 #define SCS_SHCSR_SVCALLACT__1 (0x00000080)
9449 #define SCS_SHCSR_SVCALLACT__1_ACTIVE (0x00000080)
9450 #define SCS_SHCSR_SVCALLPENDED__0 (0x00000000)
9451 #define SCS_SHCSR_SVCALLPENDED__0_NOT_PENDED (0x00000000)
9452 #define SCS_SHCSR_SVCALLPENDED__1 (0x00008000)
9453 #define SCS_SHCSR_SVCALLPENDED__1_PENDED (0x00008000)
9454 #define SCS_SHCSR_SYSTICKACT__0 (0x00000000)
9455 #define SCS_SHCSR_SYSTICKACT__0_NOT_ACTIVE (0x00000000)
9456 #define SCS_SHCSR_SYSTICKACT__1 (0x00000800)
9457 #define SCS_SHCSR_SYSTICKACT__1_ACTIVE (0x00000800)
9458 #define SCS_SHCSR_USGFAULTACT__0 (0x00000000)
9459 #define SCS_SHCSR_USGFAULTACT__0_NOT_ACTIVE (0x00000000)
9460 #define SCS_SHCSR_USGFAULTACT__1 (0x00000008)
9461 #define SCS_SHCSR_USGFAULTACT__1_ACTIVE (0x00000008)
9462 #define SCS_SHCSR_USGFAULTENA__0 (0x00000000)
9463 #define SCS_SHCSR_USGFAULTENA__0_DISABLED (0x00000000)
9464 #define SCS_SHCSR_USGFAULTENA__1 (0x00040000)
9465 #define SCS_SHCSR_USGFAULTENA__1_ENABLED (0x00040000)
9466 #define SCS_SHCSR_USGFAULTPENDED__0 (0x00000000)
9467 #define SCS_SHCSR_USGFAULTPENDED__0_NOT_PENDED (0x00000000)
9468 #define SCS_SHCSR_USGFAULTPENDED__1 (0x00001000)
9469 #define SCS_SHCSR_USGFAULTPENDED__1_PENDED (0x00001000)
9470 #define SCS_SHPR1_PRI_4__M (0x000000ff)
9471 #define SCS_SHPR1_PRI_5__M (0x0000ff00)
9472 #define SCS_SHPR1_PRI_6__M (0x00ff0000)
9473 #define SCS_SHPR1_PRI_7__M (0xff000000)
9474 #define SCS_SHPR2_PRI_10__M (0x00ff0000)
9475 #define SCS_SHPR2_PRI_11__M (0xff000000)
9476 #define SCS_SHPR2_PRI_8__M (0x000000ff)
9477 #define SCS_SHPR2_PRI_9__M (0x0000ff00)
9478 #define SCS_SHPR3_PRI_12__M (0x000000ff)
9479 #define SCS_SHPR3_PRI_13__M (0x0000ff00)
9480 #define SCS_SHPR3_PRI_14__M (0x00ff0000)
9481 #define SCS_SHPR3_PRI_15__M (0xff000000)
9482 #define SCS_STCR_TENMS__M (0x00ffffff)
9483 #define SCS_STCSR_CLKSOURCE__0 (0x00000000)
9484 #define SCS_STCSR_CLKSOURCE__1 (0x00000004)
9485 #define SCS_STCSR_CLKSOURCE__1_CORE_CLOCK (0x00000004)
9486 #define SCS_STCSR_ENABLE__0 (0x00000000)
9487 #define SCS_STCSR_TICKINT__0 (0x00000000)
9488 #define SCS_STCSR_TICKINT__1 (0x00000002)
9489 #define SCS_STCVR_CURRENT__M (0x00ffffff)
9490 #define SCS_STIR_INTID__M (0x000001ff)
9491 #define SCS_STRVR_RELOAD__M (0x00ffffff)
9492 #define SCS_VTOR_TBLOFF__M (0x1fffff80)
9493 #define SELA__0 (0x00000000)
9494 #define SELA__1 (0x00000100)
9495 #define SELA__2 (0x00000200)
9496 #define SELA__M (0x00000700)
9497 #define SELM__0 (0x00000000)
9498 #define SELM__1 (0x00000001)
9499 #define SELM__2 (0x00000002)
9500 #define SELM__3 (0x00000003)
9501 #define SELM__4 (0x00000004)
9502 #define SELM__5 (0x00000005)
9503 #define SELM__6 (0x00000006)
9504 #define SELM__7 (0x00000007)
9505 #define SELM__M (0x00000007)
9506 #define SELS__0 (0x00000000)
9507 #define SELS__1 (0x00000010)
9508 #define SELS__2 (0x00000020)
9509 #define SELS__3 (0x00000030)
9510 #define SELS__4 (0x00000040)
9511 #define SELS__5 (0x00000050)
9512 #define SELS__6 (0x00000060)
9513 #define SELS__7 (0x00000070)
9514 #define SELS__M (0x00000070)
9515 #define SYSCTL_DIOGLTFLTCTL_GLTCH_EN__0 (0x00000000)
9516 #define SYSCTL_DIOGLTFLTCTL_GLTCH_EN__1 (0x00000001)
9517 #define SYSCTL_NMI_CTLSTAT_CS_FLG__0 (0x00000000)
9518 #define SYSCTL_NMI_CTLSTAT_CS_FLG__1 (0x00010000)
9519 #define SYSCTL_NMI_CTLSTAT_CS_SRC__0 (0x00000000)
9520 #define SYSCTL_NMI_CTLSTAT_CS_SRC__1 (0x00000001)
9521 #define SYSCTL_NMI_CTLSTAT_PCM_FLG__0 (0x00000000)
9522 #define SYSCTL_NMI_CTLSTAT_PCM_FLG__1 (0x00040000)
9523 #define SYSCTL_NMI_CTLSTAT_PCM_SRC__0 (0x00000000)
9524 #define SYSCTL_NMI_CTLSTAT_PCM_SRC__1 (0x00000004)
9525 #define SYSCTL_NMI_CTLSTAT_PIN_FLG__0 (0x00000000)
9526 #define SYSCTL_NMI_CTLSTAT_PIN_FLG__1 (0x00080000)
9527 #define SYSCTL_NMI_CTLSTAT_PIN_SRC__0 (0x00000000)
9528 #define SYSCTL_NMI_CTLSTAT_PIN_SRC__1 (0x00000008)
9529 #define SYSCTL_NMI_CTLSTAT_PSS_FLG__0 (0x00000000)
9530 #define SYSCTL_NMI_CTLSTAT_PSS_FLG__1 (0x00020000)
9531 #define SYSCTL_NMI_CTLSTAT_PSS_SRC__0 (0x00000000)
9532 #define SYSCTL_NMI_CTLSTAT_PSS_SRC__1 (0x00000002)
9533 #define SYSCTL_PERI_HALTCTL_ADC__0 (0x00000000)
9534 #define SYSCTL_PERI_HALTCTL_ADC__1 (0x00002000)
9535 #define SYSCTL_PERI_HALTCTL_DMA__0 (0x00000000)
9536 #define SYSCTL_PERI_HALTCTL_DMA__1 (0x00008000)
9537 #define SYSCTL_PERI_HALTCTL_EUA0__0 (0x00000000)
9538 #define SYSCTL_PERI_HALTCTL_EUA0__1 (0x00000020)
9539 #define SYSCTL_PERI_HALTCTL_EUA1__0 (0x00000000)
9540 #define SYSCTL_PERI_HALTCTL_EUA1__1 (0x00000040)
9541 #define SYSCTL_PERI_HALTCTL_EUA2__0 (0x00000000)
9542 #define SYSCTL_PERI_HALTCTL_EUA2__1 (0x00000080)
9543 #define SYSCTL_PERI_HALTCTL_EUA3__0 (0x00000000)
9544 #define SYSCTL_PERI_HALTCTL_EUA3__1 (0x00000100)
9545 #define SYSCTL_PERI_HALTCTL_EUB0__0 (0x00000000)
9546 #define SYSCTL_PERI_HALTCTL_EUB0__1 (0x00000200)
9547 #define SYSCTL_PERI_HALTCTL_EUB1__0 (0x00000000)
9548 #define SYSCTL_PERI_HALTCTL_EUB1__1 (0x00000400)
9549 #define SYSCTL_PERI_HALTCTL_EUB2__0 (0x00000000)
9550 #define SYSCTL_PERI_HALTCTL_EUB2__1 (0x00000800)
9551 #define SYSCTL_PERI_HALTCTL_EUB3__0 (0x00000000)
9552 #define SYSCTL_PERI_HALTCTL_EUB3__1 (0x00001000)
9553 #define SYSCTL_PERI_HALTCTL_T16_0__0 (0x00000000)
9554 #define SYSCTL_PERI_HALTCTL_T16_0__1 (0x00000001)
9555 #define SYSCTL_PERI_HALTCTL_T16_1__0 (0x00000000)
9556 #define SYSCTL_PERI_HALTCTL_T16_1__1 (0x00000002)
9557 #define SYSCTL_PERI_HALTCTL_T16_2__0 (0x00000000)
9558 #define SYSCTL_PERI_HALTCTL_T16_2__1 (0x00000004)
9559 #define SYSCTL_PERI_HALTCTL_T16_3__0 (0x00000000)
9560 #define SYSCTL_PERI_HALTCTL_T16_3__1 (0x00000008)
9561 #define SYSCTL_PERI_HALTCTL_T32_0__0 (0x00000000)
9562 #define SYSCTL_PERI_HALTCTL_T32_0__1 (0x00000010)
9563 #define SYSCTL_PERI_HALTCTL_WDT__0 (0x00000000)
9564 #define SYSCTL_PERI_HALTCTL_WDT__1 (0x00004000)
9565 #define SYSCTL_REBOOT_CTL_WKEY__M (0x0000ff00)
9566 #define SYSCTL_SECDATA_UNLOCK_UNLKEY__M (0x0000ffff)
9567 #define SYSCTL_SRAM_BANKEN_BNK1_EN__0 (0x00000000)
9568 #define SYSCTL_SRAM_BANKEN_BNK1_EN__1 (0x00000002)
9569 #define SYSCTL_SRAM_BANKEN_BNK2_EN__0 (0x00000000)
9570 #define SYSCTL_SRAM_BANKEN_BNK2_EN__1 (0x00000004)
9571 #define SYSCTL_SRAM_BANKEN_BNK3_EN__0 (0x00000000)
9572 #define SYSCTL_SRAM_BANKEN_BNK3_EN__1 (0x00000008)
9573 #define SYSCTL_SRAM_BANKEN_BNK4_EN__0 (0x00000000)
9574 #define SYSCTL_SRAM_BANKEN_BNK4_EN__1 (0x00000010)
9575 #define SYSCTL_SRAM_BANKEN_BNK5_EN__0 (0x00000000)
9576 #define SYSCTL_SRAM_BANKEN_BNK5_EN__1 (0x00000020)
9577 #define SYSCTL_SRAM_BANKEN_BNK6_EN__0 (0x00000000)
9578 #define SYSCTL_SRAM_BANKEN_BNK6_EN__1 (0x00000040)
9579 #define SYSCTL_SRAM_BANKEN_BNK7_EN__0 (0x00000000)
9580 #define SYSCTL_SRAM_BANKEN_BNK7_EN__1 (0x00000080)
9581 #define SYSCTL_SRAM_BANKEN_SRAM_RDY__0 (0x00000000)
9582 #define SYSCTL_SRAM_BANKEN_SRAM_RDY__1 (0x00010000)
9583 #define SYSCTL_SRAM_BANKRET_BNK1_RET__0 (0x00000000)
9584 #define SYSCTL_SRAM_BANKRET_BNK1_RET__1 (0x00000002)
9585 #define SYSCTL_SRAM_BANKRET_BNK2_RET__0 (0x00000000)
9586 #define SYSCTL_SRAM_BANKRET_BNK2_RET__1 (0x00000004)
9587 #define SYSCTL_SRAM_BANKRET_BNK3_RET__0 (0x00000000)
9588 #define SYSCTL_SRAM_BANKRET_BNK3_RET__1 (0x00000008)
9589 #define SYSCTL_SRAM_BANKRET_BNK4_RET__0 (0x00000000)
9590 #define SYSCTL_SRAM_BANKRET_BNK4_RET__1 (0x00000010)
9591 #define SYSCTL_SRAM_BANKRET_BNK5_RET__0 (0x00000000)
9592 #define SYSCTL_SRAM_BANKRET_BNK5_RET__1 (0x00000020)
9593 #define SYSCTL_SRAM_BANKRET_BNK6_RET__0 (0x00000000)
9594 #define SYSCTL_SRAM_BANKRET_BNK6_RET__1 (0x00000040)
9595 #define SYSCTL_SRAM_BANKRET_BNK7_RET__0 (0x00000000)
9596 #define SYSCTL_SRAM_BANKRET_BNK7_RET__1 (0x00000080)
9597 #define SYSCTL_SRAM_BANKRET_SRAM_RDY__0 (0x00000000)
9598 #define SYSCTL_SRAM_BANKRET_SRAM_RDY__1 (0x00010000)
9599 #define SYSCTL_WDT_RSTCTL_TIMEOUT__0 (0x00000000)
9600 #define SYSCTL_WDT_RSTCTL_TIMEOUT__1 (0x00000001)
9601 #define SYSCTL_WDT_RSTCTL_VIOLATION__0 (0x00000000)
9602 #define SYSCTL_WDT_RSTCTL_VIOLATION__1 (0x00000002)
9603 #define T32CONTROL1_ENABLE (0x00000080)
9604 #define T32CONTROL1_ENABLE__0 (0x00000000)
9605 #define T32CONTROL1_ENABLE__0_TIMER_DISABLED (0x00000000)
9606 #define T32CONTROL1_ENABLE__1 (0x00000080)
9607 #define T32CONTROL1_ENABLE__1_TIMER_ENABLED (0x00000080)
9608 #define T32CONTROL1_IE (0x00000020)
9609 #define T32CONTROL1_IE__0 (0x00000000)
9610 #define T32CONTROL1_IE__1 (0x00000020)
9611 #define T32CONTROL1_MODE (0x00000040)
9612 #define T32CONTROL1_MODE__0 (0x00000000)
9613 #define T32CONTROL1_MODE__1 (0x00000040)
9614 #define T32CONTROL1_ONESHOT (0x00000001)
9615 #define T32CONTROL1_ONESHOT__0 (0x00000000)
9616 #define T32CONTROL1_ONESHOT__0_WRAPPING_MODE (0x00000000)
9617 #define T32CONTROL1_ONESHOT__1 (0x00000001)
9618 #define T32CONTROL1_ONESHOT__1_ONE_SHOT_MODE (0x00000001)
9619 #define T32CONTROL1_PRESCALE__0 (0x00000000)
9620 #define T32CONTROL1_PRESCALE__1 (0x00000004)
9621 #define T32CONTROL1_PRESCALE__2 (0x00000008)
9622 #define T32CONTROL1_PRESCALE__M (0x0000000c)
9623 #define T32CONTROL1_SIZE (0x00000002)
9624 #define T32CONTROL1_SIZE__0 (0x00000000)
9625 #define T32CONTROL1_SIZE__0_16_BIT_COUNTER (0x00000000)
9626 #define T32CONTROL1_SIZE__1 (0x00000002)
9627 #define T32CONTROL1_SIZE__1_32_BIT_COUNTER (0x00000002)
9628 #define T32CONTROL2_ENABLE (0x00000080)
9629 #define T32CONTROL2_ENABLE__0 (0x00000000)
9630 #define T32CONTROL2_ENABLE__0_TIMER_DISABLED (0x00000000)
9631 #define T32CONTROL2_ENABLE__1 (0x00000080)
9632 #define T32CONTROL2_ENABLE__1_TIMER_ENABLED (0x00000080)
9633 #define T32CONTROL2_IE (0x00000020)
9634 #define T32CONTROL2_IE__0 (0x00000000)
9635 #define T32CONTROL2_IE__1 (0x00000020)
9636 #define T32CONTROL2_MODE (0x00000040)
9637 #define T32CONTROL2_MODE__0 (0x00000000)
9638 #define T32CONTROL2_MODE__1 (0x00000040)
9639 #define T32CONTROL2_ONESHOT (0x00000001)
9640 #define T32CONTROL2_ONESHOT__0 (0x00000000)
9641 #define T32CONTROL2_ONESHOT__0_WRAPPING_MODE (0x00000000)
9642 #define T32CONTROL2_ONESHOT__1 (0x00000001)
9643 #define T32CONTROL2_ONESHOT__1_ONE_SHOT_MODE (0x00000001)
9644 #define T32CONTROL2_PRESCALE__0 (0x00000000)
9645 #define T32CONTROL2_PRESCALE__1 (0x00000004)
9646 #define T32CONTROL2_PRESCALE__2 (0x00000008)
9647 #define T32CONTROL2_PRESCALE__M (0x0000000c)
9648 #define T32CONTROL2_SIZE (0x00000002)
9649 #define T32CONTROL2_SIZE__0 (0x00000000)
9650 #define T32CONTROL2_SIZE__0_16_BIT_COUNTER (0x00000000)
9651 #define T32CONTROL2_SIZE__1 (0x00000002)
9652 #define T32CONTROL2_SIZE__1_32_BIT_COUNTER (0x00000002)
9653 #define T32MIS1_IFG (0x00000001)
9654 #define T32MIS2_IFG (0x00000001)
9655 #define T32RIS1_RAW_IFG (0x00000001)
9656 #define T32RIS2_RAW_IFG (0x00000001)
9657 #define T32_BGLOAD1 (HWREG32(0x4000C018))
9658 #define T32_BGLOAD2 (HWREG32(0x4000C038))
9659 #define T32_CONTROL1 (HWREG32(0x4000C008))
9660 #define T32_CONTROL1_ENABLE (0x00000080)
9661 #define T32_CONTROL1_ENABLE__0 (0x00000000)
9662 #define T32_CONTROL1_ENABLE__0_TIMER_DISABLED (0x00000000)
9663 #define T32_CONTROL1_ENABLE__1 (0x00000080)
9664 #define T32_CONTROL1_ENABLE__1_TIMER_ENABLED (0x00000080)
9665 #define T32_CONTROL1_IE (0x00000020)
9666 #define T32_CONTROL1_IE__0 (0x00000000)
9667 #define T32_CONTROL1_IE__1 (0x00000020)
9668 #define T32_CONTROL1_MODE (0x00000040)
9669 #define T32_CONTROL1_MODE__0 (0x00000000)
9670 #define T32_CONTROL1_MODE__1 (0x00000040)
9671 #define T32_CONTROL1_ONESHOT (0x00000001)
9672 #define T32_CONTROL1_ONESHOT__0 (0x00000000)
9673 #define T32_CONTROL1_ONESHOT__0_WRAPPING_MODE (0x00000000)
9674 #define T32_CONTROL1_ONESHOT__1 (0x00000001)
9675 #define T32_CONTROL1_ONESHOT__1_ONE_SHOT_MODE (0x00000001)
9676 #define T32_CONTROL1_PRESCALE__0 (0x00000000)
9677 #define T32_CONTROL1_PRESCALE__1 (0x00000004)
9678 #define T32_CONTROL1_PRESCALE__2 (0x00000008)
9679 #define T32_CONTROL1_PRESCALE__M (0x0000000c)
9680 #define T32_CONTROL1_SIZE (0x00000002)
9681 #define T32_CONTROL1_SIZE__0 (0x00000000)
9682 #define T32_CONTROL1_SIZE__0_16_BIT_COUNTER (0x00000000)
9683 #define T32_CONTROL1_SIZE__1 (0x00000002)
9684 #define T32_CONTROL1_SIZE__1_32_BIT_COUNTER (0x00000002)
9685 #define T32_CONTROL2 (HWREG32(0x4000C028))
9686 #define T32_CONTROL2_ENABLE (0x00000080)
9687 #define T32_CONTROL2_ENABLE__0 (0x00000000)
9688 #define T32_CONTROL2_ENABLE__0_TIMER_DISABLED (0x00000000)
9689 #define T32_CONTROL2_ENABLE__1 (0x00000080)
9690 #define T32_CONTROL2_ENABLE__1_TIMER_ENABLED (0x00000080)
9691 #define T32_CONTROL2_IE (0x00000020)
9692 #define T32_CONTROL2_IE__0 (0x00000000)
9693 #define T32_CONTROL2_IE__1 (0x00000020)
9694 #define T32_CONTROL2_MODE (0x00000040)
9695 #define T32_CONTROL2_MODE__0 (0x00000000)
9696 #define T32_CONTROL2_MODE__1 (0x00000040)
9697 #define T32_CONTROL2_ONESHOT (0x00000001)
9698 #define T32_CONTROL2_ONESHOT__0 (0x00000000)
9699 #define T32_CONTROL2_ONESHOT__0_WRAPPING_MODE (0x00000000)
9700 #define T32_CONTROL2_ONESHOT__1 (0x00000001)
9701 #define T32_CONTROL2_ONESHOT__1_ONE_SHOT_MODE (0x00000001)
9702 #define T32_CONTROL2_PRESCALE__0 (0x00000000)
9703 #define T32_CONTROL2_PRESCALE__1 (0x00000004)
9704 #define T32_CONTROL2_PRESCALE__2 (0x00000008)
9705 #define T32_CONTROL2_PRESCALE__M (0x0000000c)
9706 #define T32_CONTROL2_SIZE (0x00000002)
9707 #define T32_CONTROL2_SIZE__0 (0x00000000)
9708 #define T32_CONTROL2_SIZE__0_16_BIT_COUNTER (0x00000000)
9709 #define T32_CONTROL2_SIZE__1 (0x00000002)
9710 #define T32_CONTROL2_SIZE__1_32_BIT_COUNTER (0x00000002)
9711 #define T32_INTCLR1 (HWREG32(0x4000C00C))
9712 #define T32_INTCLR2 (HWREG32(0x4000C02C))
9713 #define T32_LOAD1 (HWREG32(0x4000C000))
9714 #define T32_LOAD2 (HWREG32(0x4000C020))
9715 #define T32_MIS1 (HWREG32(0x4000C014))
9716 #define T32_MIS1_IFG (0x00000001)
9717 #define T32_MIS2 (HWREG32(0x4000C034))
9718 #define T32_MIS2_IFG (0x00000001)
9719 #define T32_RIS1 (HWREG32(0x4000C010))
9720 #define T32_RIS1_RAW_IFG (0x00000001)
9721 #define T32_RIS2 (HWREG32(0x4000C030))
9722 #define T32_RIS2_RAW_IFG (0x00000001)
9723 #define T32_VALUE1 (HWREG32(0x4000C004))
9724 #define T32_VALUE2 (HWREG32(0x4000C024))
9725 #define TA0IV_3 (0x0006)
9726 #define TA0IV_4 (0x0008)
9727 #define TA0IV_5 (0x000A)
9728 #define TA0IV_6 (0x000C)
9729 #define TA0IV_NONE (0x0000)
9730 #define TA0IV_TA0CCR1 (0x0002)
9731 #define TA0IV_TA0CCR2 (0x0004)
9732 #define TA0IV_TA0IFG (0x000E)
9733 #define TA0_CCR0 (HWREG16(0x40000012))
9734 #define TA0_CCR1 (HWREG16(0x40000014))
9735 #define TA0_CCR2 (HWREG16(0x40000016))
9736 #define TA0_CCR3 (HWREG16(0x40000018))
9737 #define TA0_CCR4 (HWREG16(0x4000001A))
9738 #define TA0_CCR5 (HWREG16(0x4000001C))
9739 #define TA0_CCR6 (HWREG16(0x4000001E))
9740 #define TA0_CCTL0 (HWREG16(0x40000002))
9741 #define TA0_CCTL1 (HWREG16(0x40000004))
9742 #define TA0_CCTL2 (HWREG16(0x40000006))
9743 #define TA0_CCTL3 (HWREG16(0x40000008))
9744 #define TA0_CCTL4 (HWREG16(0x4000000A))
9745 #define TA0_CCTL5 (HWREG16(0x4000000C))
9746 #define TA0_CCTL6 (HWREG16(0x4000000E))
9747 #define TA0_CCTL_CAP (0x0100)
9748 #define TA0_CCTL_CAP__0 (0x0000)
9749 #define TA0_CCTL_CAP__0_COMPARE_MODE (0x0000)
9750 #define TA0_CCTL_CAP__1 (0x0100)
9751 #define TA0_CCTL_CAP__1_CAPTURE_MODE (0x0100)
9752 #define TA0_CCTL_CCI (0x0008)
9753 #define TA0_CCTL_CCIE (0x0010)
9754 #define TA0_CCTL_CCIE__0 (0x0000)
9755 #define TA0_CCTL_CCIE__1 (0x0010)
9756 #define TA0_CCTL_CCIFG (0x0001)
9757 #define TA0_CCTL_CCIFG__0 (0x0000)
9758 #define TA0_CCTL_CCIFG__1 (0x0001)
9759 #define TA0_CCTL_CCIS__0 (0x0000)
9760 #define TA0_CCTL_CCIS__0_CCIXA (0x0000)
9761 #define TA0_CCTL_CCIS__1 (0x1000)
9762 #define TA0_CCTL_CCIS__1_CCIXB (0x1000)
9763 #define TA0_CCTL_CCIS__2 (0x2000)
9764 #define TA0_CCTL_CCIS__2_GND (0x2000)
9765 #define TA0_CCTL_CCIS__3 (0x3000)
9766 #define TA0_CCTL_CCIS__3_VCC (0x3000)
9767 #define TA0_CCTL_CCIS__M (0x3000)
9768 #define TA0_CCTL_CM__0 (0x0000)
9769 #define TA0_CCTL_CM__0_NO_CAPTURE (0x0000)
9770 #define TA0_CCTL_CM__1 (0x4000)
9771 #define TA0_CCTL_CM__2 (0x8000)
9772 #define TA0_CCTL_CM__3 (0xc000)
9773 #define TA0_CCTL_CM__M (0xc000)
9774 #define TA0_CCTL_COV (0x0002)
9775 #define TA0_CCTL_COV__0 (0x0000)
9776 #define TA0_CCTL_COV__1 (0x0002)
9777 #define TA0_CCTL_OUT (0x0004)
9778 #define TA0_CCTL_OUTMOD__0 (0x0000)
9779 #define TA0_CCTL_OUTMOD__0_OUT_BIT_VALUE (0x0000)
9780 #define TA0_CCTL_OUTMOD__1 (0x0020)
9781 #define TA0_CCTL_OUTMOD__1_SET (0x0020)
9782 #define TA0_CCTL_OUTMOD__2 (0x0040)
9783 #define TA0_CCTL_OUTMOD__2_TOGGLE_RESET (0x0040)
9784 #define TA0_CCTL_OUTMOD__3 (0x0060)
9785 #define TA0_CCTL_OUTMOD__3_SET_RESET (0x0060)
9786 #define TA0_CCTL_OUTMOD__4 (0x0080)
9787 #define TA0_CCTL_OUTMOD__4_TOGGLE (0x0080)
9788 #define TA0_CCTL_OUTMOD__5 (0x00a0)
9789 #define TA0_CCTL_OUTMOD__5_RESET (0x00a0)
9790 #define TA0_CCTL_OUTMOD__6 (0x00c0)
9791 #define TA0_CCTL_OUTMOD__6_TOGGLE_SET (0x00c0)
9792 #define TA0_CCTL_OUTMOD__7 (0x00e0)
9793 #define TA0_CCTL_OUTMOD__7_RESET_SET (0x00e0)
9794 #define TA0_CCTL_OUTMOD__M (0x00e0)
9795 #define TA0_CCTL_OUT__0 (0x0000)
9796 #define TA0_CCTL_OUT__0_OUTPUT_LOW (0x0000)
9797 #define TA0_CCTL_OUT__1 (0x0004)
9798 #define TA0_CCTL_OUT__1_OUTPUT_HIGH (0x0004)
9799 #define TA0_CCTL_SCCI (0x0400)
9800 #define TA0_CCTL_SCS (0x0800)
9801 #define TA0_CCTL_SCS__0 (0x0000)
9802 #define TA0_CCTL_SCS__1 (0x0800)
9803 #define TA0_CTL (HWREG16(0x40000000))
9804 #define TA0_CTL_ID__0 (0x0000)
9805 #define TA0_CTL_ID__0__1 (0x0000)
9806 #define TA0_CTL_ID__1 (0x0040)
9807 #define TA0_CTL_ID__1__2 (0x0040)
9808 #define TA0_CTL_ID__2 (0x0080)
9809 #define TA0_CTL_ID__2__4 (0x0080)
9810 #define TA0_CTL_ID__3 (0x00c0)
9811 #define TA0_CTL_ID__3__8 (0x00c0)
9812 #define TA0_CTL_ID__M (0x00c0)
9813 #define TA0_CTL_MC__0 (0x0000)
9814 #define TA0_CTL_MC__1 (0x0010)
9815 #define TA0_CTL_MC__2 (0x0020)
9816 #define TA0_CTL_MC__3 (0x0030)
9817 #define TA0_CTL_MC__M (0x0030)
9818 #define TA0_CTL_TACLR (0x0004)
9819 #define TA0_CTL_TAIE (0x0002)
9820 #define TA0_CTL_TAIE__0 (0x0000)
9821 #define TA0_CTL_TAIE__1 (0x0002)
9822 #define TA0_CTL_TAIFG (0x0001)
9823 #define TA0_CTL_TAIFG__0 (0x0000)
9824 #define TA0_CTL_TAIFG__1 (0x0001)
9825 #define TA0_CTL_TASSEL__0 (0x0000)
9826 #define TA0_CTL_TASSEL__0_TAXCLK (0x0000)
9827 #define TA0_CTL_TASSEL__1 (0x0100)
9828 #define TA0_CTL_TASSEL__1_ACLK (0x0100)
9829 #define TA0_CTL_TASSEL__2 (0x0200)
9830 #define TA0_CTL_TASSEL__2_SMCLK (0x0200)
9831 #define TA0_CTL_TASSEL__3 (0x0300)
9832 #define TA0_CTL_TASSEL__3_INCLK (0x0300)
9833 #define TA0_CTL_TASSEL__M (0x0300)
9834 #define TA0_EX0 (HWREG16(0x40000020))
9835 #define TA0_EX0_TAIDEX__0 (0x0000)
9836 #define TA0_EX0_TAIDEX__0_DIVIDE_BY_1 (0x0000)
9837 #define TA0_EX0_TAIDEX__1 (0x0001)
9838 #define TA0_EX0_TAIDEX__1_DIVIDE_BY_2 (0x0001)
9839 #define TA0_EX0_TAIDEX__2 (0x0002)
9840 #define TA0_EX0_TAIDEX__2_DIVIDE_BY_3 (0x0002)
9841 #define TA0_EX0_TAIDEX__3 (0x0003)
9842 #define TA0_EX0_TAIDEX__3_DIVIDE_BY_4 (0x0003)
9843 #define TA0_EX0_TAIDEX__4 (0x0004)
9844 #define TA0_EX0_TAIDEX__4_DIVIDE_BY_5 (0x0004)
9845 #define TA0_EX0_TAIDEX__5 (0x0005)
9846 #define TA0_EX0_TAIDEX__5_DIVIDE_BY_6 (0x0005)
9847 #define TA0_EX0_TAIDEX__6 (0x0006)
9848 #define TA0_EX0_TAIDEX__6_DIVIDE_BY_7 (0x0006)
9849 #define TA0_EX0_TAIDEX__7 (0x0007)
9850 #define TA0_EX0_TAIDEX__7_DIVIDE_BY_8 (0x0007)
9851 #define TA0_EX0_TAIDEX__M (0x0007)
9852 #define TA0_IV (HWREG16(0x4000002E))
9853 #define TA0_R (HWREG16(0x40000010))
9854 #define TA1_CCR0 (HWREG16(0x40000412))
9855 #define TA1_CCR1 (HWREG16(0x40000414))
9856 #define TA1_CCR2 (HWREG16(0x40000416))
9857 #define TA1_CCR3 (HWREG16(0x40000418))
9858 #define TA1_CCR4 (HWREG16(0x4000041A))
9859 #define TA1_CCR5 (HWREG16(0x4000041C))
9860 #define TA1_CCR6 (HWREG16(0x4000041E))
9861 #define TA1_CCTL0 (HWREG16(0x40000402))
9862 #define TA1_CCTL1 (HWREG16(0x40000404))
9863 #define TA1_CCTL2 (HWREG16(0x40000406))
9864 #define TA1_CCTL3 (HWREG16(0x40000408))
9865 #define TA1_CCTL4 (HWREG16(0x4000040A))
9866 #define TA1_CCTL5 (HWREG16(0x4000040C))
9867 #define TA1_CCTL6 (HWREG16(0x4000040E))
9868 #define TA1_CCTL_CAP (0x0100)
9869 #define TA1_CCTL_CAP__0 (0x0000)
9870 #define TA1_CCTL_CAP__0_COMPARE_MODE (0x0000)
9871 #define TA1_CCTL_CAP__1 (0x0100)
9872 #define TA1_CCTL_CAP__1_CAPTURE_MODE (0x0100)
9873 #define TA1_CCTL_CCI (0x0008)
9874 #define TA1_CCTL_CCIE (0x0010)
9875 #define TA1_CCTL_CCIE__0 (0x0000)
9876 #define TA1_CCTL_CCIE__1 (0x0010)
9877 #define TA1_CCTL_CCIFG (0x0001)
9878 #define TA1_CCTL_CCIFG__0 (0x0000)
9879 #define TA1_CCTL_CCIFG__1 (0x0001)
9880 #define TA1_CCTL_CCIS__0 (0x0000)
9881 #define TA1_CCTL_CCIS__0_CCIXA (0x0000)
9882 #define TA1_CCTL_CCIS__1 (0x1000)
9883 #define TA1_CCTL_CCIS__1_CCIXB (0x1000)
9884 #define TA1_CCTL_CCIS__2 (0x2000)
9885 #define TA1_CCTL_CCIS__2_GND (0x2000)
9886 #define TA1_CCTL_CCIS__3 (0x3000)
9887 #define TA1_CCTL_CCIS__3_VCC (0x3000)
9888 #define TA1_CCTL_CCIS__M (0x3000)
9889 #define TA1_CCTL_CM__0 (0x0000)
9890 #define TA1_CCTL_CM__0_NO_CAPTURE (0x0000)
9891 #define TA1_CCTL_CM__1 (0x4000)
9892 #define TA1_CCTL_CM__2 (0x8000)
9893 #define TA1_CCTL_CM__3 (0xc000)
9894 #define TA1_CCTL_CM__M (0xc000)
9895 #define TA1_CCTL_COV (0x0002)
9896 #define TA1_CCTL_COV__0 (0x0000)
9897 #define TA1_CCTL_COV__1 (0x0002)
9898 #define TA1_CCTL_OUT (0x0004)
9899 #define TA1_CCTL_OUTMOD__0 (0x0000)
9900 #define TA1_CCTL_OUTMOD__0_OUT_BIT_VALUE (0x0000)
9901 #define TA1_CCTL_OUTMOD__1 (0x0020)
9902 #define TA1_CCTL_OUTMOD__1_SET (0x0020)
9903 #define TA1_CCTL_OUTMOD__2 (0x0040)
9904 #define TA1_CCTL_OUTMOD__2_TOGGLE_RESET (0x0040)
9905 #define TA1_CCTL_OUTMOD__3 (0x0060)
9906 #define TA1_CCTL_OUTMOD__3_SET_RESET (0x0060)
9907 #define TA1_CCTL_OUTMOD__4 (0x0080)
9908 #define TA1_CCTL_OUTMOD__4_TOGGLE (0x0080)
9909 #define TA1_CCTL_OUTMOD__5 (0x00a0)
9910 #define TA1_CCTL_OUTMOD__5_RESET (0x00a0)
9911 #define TA1_CCTL_OUTMOD__6 (0x00c0)
9912 #define TA1_CCTL_OUTMOD__6_TOGGLE_SET (0x00c0)
9913 #define TA1_CCTL_OUTMOD__7 (0x00e0)
9914 #define TA1_CCTL_OUTMOD__7_RESET_SET (0x00e0)
9915 #define TA1_CCTL_OUTMOD__M (0x00e0)
9916 #define TA1_CCTL_OUT__0 (0x0000)
9917 #define TA1_CCTL_OUT__0_OUTPUT_LOW (0x0000)
9918 #define TA1_CCTL_OUT__1 (0x0004)
9919 #define TA1_CCTL_OUT__1_OUTPUT_HIGH (0x0004)
9920 #define TA1_CCTL_SCCI (0x0400)
9921 #define TA1_CCTL_SCS (0x0800)
9922 #define TA1_CCTL_SCS__0 (0x0000)
9923 #define TA1_CCTL_SCS__1 (0x0800)
9924 #define TA1_CTL (HWREG16(0x40000400))
9925 #define TA1_CTL_ID__0 (0x0000)
9926 #define TA1_CTL_ID__0__1 (0x0000)
9927 #define TA1_CTL_ID__1 (0x0040)
9928 #define TA1_CTL_ID__1__2 (0x0040)
9929 #define TA1_CTL_ID__2 (0x0080)
9930 #define TA1_CTL_ID__2__4 (0x0080)
9931 #define TA1_CTL_ID__3 (0x00c0)
9932 #define TA1_CTL_ID__3__8 (0x00c0)
9933 #define TA1_CTL_ID__M (0x00c0)
9934 #define TA1_CTL_MC__0 (0x0000)
9935 #define TA1_CTL_MC__1 (0x0010)
9936 #define TA1_CTL_MC__2 (0x0020)
9937 #define TA1_CTL_MC__3 (0x0030)
9938 #define TA1_CTL_MC__M (0x0030)
9939 #define TA1_CTL_TACLR (0x0004)
9940 #define TA1_CTL_TAIE (0x0002)
9941 #define TA1_CTL_TAIE__0 (0x0000)
9942 #define TA1_CTL_TAIE__1 (0x0002)
9943 #define TA1_CTL_TAIFG (0x0001)
9944 #define TA1_CTL_TAIFG__0 (0x0000)
9945 #define TA1_CTL_TAIFG__1 (0x0001)
9946 #define TA1_CTL_TASSEL__0 (0x0000)
9947 #define TA1_CTL_TASSEL__0_TAXCLK (0x0000)
9948 #define TA1_CTL_TASSEL__1 (0x0100)
9949 #define TA1_CTL_TASSEL__1_ACLK (0x0100)
9950 #define TA1_CTL_TASSEL__2 (0x0200)
9951 #define TA1_CTL_TASSEL__2_SMCLK (0x0200)
9952 #define TA1_CTL_TASSEL__3 (0x0300)
9953 #define TA1_CTL_TASSEL__3_INCLK (0x0300)
9954 #define TA1_CTL_TASSEL__M (0x0300)
9955 #define TA1_EX0 (HWREG16(0x40000420))
9956 #define TA1_EX0_TAIDEX__0 (0x0000)
9957 #define TA1_EX0_TAIDEX__0_DIVIDE_BY_1 (0x0000)
9958 #define TA1_EX0_TAIDEX__1 (0x0001)
9959 #define TA1_EX0_TAIDEX__1_DIVIDE_BY_2 (0x0001)
9960 #define TA1_EX0_TAIDEX__2 (0x0002)
9961 #define TA1_EX0_TAIDEX__2_DIVIDE_BY_3 (0x0002)
9962 #define TA1_EX0_TAIDEX__3 (0x0003)
9963 #define TA1_EX0_TAIDEX__3_DIVIDE_BY_4 (0x0003)
9964 #define TA1_EX0_TAIDEX__4 (0x0004)
9965 #define TA1_EX0_TAIDEX__4_DIVIDE_BY_5 (0x0004)
9966 #define TA1_EX0_TAIDEX__5 (0x0005)
9967 #define TA1_EX0_TAIDEX__5_DIVIDE_BY_6 (0x0005)
9968 #define TA1_EX0_TAIDEX__6 (0x0006)
9969 #define TA1_EX0_TAIDEX__6_DIVIDE_BY_7 (0x0006)
9970 #define TA1_EX0_TAIDEX__7 (0x0007)
9971 #define TA1_EX0_TAIDEX__7_DIVIDE_BY_8 (0x0007)
9972 #define TA1_EX0_TAIDEX__M (0x0007)
9973 #define TA1_IV (HWREG16(0x4000042E))
9974 #define TA1_R (HWREG16(0x40000410))
9975 #define TA2_CCR0 (HWREG16(0x40000812))
9976 #define TA2_CCR1 (HWREG16(0x40000814))
9977 #define TA2_CCR2 (HWREG16(0x40000816))
9978 #define TA2_CCR3 (HWREG16(0x40000818))
9979 #define TA2_CCR4 (HWREG16(0x4000081A))
9980 #define TA2_CCR5 (HWREG16(0x4000081C))
9981 #define TA2_CCR6 (HWREG16(0x4000081E))
9982 #define TA2_CCTL0 (HWREG16(0x40000802))
9983 #define TA2_CCTL1 (HWREG16(0x40000804))
9984 #define TA2_CCTL2 (HWREG16(0x40000806))
9985 #define TA2_CCTL3 (HWREG16(0x40000808))
9986 #define TA2_CCTL4 (HWREG16(0x4000080A))
9987 #define TA2_CCTL5 (HWREG16(0x4000080C))
9988 #define TA2_CCTL6 (HWREG16(0x4000080E))
9989 #define TA2_CCTL_CAP (0x0100)
9990 #define TA2_CCTL_CAP__0 (0x0000)
9991 #define TA2_CCTL_CAP__0_COMPARE_MODE (0x0000)
9992 #define TA2_CCTL_CAP__1 (0x0100)
9993 #define TA2_CCTL_CAP__1_CAPTURE_MODE (0x0100)
9994 #define TA2_CCTL_CCI (0x0008)
9995 #define TA2_CCTL_CCIE (0x0010)
9996 #define TA2_CCTL_CCIE__0 (0x0000)
9997 #define TA2_CCTL_CCIE__1 (0x0010)
9998 #define TA2_CCTL_CCIFG (0x0001)
9999 #define TA2_CCTL_CCIFG__0 (0x0000)
10000 #define TA2_CCTL_CCIFG__1 (0x0001)
10001 #define TA2_CCTL_CCIS__0 (0x0000)
10002 #define TA2_CCTL_CCIS__0_CCIXA (0x0000)
10003 #define TA2_CCTL_CCIS__1 (0x1000)
10004 #define TA2_CCTL_CCIS__1_CCIXB (0x1000)
10005 #define TA2_CCTL_CCIS__2 (0x2000)
10006 #define TA2_CCTL_CCIS__2_GND (0x2000)
10007 #define TA2_CCTL_CCIS__3 (0x3000)
10008 #define TA2_CCTL_CCIS__3_VCC (0x3000)
10009 #define TA2_CCTL_CCIS__M (0x3000)
10010 #define TA2_CCTL_CM__0 (0x0000)
10011 #define TA2_CCTL_CM__0_NO_CAPTURE (0x0000)
10012 #define TA2_CCTL_CM__1 (0x4000)
10013 #define TA2_CCTL_CM__2 (0x8000)
10014 #define TA2_CCTL_CM__3 (0xc000)
10015 #define TA2_CCTL_CM__M (0xc000)
10016 #define TA2_CCTL_COV (0x0002)
10017 #define TA2_CCTL_COV__0 (0x0000)
10018 #define TA2_CCTL_COV__1 (0x0002)
10019 #define TA2_CCTL_OUT (0x0004)
10020 #define TA2_CCTL_OUTMOD__0 (0x0000)
10021 #define TA2_CCTL_OUTMOD__0_OUT_BIT_VALUE (0x0000)
10022 #define TA2_CCTL_OUTMOD__1 (0x0020)
10023 #define TA2_CCTL_OUTMOD__1_SET (0x0020)
10024 #define TA2_CCTL_OUTMOD__2 (0x0040)
10025 #define TA2_CCTL_OUTMOD__2_TOGGLE_RESET (0x0040)
10026 #define TA2_CCTL_OUTMOD__3 (0x0060)
10027 #define TA2_CCTL_OUTMOD__3_SET_RESET (0x0060)
10028 #define TA2_CCTL_OUTMOD__4 (0x0080)
10029 #define TA2_CCTL_OUTMOD__4_TOGGLE (0x0080)
10030 #define TA2_CCTL_OUTMOD__5 (0x00a0)
10031 #define TA2_CCTL_OUTMOD__5_RESET (0x00a0)
10032 #define TA2_CCTL_OUTMOD__6 (0x00c0)
10033 #define TA2_CCTL_OUTMOD__6_TOGGLE_SET (0x00c0)
10034 #define TA2_CCTL_OUTMOD__7 (0x00e0)
10035 #define TA2_CCTL_OUTMOD__7_RESET_SET (0x00e0)
10036 #define TA2_CCTL_OUTMOD__M (0x00e0)
10037 #define TA2_CCTL_OUT__0 (0x0000)
10038 #define TA2_CCTL_OUT__0_OUTPUT_LOW (0x0000)
10039 #define TA2_CCTL_OUT__1 (0x0004)
10040 #define TA2_CCTL_OUT__1_OUTPUT_HIGH (0x0004)
10041 #define TA2_CCTL_SCCI (0x0400)
10042 #define TA2_CCTL_SCS (0x0800)
10043 #define TA2_CCTL_SCS__0 (0x0000)
10044 #define TA2_CCTL_SCS__1 (0x0800)
10045 #define TA2_CTL (HWREG16(0x40000800))
10046 #define TA2_CTL_ID__0 (0x0000)
10047 #define TA2_CTL_ID__0__1 (0x0000)
10048 #define TA2_CTL_ID__1 (0x0040)
10049 #define TA2_CTL_ID__1__2 (0x0040)
10050 #define TA2_CTL_ID__2 (0x0080)
10051 #define TA2_CTL_ID__2__4 (0x0080)
10052 #define TA2_CTL_ID__3 (0x00c0)
10053 #define TA2_CTL_ID__3__8 (0x00c0)
10054 #define TA2_CTL_ID__M (0x00c0)
10055 #define TA2_CTL_MC__0 (0x0000)
10056 #define TA2_CTL_MC__1 (0x0010)
10057 #define TA2_CTL_MC__2 (0x0020)
10058 #define TA2_CTL_MC__3 (0x0030)
10059 #define TA2_CTL_MC__M (0x0030)
10060 #define TA2_CTL_TACLR (0x0004)
10061 #define TA2_CTL_TAIE (0x0002)
10062 #define TA2_CTL_TAIE__0 (0x0000)
10063 #define TA2_CTL_TAIE__1 (0x0002)
10064 #define TA2_CTL_TAIFG (0x0001)
10065 #define TA2_CTL_TAIFG__0 (0x0000)
10066 #define TA2_CTL_TAIFG__1 (0x0001)
10067 #define TA2_CTL_TASSEL__0 (0x0000)
10068 #define TA2_CTL_TASSEL__0_TAXCLK (0x0000)
10069 #define TA2_CTL_TASSEL__1 (0x0100)
10070 #define TA2_CTL_TASSEL__1_ACLK (0x0100)
10071 #define TA2_CTL_TASSEL__2 (0x0200)
10072 #define TA2_CTL_TASSEL__2_SMCLK (0x0200)
10073 #define TA2_CTL_TASSEL__3 (0x0300)
10074 #define TA2_CTL_TASSEL__3_INCLK (0x0300)
10075 #define TA2_CTL_TASSEL__M (0x0300)
10076 #define TA2_EX0 (HWREG16(0x40000820))
10077 #define TA2_EX0_TAIDEX__0 (0x0000)
10078 #define TA2_EX0_TAIDEX__0_DIVIDE_BY_1 (0x0000)
10079 #define TA2_EX0_TAIDEX__1 (0x0001)
10080 #define TA2_EX0_TAIDEX__1_DIVIDE_BY_2 (0x0001)
10081 #define TA2_EX0_TAIDEX__2 (0x0002)
10082 #define TA2_EX0_TAIDEX__2_DIVIDE_BY_3 (0x0002)
10083 #define TA2_EX0_TAIDEX__3 (0x0003)
10084 #define TA2_EX0_TAIDEX__3_DIVIDE_BY_4 (0x0003)
10085 #define TA2_EX0_TAIDEX__4 (0x0004)
10086 #define TA2_EX0_TAIDEX__4_DIVIDE_BY_5 (0x0004)
10087 #define TA2_EX0_TAIDEX__5 (0x0005)
10088 #define TA2_EX0_TAIDEX__5_DIVIDE_BY_6 (0x0005)
10089 #define TA2_EX0_TAIDEX__6 (0x0006)
10090 #define TA2_EX0_TAIDEX__6_DIVIDE_BY_7 (0x0006)
10091 #define TA2_EX0_TAIDEX__7 (0x0007)
10092 #define TA2_EX0_TAIDEX__7_DIVIDE_BY_8 (0x0007)
10093 #define TA2_EX0_TAIDEX__M (0x0007)
10094 #define TA2_IV (HWREG16(0x4000082E))
10095 #define TA2_R (HWREG16(0x40000810))
10096 #define TA3_CCR0 (HWREG16(0x40000C12))
10097 #define TA3_CCR1 (HWREG16(0x40000C14))
10098 #define TA3_CCR2 (HWREG16(0x40000C16))
10099 #define TA3_CCR3 (HWREG16(0x40000C18))
10100 #define TA3_CCR4 (HWREG16(0x40000C1A))
10101 #define TA3_CCR5 (HWREG16(0x40000C1C))
10102 #define TA3_CCR6 (HWREG16(0x40000C1E))
10103 #define TA3_CCTL0 (HWREG16(0x40000C02))
10104 #define TA3_CCTL1 (HWREG16(0x40000C04))
10105 #define TA3_CCTL2 (HWREG16(0x40000C06))
10106 #define TA3_CCTL3 (HWREG16(0x40000C08))
10107 #define TA3_CCTL4 (HWREG16(0x40000C0A))
10108 #define TA3_CCTL5 (HWREG16(0x40000C0C))
10109 #define TA3_CCTL6 (HWREG16(0x40000C0E))
10110 #define TA3_CCTL_CAP (0x0100)
10111 #define TA3_CCTL_CAP__0 (0x0000)
10112 #define TA3_CCTL_CAP__0_COMPARE_MODE (0x0000)
10113 #define TA3_CCTL_CAP__1 (0x0100)
10114 #define TA3_CCTL_CAP__1_CAPTURE_MODE (0x0100)
10115 #define TA3_CCTL_CCI (0x0008)
10116 #define TA3_CCTL_CCIE (0x0010)
10117 #define TA3_CCTL_CCIE__0 (0x0000)
10118 #define TA3_CCTL_CCIE__1 (0x0010)
10119 #define TA3_CCTL_CCIFG (0x0001)
10120 #define TA3_CCTL_CCIFG__0 (0x0000)
10121 #define TA3_CCTL_CCIFG__1 (0x0001)
10122 #define TA3_CCTL_CCIS__0 (0x0000)
10123 #define TA3_CCTL_CCIS__0_CCIXA (0x0000)
10124 #define TA3_CCTL_CCIS__1 (0x1000)
10125 #define TA3_CCTL_CCIS__1_CCIXB (0x1000)
10126 #define TA3_CCTL_CCIS__2 (0x2000)
10127 #define TA3_CCTL_CCIS__2_GND (0x2000)
10128 #define TA3_CCTL_CCIS__3 (0x3000)
10129 #define TA3_CCTL_CCIS__3_VCC (0x3000)
10130 #define TA3_CCTL_CCIS__M (0x3000)
10131 #define TA3_CCTL_CM__0 (0x0000)
10132 #define TA3_CCTL_CM__0_NO_CAPTURE (0x0000)
10133 #define TA3_CCTL_CM__1 (0x4000)
10134 #define TA3_CCTL_CM__2 (0x8000)
10135 #define TA3_CCTL_CM__3 (0xc000)
10136 #define TA3_CCTL_CM__M (0xc000)
10137 #define TA3_CCTL_COV (0x0002)
10138 #define TA3_CCTL_COV__0 (0x0000)
10139 #define TA3_CCTL_COV__1 (0x0002)
10140 #define TA3_CCTL_OUT (0x0004)
10141 #define TA3_CCTL_OUTMOD__0 (0x0000)
10142 #define TA3_CCTL_OUTMOD__0_OUT_BIT_VALUE (0x0000)
10143 #define TA3_CCTL_OUTMOD__1 (0x0020)
10144 #define TA3_CCTL_OUTMOD__1_SET (0x0020)
10145 #define TA3_CCTL_OUTMOD__2 (0x0040)
10146 #define TA3_CCTL_OUTMOD__2_TOGGLE_RESET (0x0040)
10147 #define TA3_CCTL_OUTMOD__3 (0x0060)
10148 #define TA3_CCTL_OUTMOD__3_SET_RESET (0x0060)
10149 #define TA3_CCTL_OUTMOD__4 (0x0080)
10150 #define TA3_CCTL_OUTMOD__4_TOGGLE (0x0080)
10151 #define TA3_CCTL_OUTMOD__5 (0x00a0)
10152 #define TA3_CCTL_OUTMOD__5_RESET (0x00a0)
10153 #define TA3_CCTL_OUTMOD__6 (0x00c0)
10154 #define TA3_CCTL_OUTMOD__6_TOGGLE_SET (0x00c0)
10155 #define TA3_CCTL_OUTMOD__7 (0x00e0)
10156 #define TA3_CCTL_OUTMOD__7_RESET_SET (0x00e0)
10157 #define TA3_CCTL_OUTMOD__M (0x00e0)
10158 #define TA3_CCTL_OUT__0 (0x0000)
10159 #define TA3_CCTL_OUT__0_OUTPUT_LOW (0x0000)
10160 #define TA3_CCTL_OUT__1 (0x0004)
10161 #define TA3_CCTL_OUT__1_OUTPUT_HIGH (0x0004)
10162 #define TA3_CCTL_SCCI (0x0400)
10163 #define TA3_CCTL_SCS (0x0800)
10164 #define TA3_CCTL_SCS__0 (0x0000)
10165 #define TA3_CCTL_SCS__1 (0x0800)
10166 #define TA3_CTL (HWREG16(0x40000C00))
10167 #define TA3_CTL_ID__0 (0x0000)
10168 #define TA3_CTL_ID__0__1 (0x0000)
10169 #define TA3_CTL_ID__1 (0x0040)
10170 #define TA3_CTL_ID__1__2 (0x0040)
10171 #define TA3_CTL_ID__2 (0x0080)
10172 #define TA3_CTL_ID__2__4 (0x0080)
10173 #define TA3_CTL_ID__3 (0x00c0)
10174 #define TA3_CTL_ID__3__8 (0x00c0)
10175 #define TA3_CTL_ID__M (0x00c0)
10176 #define TA3_CTL_MC__0 (0x0000)
10177 #define TA3_CTL_MC__1 (0x0010)
10178 #define TA3_CTL_MC__2 (0x0020)
10179 #define TA3_CTL_MC__3 (0x0030)
10180 #define TA3_CTL_MC__M (0x0030)
10181 #define TA3_CTL_TACLR (0x0004)
10182 #define TA3_CTL_TAIE (0x0002)
10183 #define TA3_CTL_TAIE__0 (0x0000)
10184 #define TA3_CTL_TAIE__1 (0x0002)
10185 #define TA3_CTL_TAIFG (0x0001)
10186 #define TA3_CTL_TAIFG__0 (0x0000)
10187 #define TA3_CTL_TAIFG__1 (0x0001)
10188 #define TA3_CTL_TASSEL__0 (0x0000)
10189 #define TA3_CTL_TASSEL__0_TAXCLK (0x0000)
10190 #define TA3_CTL_TASSEL__1 (0x0100)
10191 #define TA3_CTL_TASSEL__1_ACLK (0x0100)
10192 #define TA3_CTL_TASSEL__2 (0x0200)
10193 #define TA3_CTL_TASSEL__2_SMCLK (0x0200)
10194 #define TA3_CTL_TASSEL__3 (0x0300)
10195 #define TA3_CTL_TASSEL__3_INCLK (0x0300)
10196 #define TA3_CTL_TASSEL__M (0x0300)
10197 #define TA3_EX0 (HWREG16(0x40000C20))
10198 #define TA3_EX0_TAIDEX__0 (0x0000)
10199 #define TA3_EX0_TAIDEX__0_DIVIDE_BY_1 (0x0000)
10200 #define TA3_EX0_TAIDEX__1 (0x0001)
10201 #define TA3_EX0_TAIDEX__1_DIVIDE_BY_2 (0x0001)
10202 #define TA3_EX0_TAIDEX__2 (0x0002)
10203 #define TA3_EX0_TAIDEX__2_DIVIDE_BY_3 (0x0002)
10204 #define TA3_EX0_TAIDEX__3 (0x0003)
10205 #define TA3_EX0_TAIDEX__3_DIVIDE_BY_4 (0x0003)
10206 #define TA3_EX0_TAIDEX__4 (0x0004)
10207 #define TA3_EX0_TAIDEX__4_DIVIDE_BY_5 (0x0004)
10208 #define TA3_EX0_TAIDEX__5 (0x0005)
10209 #define TA3_EX0_TAIDEX__5_DIVIDE_BY_6 (0x0005)
10210 #define TA3_EX0_TAIDEX__6 (0x0006)
10211 #define TA3_EX0_TAIDEX__6_DIVIDE_BY_7 (0x0006)
10212 #define TA3_EX0_TAIDEX__7 (0x0007)
10213 #define TA3_EX0_TAIDEX__7_DIVIDE_BY_8 (0x0007)
10214 #define TA3_EX0_TAIDEX__M (0x0007)
10215 #define TA3_IV (HWREG16(0x40000C2E))
10216 #define TA3_R (HWREG16(0x40000C10))
10217 #define TAIDEX0 (0x0001)
10218 #define TAIDEX1 (0x0002)
10219 #define TAIDEX2 (0x0004)
10220 #define TASSEL0 (0x0100)
10221 #define TASSEL1 (0x0200)
10222 #define TCEN (0x0001)
10223 #define UC7BIT_H (0x0010)
10224 #define UCA0BRW_H (HWREG8_H(UCA0BRW))
10225 #define UCA0BRW_L (HWREG8_L(UCA0BRW))
10228 #define UCA0CTLW1_H (HWREG8_H(UCA0CTLW1))
10229 #define UCA0CTLW1_L (HWREG8_L(UCA0CTLW1))
10230 #define UCA0IE_H (HWREG8_H(UCA0IE))
10231 #define UCA0IE_L (HWREG8_L(UCA0IE))
10232 #define UCA0IFG_H (HWREG8_H(UCA0IFG))
10233 #define UCA0IFG_L (HWREG8_L(UCA0IFG))
10234 #define UCA0IRCTL_H (HWREG8_H(UCA0IRCTL))
10235 #define UCA0IRCTL_L (HWREG8_L(UCA0IRCTL))
10236 #define UCA0MCTLW_H (HWREG8_H(UCA0MCTLW))
10237 #define UCA0MCTLW_L (HWREG8_L(UCA0MCTLW))
10238 #define UCA0RXBUF_H (HWREG8_H(UCA0RXBUF))
10239 #define UCA0RXBUF_L (HWREG8_L(UCA0RXBUF))
10240 #define UCA0TXBUF_H (HWREG8_H(UCA0TXBUF))
10241 #define UCA0TXBUF_L (HWREG8_L(UCA0TXBUF))
10242 #define UCA10_H (0x0080)
10243 #define UCA1BRW_H (HWREG8_H(UCA1BRW))
10244 #define UCA1BRW_L (HWREG8_L(UCA1BRW))
10247 #define UCA1CTLW1_H (HWREG8_H(UCA1CTLW1))
10248 #define UCA1CTLW1_L (HWREG8_L(UCA1CTLW1))
10249 #define UCA1IE_H (HWREG8_H(UCA1IE))
10250 #define UCA1IE_L (HWREG8_L(UCA1IE))
10251 #define UCA1IFG_H (HWREG8_H(UCA1IFG))
10252 #define UCA1IFG_L (HWREG8_L(UCA1IFG))
10253 #define UCA1IRCTL_H (HWREG8_H(UCA1IRCTL))
10254 #define UCA1IRCTL_L (HWREG8_L(UCA1IRCTL))
10255 #define UCA1MCTLW_H (HWREG8_H(UCA1MCTLW))
10256 #define UCA1MCTLW_L (HWREG8_L(UCA1MCTLW))
10257 #define UCA1RXBUF_H (HWREG8_H(UCA1RXBUF))
10258 #define UCA1RXBUF_L (HWREG8_L(UCA1RXBUF))
10259 #define UCA1TXBUF_H (HWREG8_H(UCA1TXBUF))
10260 #define UCA1TXBUF_L (HWREG8_L(UCA1TXBUF))
10261 #define UCA2BRW_H (HWREG8_H(UCA2BRW))
10262 #define UCA2BRW_L (HWREG8_L(UCA2BRW))
10265 #define UCA2CTLW1_H (HWREG8_H(UCA2CTLW1))
10266 #define UCA2CTLW1_L (HWREG8_L(UCA2CTLW1))
10267 #define UCA2IE_H (HWREG8_H(UCA2IE))
10268 #define UCA2IE_L (HWREG8_L(UCA2IE))
10269 #define UCA2IFG_H (HWREG8_H(UCA2IFG))
10270 #define UCA2IFG_L (HWREG8_L(UCA2IFG))
10271 #define UCA2IRCTL_H (HWREG8_H(UCA2IRCTL))
10272 #define UCA2IRCTL_L (HWREG8_L(UCA2IRCTL))
10273 #define UCA2MCTLW_H (HWREG8_H(UCA2MCTLW))
10274 #define UCA2MCTLW_L (HWREG8_L(UCA2MCTLW))
10275 #define UCA2RXBUF_H (HWREG8_H(UCA2RXBUF))
10276 #define UCA2RXBUF_L (HWREG8_L(UCA2RXBUF))
10277 #define UCA2TXBUF_H (HWREG8_H(UCA2TXBUF))
10278 #define UCA2TXBUF_L (HWREG8_L(UCA2TXBUF))
10279 #define UCA3BRW_H (HWREG8_H(UCA3BRW))
10280 #define UCA3BRW_L (HWREG8_L(UCA3BRW))
10283 #define UCA3CTLW1_H (HWREG8_H(UCA3CTLW1))
10284 #define UCA3CTLW1_L (HWREG8_L(UCA3CTLW1))
10285 #define UCA3IE_H (HWREG8_H(UCA3IE))
10286 #define UCA3IE_L (HWREG8_L(UCA3IE))
10287 #define UCA3IFG_H (HWREG8_H(UCA3IFG))
10288 #define UCA3IFG_L (HWREG8_L(UCA3IFG))
10289 #define UCA3IRCTL_H (HWREG8_H(UCA3IRCTL))
10290 #define UCA3IRCTL_L (HWREG8_L(UCA3IRCTL))
10291 #define UCA3MCTLW_H (HWREG8_H(UCA3MCTLW))
10292 #define UCA3MCTLW_L (HWREG8_L(UCA3MCTLW))
10293 #define UCA3RXBUF_H (HWREG8_H(UCA3RXBUF))
10294 #define UCA3RXBUF_L (HWREG8_L(UCA3RXBUF))
10295 #define UCA3TXBUF_H (HWREG8_H(UCA3TXBUF))
10296 #define UCA3TXBUF_L (HWREG8_L(UCA3TXBUF))
10297 #define UCADDMASK0 (0x0001)
10298 #define UCADDMASK0_L (0x0001)
10299 #define UCADDMASK1 (0x0002)
10300 #define UCADDMASK1_L (0x0002)
10301 #define UCADDMASK2 (0x0004)
10302 #define UCADDMASK2_L (0x0004)
10303 #define UCADDMASK3 (0x0008)
10304 #define UCADDMASK3_L (0x0008)
10305 #define UCADDMASK4 (0x0010)
10306 #define UCADDMASK4_L (0x0010)
10307 #define UCADDMASK5 (0x0020)
10308 #define UCADDMASK5_L (0x0020)
10309 #define UCADDMASK6 (0x0040)
10310 #define UCADDMASK6_L (0x0040)
10311 #define UCADDMASK7 (0x0080)
10312 #define UCADDMASK7_L (0x0080)
10313 #define UCADDMASK8 (0x0100)
10314 #define UCADDMASK8_H (0x0001)
10315 #define UCADDMASK9 (0x0200)
10316 #define UCADDMASK9_H (0x0002)
10317 #define UCADDR (0x0002)
10318 #define UCADDRX0 (0x0001)
10319 #define UCADDRX0_L (0x0001)
10320 #define UCADDRX1 (0x0002)
10321 #define UCADDRX1_L (0x0002)
10322 #define UCADDRX2 (0x0004)
10323 #define UCADDRX2_L (0x0004)
10324 #define UCADDRX3 (0x0008)
10325 #define UCADDRX3_L (0x0008)
10326 #define UCADDRX4 (0x0010)
10327 #define UCADDRX4_L (0x0010)
10328 #define UCADDRX5 (0x0020)
10329 #define UCADDRX5_L (0x0020)
10330 #define UCADDRX6 (0x0040)
10331 #define UCADDRX6_L (0x0040)
10332 #define UCADDRX7 (0x0080)
10333 #define UCADDRX7_L (0x0080)
10334 #define UCADDRX8 (0x0100)
10335 #define UCADDRX8_H (0x0001)
10336 #define UCADDRX9 (0x0200)
10337 #define UCADDRX9_H (0x0002)
10338 #define UCASTP0 (0x0004)
10339 #define UCASTP0_L (0x0004)
10340 #define UCASTP1 (0x0008)
10341 #define UCASTP1_L (0x0008)
10342 #define UCASTP_3 (0x000C)
10343 #define UCB0ADDMASK_H (HWREG8_H(UCB0ADDMASK))
10344 #define UCB0ADDMASK_L (HWREG8_L(UCB0ADDMASK))
10345 #define UCB0ADDRX_H (HWREG8_H(UCB0ADDRX))
10346 #define UCB0ADDRX_L (HWREG8_L(UCB0ADDRX))
10347 #define UCB0BRW_H (HWREG8_H(UCB0BRW))
10348 #define UCB0BRW_L (HWREG8_L(UCB0BRW))
10351 #define UCB0I2COA0_H (HWREG8_H(UCB0I2COA0))
10352 #define UCB0I2COA0_L (HWREG8_L(UCB0I2COA0))
10353 #define UCB0I2COA1_H (HWREG8_H(UCB0I2COA1))
10354 #define UCB0I2COA1_L (HWREG8_L(UCB0I2COA1))
10355 #define UCB0I2COA2_H (HWREG8_H(UCB0I2COA2))
10356 #define UCB0I2COA2_L (HWREG8_L(UCB0I2COA2))
10357 #define UCB0I2COA3_H (HWREG8_H(UCB0I2COA3))
10358 #define UCB0I2COA3_L (HWREG8_L(UCB0I2COA3))
10359 #define UCB0I2CSA_H (HWREG8_H(UCB0I2CSA))
10360 #define UCB0I2CSA_L (HWREG8_L(UCB0I2CSA))
10361 #define UCB0IE_H (HWREG8_H(UCB0IE))
10362 #define UCB0IE_L (HWREG8_L(UCB0IE))
10363 #define UCB0IFG_H (HWREG8_H(UCB0IFG))
10364 #define UCB0IFG_L (HWREG8_L(UCB0IFG))
10365 #define UCB0RXBUF_H (HWREG8_H(UCB0RXBUF))
10366 #define UCB0RXBUF_L (HWREG8_L(UCB0RXBUF))
10367 #define UCB0STATW_H (HWREG8_H(UCB0STATW))
10368 #define UCB0STATW_L (HWREG8_L(UCB0STATW))
10369 #define UCB0TXBUF_H (HWREG8_H(UCB0TXBUF))
10370 #define UCB0TXBUF_L (HWREG8_L(UCB0TXBUF))
10371 #define UCB1ADDMASK_H (HWREG8_H(UCB1ADDMASK))
10372 #define UCB1ADDMASK_L (HWREG8_L(UCB1ADDMASK))
10373 #define UCB1ADDRX_H (HWREG8_H(UCB1ADDRX))
10374 #define UCB1ADDRX_L (HWREG8_L(UCB1ADDRX))
10375 #define UCB1BRW_H (HWREG8_H(UCB1BRW))
10376 #define UCB1BRW_L (HWREG8_L(UCB1BRW))
10379 #define UCB1I2COA0_H (HWREG8_H(UCB1I2COA0))
10380 #define UCB1I2COA0_L (HWREG8_L(UCB1I2COA0))
10381 #define UCB1I2COA1_H (HWREG8_H(UCB1I2COA1))
10382 #define UCB1I2COA1_L (HWREG8_L(UCB1I2COA1))
10383 #define UCB1I2COA2_H (HWREG8_H(UCB1I2COA2))
10384 #define UCB1I2COA2_L (HWREG8_L(UCB1I2COA2))
10385 #define UCB1I2COA3_H (HWREG8_H(UCB1I2COA3))
10386 #define UCB1I2COA3_L (HWREG8_L(UCB1I2COA3))
10387 #define UCB1I2CSA_H (HWREG8_H(UCB1I2CSA))
10388 #define UCB1I2CSA_L (HWREG8_L(UCB1I2CSA))
10389 #define UCB1IE_H (HWREG8_H(UCB1IE))
10390 #define UCB1IE_L (HWREG8_L(UCB1IE))
10391 #define UCB1IFG_H (HWREG8_H(UCB1IFG))
10392 #define UCB1IFG_L (HWREG8_L(UCB1IFG))
10393 #define UCB1RXBUF_H (HWREG8_H(UCB1RXBUF))
10394 #define UCB1RXBUF_L (HWREG8_L(UCB1RXBUF))
10395 #define UCB1STATW_H (HWREG8_H(UCB1STATW))
10396 #define UCB1STATW_L (HWREG8_L(UCB1STATW))
10397 #define UCB1TXBUF_H (HWREG8_H(UCB1TXBUF))
10398 #define UCB1TXBUF_L (HWREG8_L(UCB1TXBUF))
10399 #define UCB2ADDMASK_H (HWREG8_H(UCB2ADDMASK))
10400 #define UCB2ADDMASK_L (HWREG8_L(UCB2ADDMASK))
10401 #define UCB2ADDRX_H (HWREG8_H(UCB2ADDRX))
10402 #define UCB2ADDRX_L (HWREG8_L(UCB2ADDRX))
10403 #define UCB2BRW_H (HWREG8_H(UCB2BRW))
10404 #define UCB2BRW_L (HWREG8_L(UCB2BRW))
10407 #define UCB2I2COA0_H (HWREG8_H(UCB2I2COA0))
10408 #define UCB2I2COA0_L (HWREG8_L(UCB2I2COA0))
10409 #define UCB2I2COA1_H (HWREG8_H(UCB2I2COA1))
10410 #define UCB2I2COA1_L (HWREG8_L(UCB2I2COA1))
10411 #define UCB2I2COA2_H (HWREG8_H(UCB2I2COA2))
10412 #define UCB2I2COA2_L (HWREG8_L(UCB2I2COA2))
10413 #define UCB2I2COA3_H (HWREG8_H(UCB2I2COA3))
10414 #define UCB2I2COA3_L (HWREG8_L(UCB2I2COA3))
10415 #define UCB2I2CSA_H (HWREG8_H(UCB2I2CSA))
10416 #define UCB2I2CSA_L (HWREG8_L(UCB2I2CSA))
10417 #define UCB2IE_H (HWREG8_H(UCB2IE))
10418 #define UCB2IE_L (HWREG8_L(UCB2IE))
10419 #define UCB2IFG_H (HWREG8_H(UCB2IFG))
10420 #define UCB2IFG_L (HWREG8_L(UCB2IFG))
10421 #define UCB2RXBUF_H (HWREG8_H(UCB2RXBUF))
10422 #define UCB2RXBUF_L (HWREG8_L(UCB2RXBUF))
10423 #define UCB2STATW_H (HWREG8_H(UCB2STATW))
10424 #define UCB2STATW_L (HWREG8_L(UCB2STATW))
10425 #define UCB2TXBUF_H (HWREG8_H(UCB2TXBUF))
10426 #define UCB2TXBUF_L (HWREG8_L(UCB2TXBUF))
10427 #define UCB3ADDMASK_H (HWREG8_H(UCB3ADDMASK))
10428 #define UCB3ADDMASK_L (HWREG8_L(UCB3ADDMASK))
10429 #define UCB3ADDRX_H (HWREG8_H(UCB3ADDRX))
10430 #define UCB3ADDRX_L (HWREG8_L(UCB3ADDRX))
10431 #define UCB3BRW_H (HWREG8_H(UCB3BRW))
10432 #define UCB3BRW_L (HWREG8_L(UCB3BRW))
10435 #define UCB3I2COA0_H (HWREG8_H(UCB3I2COA0))
10436 #define UCB3I2COA0_L (HWREG8_L(UCB3I2COA0))
10437 #define UCB3I2COA1_H (HWREG8_H(UCB3I2COA1))
10438 #define UCB3I2COA1_L (HWREG8_L(UCB3I2COA1))
10439 #define UCB3I2COA2_H (HWREG8_H(UCB3I2COA2))
10440 #define UCB3I2COA2_L (HWREG8_L(UCB3I2COA2))
10441 #define UCB3I2COA3_H (HWREG8_H(UCB3I2COA3))
10442 #define UCB3I2COA3_L (HWREG8_L(UCB3I2COA3))
10443 #define UCB3I2CSA_H (HWREG8_H(UCB3I2CSA))
10444 #define UCB3I2CSA_L (HWREG8_L(UCB3I2CSA))
10445 #define UCB3IE_H (HWREG8_H(UCB3IE))
10446 #define UCB3IE_L (HWREG8_L(UCB3IE))
10447 #define UCB3IFG_H (HWREG8_H(UCB3IFG))
10448 #define UCB3IFG_L (HWREG8_L(UCB3IFG))
10449 #define UCB3RXBUF_H (HWREG8_H(UCB3RXBUF))
10450 #define UCB3RXBUF_L (HWREG8_L(UCB3RXBUF))
10451 #define UCB3STATW_H (HWREG8_H(UCB3STATW))
10452 #define UCB3STATW_L (HWREG8_L(UCB3STATW))
10453 #define UCB3TXBUF_H (HWREG8_H(UCB3TXBUF))
10454 #define UCB3TXBUF_L (HWREG8_L(UCB3TXBUF))
10455 #define UCBCNT0 (0x0100)
10456 #define UCBCNT1 (0x0200)
10457 #define UCBCNT2 (0x0400)
10458 #define UCBCNT3 (0x0800)
10459 #define UCBCNT4 (0x1000)
10460 #define UCBCNT5 (0x2000)
10461 #define UCBCNT6 (0x4000)
10462 #define UCBCNT7 (0x8000)
10463 #define UCBRF0 (0x0010)
10464 #define UCBRF0_L (0x0010)
10465 #define UCBRF1 (0x0020)
10466 #define UCBRF1_L (0x0020)
10467 #define UCBRF2 (0x0040)
10468 #define UCBRF2_L (0x0040)
10469 #define UCBRF3 (0x0080)
10470 #define UCBRF3_L (0x0080)
10471 #define UCBRF_0 (0x00)
10472 #define UCBRF_1 (0x10)
10473 #define UCBRF_10 (0xA0)
10474 #define UCBRF_11 (0xB0)
10475 #define UCBRF_12 (0xC0)
10476 #define UCBRF_13 (0xD0)
10477 #define UCBRF_14 (0xE0)
10478 #define UCBRF_15 (0xF0)
10479 #define UCBRF_2 (0x20)
10480 #define UCBRF_3 (0x30)
10481 #define UCBRF_4 (0x40)
10482 #define UCBRF_5 (0x50)
10483 #define UCBRF_6 (0x60)
10484 #define UCBRF_7 (0x70)
10485 #define UCBRF_8 (0x80)
10486 #define UCBRF_9 (0x90)
10487 #define UCBRKIE_L (0x0010)
10488 #define UCBRS0 (0x0100)
10489 #define UCBRS0_H (0x0001)
10490 #define UCBRS1 (0x0200)
10491 #define UCBRS1_H (0x0002)
10492 #define UCBRS2 (0x0400)
10493 #define UCBRS2_H (0x0004)
10494 #define UCBRS3 (0x0800)
10495 #define UCBRS3_H (0x0008)
10496 #define UCBRS4 (0x1000)
10497 #define UCBRS4_H (0x0010)
10498 #define UCBRS5 (0x2000)
10499 #define UCBRS5_H (0x0020)
10500 #define UCBRS6 (0x4000)
10501 #define UCBRS6_H (0x0040)
10502 #define UCBRS7 (0x8000)
10503 #define UCBRS7_H (0x0080)
10504 #define UCCLTO0 (0x0040)
10505 #define UCCLTO0_L (0x0040)
10506 #define UCCLTO1 (0x0080)
10507 #define UCCLTO1_L (0x0080)
10508 #define UCDELIM0 (0x10)
10509 #define UCDELIM1 (0x20)
10510 #define UCDORM_L (0x0008)
10511 #define UCETXINT_H (0x0001)
10512 #define UCGCEN_H (0x0080)
10513 #define UCGLIT0 (0x0001)
10514 #define UCGLIT0_L (0x0001)
10515 #define UCGLIT1 (0x0002)
10516 #define UCGLIT1_L (0x0002)
10517 #define UCIDLE (0x0002)
10518 #define UCIREN_L (0x0001)
10519 #define UCIRRXFE_H (0x0001)
10520 #define UCIRRXFL0 (0x0400)
10521 #define UCIRRXFL0_H (0x0004)
10522 #define UCIRRXFL1 (0x0800)
10523 #define UCIRRXFL1_H (0x0008)
10524 #define UCIRRXFL2 (0x1000)
10525 #define UCIRRXFL2_H (0x0010)
10526 #define UCIRRXFL3 (0x2000)
10527 #define UCIRRXFL3_H (0x0020)
10528 #define UCIRRXFL4 (0x4000)
10529 #define UCIRRXFL4_H (0x0040)
10530 #define UCIRRXFL5 (0x8000)
10531 #define UCIRRXFL5_H (0x0080)
10532 #define UCIRRXPL_H (0x0002)
10533 #define UCIRTXCLK_L (0x0002)
10534 #define UCIRTXPL0 (0x0004)
10535 #define UCIRTXPL0_L (0x0004)
10536 #define UCIRTXPL1 (0x0008)
10537 #define UCIRTXPL1_L (0x0008)
10538 #define UCIRTXPL2 (0x0010)
10539 #define UCIRTXPL2_L (0x0010)
10540 #define UCIRTXPL3 (0x0020)
10541 #define UCIRTXPL3_L (0x0020)
10542 #define UCIRTXPL4 (0x0040)
10543 #define UCIRTXPL4_L (0x0040)
10544 #define UCIRTXPL5 (0x0080)
10545 #define UCIRTXPL5_L (0x0080)
10546 #define UCMM_H (0x0020)
10547 #define UCMODE0 (0x0200)
10548 #define UCMODE0_H (0x0002)
10549 #define UCMODE1 (0x0400)
10550 #define UCMODE1_H (0x0004)
10551 #define UCMSB_H (0x0020)
10552 #define UCOA0 (0x0001)
10553 #define UCOA0_L (0x0001)
10554 #define UCOA1 (0x0002)
10555 #define UCOA1_L (0x0002)
10556 #define UCOA2 (0x0004)
10557 #define UCOA2_L (0x0004)
10558 #define UCOA3 (0x0008)
10559 #define UCOA3_L (0x0008)
10560 #define UCOA4 (0x0010)
10561 #define UCOA4_L (0x0010)
10562 #define UCOA5 (0x0020)
10563 #define UCOA5_L (0x0020)
10564 #define UCOA6 (0x0040)
10565 #define UCOA6_L (0x0040)
10566 #define UCOA7 (0x0080)
10567 #define UCOA7_L (0x0080)
10568 #define UCOA8 (0x0100)
10569 #define UCOA8_H (0x0001)
10570 #define UCOA9 (0x0200)
10571 #define UCOA9_H (0x0002)
10572 #define UCOAEN_H (0x0004)
10573 #define UCOS16_L (0x0001)
10574 #define UCPAR_H (0x0040)
10575 #define UCPEN_H (0x0080)
10576 #define UCRXEIE_L (0x0020)
10577 #define UCSA0 (0x0001)
10578 #define UCSA0_L (0x0001)
10579 #define UCSA1 (0x0002)
10580 #define UCSA1_L (0x0002)
10581 #define UCSA2 (0x0004)
10582 #define UCSA2_L (0x0004)
10583 #define UCSA3 (0x0008)
10584 #define UCSA3_L (0x0008)
10585 #define UCSA4 (0x0010)
10586 #define UCSA4_L (0x0010)
10587 #define UCSA5 (0x0020)
10588 #define UCSA5_L (0x0020)
10589 #define UCSA6 (0x0040)
10590 #define UCSA6_L (0x0040)
10591 #define UCSA7 (0x0080)
10592 #define UCSA7_L (0x0080)
10593 #define UCSA8 (0x0100)
10594 #define UCSA8_H (0x0001)
10595 #define UCSA9 (0x0200)
10596 #define UCSA9_H (0x0002)
10597 #define UCSLA10_H (0x0040)
10598 #define UCSPB_H (0x0008)
10599 #define UCSSEL0 (0x0040)
10600 #define UCSSEL0_L (0x0040)
10601 #define UCSSEL1 (0x0080)
10602 #define UCSSEL1_L (0x0080)
10603 #define UCSTPNACK_L (0x0020)
10604 #define UCSWACK_L (0x0010)
10605 #define UCSWRST_L (0x0001)
10606 #define UCSYNC_H (0x0001)
10607 #define UCTBCNT0 (0x0001)
10608 #define UCTBCNT1 (0x0002)
10609 #define UCTBCNT2 (0x0004)
10610 #define UCTBCNT3 (0x0008)
10611 #define UCTBCNT4 (0x0010)
10612 #define UCTBCNT5 (0x0020)
10613 #define UCTBCNT6 (0x0040)
10614 #define UCTBCNT7 (0x0080)
10615 #define UCTR_L (0x0010)
10616 #define UCTXACK_L (0x0020)
10617 #define UCTXADDR_L (0x0004)
10618 #define UCTXBRK_L (0x0002)
10619 #define UCTXNACK_L (0x0008)
10620 #define UCTXSTP_L (0x0004)
10621 #define UCTXSTT_L (0x0002)
10622 #define UDMA_ALTBASE (HWREG32(0x4000F00C))
10623 #define UDMA_ALTCLR (HWREG32(0x4000F034))
10624 #define UDMA_ALTSET (HWREG32(0x4000F030))
10625 #define UDMA_CFG (HWREG32(0x4000F004))
10626 #define UDMA_CTLBASE (HWREG32(0x4000F008))
10627 #define UDMA_ENACLR (HWREG32(0x4000F02C))
10628 #define UDMA_ENASET (HWREG32(0x4000F028))
10629 #define UDMA_ERRCLR (HWREG32(0x4000F04C))
10630 #define UDMA_PCELL_ID_0 (HWREG32(0x4000FFF0))
10631 #define UDMA_PCELL_ID_1 (HWREG32(0x4000FFF4))
10632 #define UDMA_PCELL_ID_2 (HWREG32(0x4000FFF8))
10633 #define UDMA_PCELL_ID_3 (HWREG32(0x4000FFFC))
10634 #define UDMA_PERIPH_ID_0 (HWREG32(0x4000FFE0))
10635 #define UDMA_PERIPH_ID_1 (HWREG32(0x4000FFE4))
10636 #define UDMA_PERIPH_ID_2 (HWREG32(0x4000FFE8))
10637 #define UDMA_PERIPH_ID_3 (HWREG32(0x4000FFEC))
10638 #define UDMA_PERIPH_ID_4 (HWREG32(0x4000FFD0))
10639 #define UDMA_PRIOCLR (HWREG32(0x4000F03C))
10640 #define UDMA_PRIOSET (HWREG32(0x4000F038))
10641 #define UDMA_REQMASKCLR (HWREG32(0x4000F024))
10642 #define UDMA_REQMASKSET (HWREG32(0x4000F020))
10643 #define UDMA_STAT (HWREG32(0x4000F000))
10644 #define UDMA_SWREQ (HWREG32(0x4000F014))
10645 #define UDMA_USEBURSTCLR (HWREG32(0x4000F01C))
10646 #define UDMA_USEBURSTSET (HWREG32(0x4000F018))
10647 #define UDMA_WAITSTAT (HWREG32(0x4000F010))
10648 #define USCI_I2C_UCALIFG (0x0002)
10649 #define USCI_I2C_UCBCNTIFG (0x001A)
10650 #define USCI_I2C_UCBIT9IFG (0x001E)
10651 #define USCI_I2C_UCCLTOIFG (0x001C)
10652 #define USCI_I2C_UCNACKIFG (0x0004)
10653 #define USCI_I2C_UCRXIFG0 (0x0016)
10654 #define USCI_I2C_UCRXIFG1 (0x0012)
10655 #define USCI_I2C_UCRXIFG2 (0x000E)
10656 #define USCI_I2C_UCRXIFG3 (0x000A)
10657 #define USCI_I2C_UCSTPIFG (0x0008)
10658 #define USCI_I2C_UCSTTIFG (0x0006)
10659 #define USCI_I2C_UCTXIFG0 (0x0018)
10660 #define USCI_I2C_UCTXIFG1 (0x0014)
10661 #define USCI_I2C_UCTXIFG2 (0x0010)
10662 #define USCI_I2C_UCTXIFG3 (0x000C)
10663 #define USCI_NONE (0x0000)
10664 #define USCI_SPI_UCRXIFG (0x0002)
10665 #define USCI_SPI_UCTXIFG (0x0004)
10666 #define USCI_UART_UCRXIFG (0x0002)
10667 #define USCI_UART_UCSTTIFG (0x0006)
10668 #define USCI_UART_UCTXCPTIFG (0x0008)
10669 #define USCI_UART_UCTXIFG (0x0004)
10670 #define WDTCNTCL_L (0x0008)
10671 #define WDTCTL_H (HWREG8_H(WDTCTL))
10672 #define WDTCTL_L (HWREG8_L(WDTCTL))
10673 #define WDTHOLD_L (0x0080)
10674 #define WDTIS0 (0x0001)
10675 #define WDTIS0_L (0x0001)
10676 #define WDTIS1 (0x0002)
10677 #define WDTIS1_L (0x0002)
10678 #define WDTIS2 (0x0004)
10679 #define WDTIS2_L (0x0004)
10680 #define WDTIS__128M (1*0x0001u)
10681 #define WDTIS__2G (0*0x0001u)
10682 #define WDTIS__32K (4*0x0001u)
10683 #define WDTIS__512 (6*0x0001u)
10684 #define WDTIS__512K (3*0x0001u)
10685 #define WDTIS__64 (7*0x0001u)
10686 #define WDTIS__8192 (5*0x0001u)
10687 #define WDTIS__8192K (2*0x0001u)
10688 #define WDTPW_VAL (0x5A00)
10689 #define WDTSSEL0 (0x0020)
10690 #define WDTSSEL0_L (0x0020)
10691 #define WDTSSEL1 (0x0040)
10692 #define WDTSSEL1_L (0x0040)
10693 #define WDTSSEL__VLO (2*0x0020u)
10694 #define WDTTMSEL_L (0x0010)
10695 #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0)
10696 #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1)
10697 #define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0)
10698 #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0)
10699 #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2)
10700 #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1)
10701 #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0)
10702 #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0)
10703 #define WDT_A_CTL (HWREG16(0x4000480C))
10704 #define WDT_A_CTL_CNTCL (0x0008)
10705 #define WDT_A_CTL_CNTCL__0 (0x0000)
10706 #define WDT_A_CTL_CNTCL__0_NO_ACTION (0x0000)
10707 #define WDT_A_CTL_CNTCL__1 (0x0008)
10708 #define WDT_A_CTL_CNTCL__1_CLEAR (0x0008)
10709 #define WDT_A_CTL_HOLD (0x0080)
10710 #define WDT_A_CTL_HOLD__0 (0x0000)
10711 #define WDT_A_CTL_HOLD__1 (0x0080)
10712 #define WDT_A_CTL_IS__0 (0x0000)
10713 #define WDT_A_CTL_IS__1 (0x0001)
10714 #define WDT_A_CTL_IS__2 (0x0002)
10715 #define WDT_A_CTL_IS__3 (0x0003)
10716 #define WDT_A_CTL_IS__4 (0x0004)
10717 #define WDT_A_CTL_IS__5 (0x0005)
10718 #define WDT_A_CTL_IS__6 (0x0006)
10719 #define WDT_A_CTL_IS__7 (0x0007)
10720 #define WDT_A_CTL_IS__M (0x0007)
10721 #define WDT_A_CTL_PW__M (0xff00)
10722 #define WDT_A_CTL_SSEL__0 (0x0000)
10723 #define WDT_A_CTL_SSEL__0_SMCLK (0x0000)
10724 #define WDT_A_CTL_SSEL__1 (0x0020)
10725 #define WDT_A_CTL_SSEL__1_ACLK (0x0020)
10726 #define WDT_A_CTL_SSEL__2 (0x0040)
10727 #define WDT_A_CTL_SSEL__2_VLOCLK (0x0040)
10728 #define WDT_A_CTL_SSEL__3 (0x0060)
10729 #define WDT_A_CTL_SSEL__3_BCLK (0x0060)
10730 #define WDT_A_CTL_SSEL__M (0x0060)
10731 #define WDT_A_CTL_TMSEL (0x0010)
10732 #define WDT_A_CTL_TMSEL__0 (0x0000)
10733 #define WDT_A_CTL_TMSEL__0_WATCHDOG_MODE (0x0000)
10734 #define WDT_A_CTL_TMSEL__1 (0x0010)
10735 #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)
10736 #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1)
10737 #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2)
10738 #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0)
10739 #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)
10740 #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1)
10741 #define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2)
10742 #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0)
10743 #define WDT_PW_VAL (0x5A00)
10744 #define __ADC14_BASE__ (0x40012000)
10745 #define __AES256_BASE__ (0x40003C00)
10746 #define __CAPTIO0_BASE__ (0x40005400)
10747 #define __CAPTIO1_BASE__ (0x40005800)
10748 #define __COMP_E0_BASE__ (0x40003400)
10749 #define __COMP_E1_BASE__ (0x40003800)
10750 #define __CRC32_BASE__ (0x40004000)
10751 #define __CRC_BASE__ (__CRC32_BASE__)
10752 #define __CS_BASE__ (0x40010400)
10753 #define __DDDS_BASE__ (0x00203000)
10754 #define __DMA_BASE__ (0x4000E000)
10755 #define __DWT_BASE__ (0xE0001000)
10756 #define __EUSCI_A0_BASE__ (__EUSCI_A0_SPI_BASE__)
10757 #define __EUSCI_A0_SPI_BASE__ (0x40001000)
10758 #define __EUSCI_A0_UART_BASE__ (0x40001000)
10759 #define __EUSCI_A1_BASE__ (__EUSCI_A1_SPI_BASE__)
10760 #define __EUSCI_A1_SPI_BASE__ (0x40001400)
10761 #define __EUSCI_A1_UART_BASE__ (0x40001400)
10762 #define __EUSCI_A2_BASE__ (__EUSCI_A2_SPI_BASE__)
10763 #define __EUSCI_A2_SPI_BASE__ (0x40001800)
10764 #define __EUSCI_A2_UART_BASE__ (0x40001800)
10765 #define __EUSCI_A3_BASE__ (__EUSCI_A3_SPI_BASE__)
10766 #define __EUSCI_A3_SPI_BASE__ (0x40001C00)
10767 #define __EUSCI_A3_UART_BASE__ (0x40001C00)
10768 #define __EUSCI_B0_BASE__ (__EUSCI_B0_SPI_BASE__)
10769 #define __EUSCI_B0_I2C_BASE__ (0x40002000)
10770 #define __EUSCI_B0_SPI_BASE__ (0x40002000)
10771 #define __EUSCI_B1_BASE__ (__EUSCI_B1_SPI_BASE__)
10772 #define __EUSCI_B1_I2C_BASE__ (0x40002400)
10773 #define __EUSCI_B1_SPI_BASE__ (0x40002400)
10774 #define __EUSCI_B2_BASE__ (__EUSCI_B2_SPI_BASE__)
10775 #define __EUSCI_B2_I2C_BASE__ (0x40002800)
10776 #define __EUSCI_B2_SPI_BASE__ (0x40002800)
10777 #define __EUSCI_B3_BASE__ (__EUSCI_B3_SPI_BASE__)
10778 #define __EUSCI_B3_I2C_BASE__ (0x40002C00)
10779 #define __EUSCI_B3_SPI_BASE__ (0x40002C00)
10780 #define __FLASH_END__ (0x0003FFFF)
10781 #define __FLASH_START__ (0x00000000)
10782 #define __FLCTL_BASE__ (0x40011000)
10783 #define __FPB_BASE__ (0xE0002000)
10784 #define __FPU_BASE__ (0xE000E000)
10785 #define __INFO_FLASH_END__ (0x00203FFF)
10786 #define __INFO_FLASH_START__ (0x00200000)
10787 #define __ITM_BASE__ (0xE0000000)
10788 #define __MPU_BASE__ (0xE000E000)
10789 #define __MSP430_BASEADDRESS_CRC__ (__CRC32_BASE__)
10790 #define __MSP430_BASEADDRESS_PORT10_R__ (__P10_BASE__)
10791 #define __MSP430_BASEADDRESS_PORT1_R__ (__P1_BASE__)
10792 #define __MSP430_BASEADDRESS_PORT2_R__ (__P2_BASE__)
10793 #define __MSP430_BASEADDRESS_PORT3_R__ (__P3_BASE__)
10794 #define __MSP430_BASEADDRESS_PORT4_R__ (__P4_BASE__)
10795 #define __MSP430_BASEADDRESS_PORT5_R__ (__P5_BASE__)
10796 #define __MSP430_BASEADDRESS_PORT6_R__ (__P6_BASE__)
10797 #define __MSP430_BASEADDRESS_PORT7_R__ (__P7_BASE__)
10798 #define __MSP430_BASEADDRESS_PORT8_R__ (__P8_BASE__)
10799 #define __MSP430_BASEADDRESS_PORT9_R__ (__P9_BASE__)
10800 #define __MSP430_BASEADDRESS_PORTA_R__ (__PA_BASE__)
10801 #define __MSP430_BASEADDRESS_PORTB_R__ (__PB_BASE__)
10802 #define __MSP430_BASEADDRESS_PORTC_R__ (__PC_BASE__)
10803 #define __MSP430_BASEADDRESS_PORTD_R__ (__PD_BASE__)
10804 #define __MSP430_BASEADDRESS_PORTE_R__ (__PE_BASE__)
10805 #define __MSP430_BASEADDRESS_PORTJ_R__ (__PJ_BASE__)
10806 #define __MSP430_BASEADDRESS_REF__ (__REF_A_BASE__)
10807 #define __MSP430_BASEADDRESS_RTC_CE__ (__RTC_C_BASE__)
10808 #define __MSP430_BASEADDRESS_WDT_A__ (__WDT_A_BASE__)
10809 #define __P10_BASE__ (0x40004C81)
10810 #define __P1_BASE__ (0x40004C00)
10811 #define __P2_BASE__ (0x40004C01)
10812 #define __P3_BASE__ (0x40004C20)
10813 #define __P4_BASE__ (0x40004C21)
10814 #define __P5_BASE__ (0x40004C40)
10815 #define __P6_BASE__ (0x40004C41)
10816 #define __P7_BASE__ (0x40004C60)
10817 #define __P8_BASE__ (0x40004C61)
10818 #define __P9_BASE__ (0x40004C80)
10819 #define __PA_BASE__ (0x40004C00)
10820 #define __PB_BASE__ (0x40004C20)
10821 #define __PCM_BASE__ (0x40010000)
10822 #define __PC_BASE__ (0x40004C40)
10823 #define __PD_BASE__ (0x40004C60)
10824 #define __PE_BASE__ (0x40004C80)
10825 #define __PJ_BASE__ (0x40004D20)
10826 #define __PMAP_BASE__ (0x40005000)
10827 #define __PSS_BASE__ (0x40010800)
10828 #define __REF_A_BASE__ (0x40003000)
10829 #define __RSTCTL_BASE__ (0xE0042000)
10830 #define __RTC_C_BASE__ (0x40004400)
10831 #define __SCS_BASE__ (0xE000E000)
10832 #define __SYSCTL_BASE__ (0xE0043000)
10833 #define __T32_BASE__ (0x4000C000)
10834 #define __TA0_BASE__ (0x40000000)
10835 #define __TA1_BASE__ (0x40000400)
10836 #define __TA2_BASE__ (0x40000800)
10837 #define __TA3_BASE__ (0x40000C00)
10838 #define __UDMA_BASE__ (0x4000F000)
10839 #define __WDT_A_BASE__ (0x40004800)
Copyright 2014, Texas Instruments Incorporated