124 #define DMA_TaskStructEntry(transferCount, \
133 (((srcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(srcAddr) : \
134 ((void *)(&((uint8_t *)(srcAddr))[((transferCount) << \
135 ((srcIncrement) >> 26)) - 1]))), \
136 (((dstIncrement) == UDMA_DST_INC_NONE) ? (void *)(dstAddr) : \
137 ((void *)(&((uint8_t *)(dstAddr))[((transferCount) << \
138 ((dstIncrement) >> 30)) - 1]))), \
139 (srcIncrement) | (dstIncrement) | (itemSize) | (arbSize) | \
140 (((transferCount) - 1) << 4) | \
141 ((((mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
142 ((mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
143 (mode) | UDMA_MODE_ALT_SELECT : (mode)), 0 \
159 #define UDMA_ATTR_USEBURST 0x00000001
160 #define UDMA_ATTR_ALTSELECT 0x00000002
161 #define UDMA_ATTR_HIGH_PRIORITY 0x00000004
162 #define UDMA_ATTR_REQMASK 0x00000008
163 #define UDMA_ATTR_ALL 0x0000000F
171 #define UDMA_MODE_STOP 0x00000000
172 #define UDMA_MODE_BASIC 0x00000001
173 #define UDMA_MODE_AUTO 0x00000002
174 #define UDMA_MODE_PINGPONG 0x00000003
175 #define UDMA_MODE_MEM_SCATTER_GATHER \
177 #define UDMA_MODE_PER_SCATTER_GATHER \
179 #define UDMA_MODE_ALT_SELECT 0x00000001
186 #define UDMA_DST_INC_8 0x00000000
187 #define UDMA_DST_INC_16 0x40000000
188 #define UDMA_DST_INC_32 0x80000000
189 #define UDMA_DST_INC_NONE 0xc0000000
190 #define UDMA_SRC_INC_8 0x00000000
191 #define UDMA_SRC_INC_16 0x04000000
192 #define UDMA_SRC_INC_32 0x08000000
193 #define UDMA_SRC_INC_NONE 0x0c000000
194 #define UDMA_SIZE_8 0x00000000
195 #define UDMA_SIZE_16 0x11000000
196 #define UDMA_SIZE_32 0x22000000
197 #define UDMA_DST_PROT_PRIV 0x00200000
198 #define UDMA_SRC_PROT_PRIV 0x00040000
199 #define UDMA_ARB_1 0x00000000
200 #define UDMA_ARB_2 0x00004000
201 #define UDMA_ARB_4 0x00008000
202 #define UDMA_ARB_8 0x0000c000
203 #define UDMA_ARB_16 0x00010000
204 #define UDMA_ARB_32 0x00014000
205 #define UDMA_ARB_64 0x00018000
206 #define UDMA_ARB_128 0x0001c000
207 #define UDMA_ARB_256 0x00020000
208 #define UDMA_ARB_512 0x00024000
209 #define UDMA_ARB_1024 0x00028000
210 #define UDMA_NEXT_USEBURST 0x00000008
218 #define UDMA_PRI_SELECT 0x00000000
219 #define UDMA_ALT_SELECT 0x00000008
231 #define DMA_CH0_RESERVED0 0x00000000
232 #define DMA_CH0_EUSCIA0TX 0x01000000
233 #define DMA_CH0_EUSCIB0TX0 0x02000000
234 #define DMA_CH0_EUSCIB3TX1 0x03000000
235 #define DMA_CH0_EUSCIB2TX2 0x04000000
236 #define DMA_CH0_EUSCIB1TX3 0x05000000
237 #define DMA_CH0_TIMERA0CCR0 0x06000000
238 #define DMA_CH0_AESTRIGGER0 0x07000000
243 #define DMA_CH1_RESERVED0 0x00000001
244 #define DMA_CH1_EUSCIA0RX 0x01000001
245 #define DMA_CH1_EUSCIB0RX0 0x02000001
246 #define DMA_CH1_EUSCIB3RX1 0x03000001
247 #define DMA_CH1_EUSCIB2RX2 0x04000001
248 #define DMA_CH1_EUSCIB1RX3 0x05000001
249 #define DMA_CH1_TIMERA0CCR2 0x06000001
250 #define DMA_CH1_AESTRIGGER1 0x07000001
255 #define DMA_CH2_RESERVED0 0x00000002
256 #define DMA_CH2_EUSCIA1TX 0x01000002
257 #define DMA_CH2_EUSCIB1TX0 0x02000002
258 #define DMA_CH2_EUSCIB0TX1 0x03000002
259 #define DMA_CH2_EUSCIB3TX2 0x04000002
260 #define DMA_CH2_EUSCIB2TX3 0x05000002
261 #define DMA_CH2_TIMERA1CCR0 0x06000002
262 #define DMA_CH2_AESTRIGGER2 0x07000002
267 #define DMA_CH3_RESERVED0 0x00000003
268 #define DMA_CH3_EUSCIA1RX 0x01000003
269 #define DMA_CH3_EUSCIB1RX0 0x02000003
270 #define DMA_CH3_EUSCIB0RX1 0x03000003
271 #define DMA_CH3_EUSCIB3RX2 0x04000003
272 #define DMA_CH3_EUSCIB2RX3 0x05000003
273 #define DMA_CH3_TIMERA1CCR2 0x06000003
274 #define DMA_CH3_RESERVED1 0x07000003
279 #define DMA_CH4_RESERVED0 0x00000004
280 #define DMA_CH4_EUSCIA2TX 0x01000004
281 #define DMA_CH4_EUSCIB2TX0 0x02000004
282 #define DMA_CH4_EUSCIB1TX1 0x03000004
283 #define DMA_CH4_EUSCIB0TX2 0x04000004
284 #define DMA_CH4_EUSCIB3TX3 0x05000004
285 #define DMA_CH4_TIMERA2CCR0 0x06000004
286 #define DMA_CH4_RESERVED1 0x07000004
291 #define DMA_CH5_RESERVED0 0x00000005
292 #define DMA_CH5_EUSCIA2RX 0x01000005
293 #define DMA_CH5_EUSCIB2RX0 0x02000005
294 #define DMA_CH5_EUSCIB1RX1 0x03000005
295 #define DMA_CH5_EUSCIB0RX2 0x04000005
296 #define DMA_CH5_EUSCIB3RX3 0x05000005
297 #define DMA_CH5_TIMERA2CCR2 0x06000005
298 #define DMA_CH5_RESERVED1 0x07000005
303 #define DMA_CH6_RESERVED0 0x00000006
304 #define DMA_CH6_EUSCIA3TX 0x01000006
305 #define DMA_CH6_EUSCIB3TX0 0x02000006
306 #define DMA_CH6_EUSCIB2TX1 0x03000006
307 #define DMA_CH6_EUSCIB1TX2 0x04000006
308 #define DMA_CH6_EUSCIB0TX3 0x05000006
309 #define DMA_CH6_TIMERA3CCR0 0x06000006
310 #define DMA_CH6_EXTERNALPIN 0x07000006
315 #define DMA_CH7_RESERVED0 0x00000007
316 #define DMA_CH7_EUSCIA3RX 0x01000007
317 #define DMA_CH7_EUSCIB3RX0 0x02000007
318 #define DMA_CH7_EUSCIB2RX1 0x03000007
319 #define DMA_CH7_EUSCIB1RX2 0x04000007
320 #define DMA_CH7_EUSCIB0RX3 0x05000007
321 #define DMA_CH7_TIMERA3CCR2 0x06000007
322 #define DMA_CH7_ADC12C 0x07000007
328 #define DMA_INT0 INT_DMA_INT0
329 #define DMA_INT1 INT_DMA_INT1
330 #define DMA_INT2 INT_DMA_INT2
331 #define DMA_INT3 INT_DMA_INT3
332 #define DMA_INTERR INT_DMA_ERR
334 #define DMA_CHANNEL_0 0
335 #define DMA_CHANNEL_1 1
336 #define DMA_CHANNEL_2 2
337 #define DMA_CHANNEL_3 3
338 #define DMA_CHANNEL_4 4
339 #define DMA_CHANNEL_5 5
340 #define DMA_CHANNEL_6 6
341 #define DMA_CHANNEL_7 7
704 void *srcAddr,
void *dstAddr, uint32_t transferSize);
731 void *taskList, uint32_t isPeriphSG);
940 void (*intHandler)(
void));
uint32_t DMA_getChannelSize(uint32_t channelStructIndex)
Definition: dma.c:508
uint32_t DMA_getChannelMode(uint32_t channelStructIndex)
Definition: dma.c:560
void DMA_disableChannel(uint32_t channelNum)
Definition: dma.c:53
struct _DMA_ControlTable DMA_ControlTable
void DMA_requestChannel(uint32_t channelNum)
Definition: dma.c:112
void DMA_requestSoftwareTransfer(uint32_t channel)
Definition: dma.c:719
volatile uint32_t spare
Definition: dma.h:52
uint32_t DMA_getChannelAttribute(uint32_t channelNum)
Definition: dma.c:231
void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount, void *taskList, uint32_t isPeriphSG)
Definition: dma.c:439
void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
Definition: dma.c:125
void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel)
Definition: dma.c:695
void DMA_assignChannel(uint32_t mapping)
Definition: dma.c:605
void DMA_unregisterInterrupt(uint32_t intChannel)
Definition: dma.c:797
volatile uint32_t control
Definition: dma.h:47
volatile void * dstEndAddr
Definition: dma.h:42
volatile void * srcEndAddr
Definition: dma.h:37
void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
Definition: dma.c:178
void DMA_registerInterrupt(uint32_t intChannel, void(*intHandler)(void))
Definition: dma.c:773
void DMA_enableInterrupt(uint32_t interruptNumber)
Definition: dma.c:734
void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode, void *srcAddr, void *dstAddr, uint32_t transferSize)
Definition: dma.c:317
void DMA_enableChannel(uint32_t channelNum)
Definition: dma.c:40
bool DMA_isChannelEnabled(uint32_t channelNum)
Definition: dma.c:66
void DMA_setChannelControl(uint32_t channelStructIndex, uint32_t control)
Definition: dma.c:285
void DMA_setControlBase(void *controlTable)
Definition: dma.c:80
void DMA_disableModule(void)
Definition: dma.c:16
void * DMA_getControlBase(void)
Definition: dma.c:94
void DMA_enableModule(void)
Definition: dma.c:8
void DMA_disableInterrupt(uint32_t interruptNumber)
Definition: dma.c:754
uint32_t DMA_getErrorStatus(void)
Definition: dma.c:24
uint32_t DMA_getInterruptStatus(void)
Definition: dma.c:724
void * DMA_getControlAlternateBase(void)
Definition: dma.c:103
void DMA_clearErrorStatus(void)
Definition: dma.c:32
void DMA_clearInterruptFlag(uint32_t intChannel)
Definition: dma.c:729