CC3200 Peripheral Driver Library User's Guide  1.2.0
udma.h
1 //*****************************************************************************
2 //
3 // udma.h
4 //
5 // Prototypes and macros for the uDMA controller.
6 //
7 // Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
8 //
9 //
10 // Redistribution and use in source and binary forms, with or without
11 // modification, are permitted provided that the following conditions
12 // are met:
13 //
14 // Redistributions of source code must retain the above copyright
15 // notice, this list of conditions and the following disclaimer.
16 //
17 // Redistributions in binary form must reproduce the above copyright
18 // notice, this list of conditions and the following disclaimer in the
19 // documentation and/or other materials provided with the
20 // distribution.
21 //
22 // Neither the name of Texas Instruments Incorporated nor the names of
23 // its contributors may be used to endorse or promote products derived
24 // from this software without specific prior written permission.
25 //
26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 //
38 //*****************************************************************************
39 
40 #ifndef __UDMA_H__
41 #define __UDMA_H__
42 
43 //*****************************************************************************
44 //
45 // If building with a C++ compiler, make all of the definitions in this header
46 // have a C binding.
47 //
48 //*****************************************************************************
49 #ifdef __cplusplus
50 extern "C"
51 {
52 #endif
53 
54 //*****************************************************************************
55 //
58 //
59 //*****************************************************************************
60 
61 //*****************************************************************************
62 //
63 // A structure that defines an entry in the channel control table. These
64 // fields are used by the uDMA controller and normally it is not necessary for
65 // software to directly read or write fields in the table.
66 //
67 //*****************************************************************************
68 typedef struct
69 {
70  //
71  // The ending source address of the data transfer.
72  //
73  volatile void *pvSrcEndAddr;
74 
75  //
76  // The ending destination address of the data transfer.
77  //
78  volatile void *pvDstEndAddr;
79 
80  //
81  // The channel control mode.
82  //
83  volatile unsigned long ulControl;
84 
85  //
86  // An unused location.
87  //
88  volatile unsigned long ulSpare;
89 }
91 
92 //*****************************************************************************
93 //
159 //
160 //*****************************************************************************
161 #define uDMATaskStructEntry(ulTransferCount, \
162  ulItemSize, \
163  ulSrcIncrement, \
164  pvSrcAddr, \
165  ulDstIncrement, \
166  pvDstAddr, \
167  ulArbSize, \
168  ulMode) \
169  { \
170  (((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \
171  ((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \
172  ((ulSrcIncrement) >> 26)) - 1]))), \
173  (((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \
174  ((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \
175  ((ulDstIncrement) >> 30)) - 1]))), \
176  (ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \
177  (((ulTransferCount) - 1) << 4) | \
178  ((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
179  ((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
180  (ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \
181  }
182 
183 //*****************************************************************************
184 //
185 // Close the Doxygen group.
187 //
188 //*****************************************************************************
189 
190 //*****************************************************************************
191 //
192 // Flags that can be passed to uDMAChannelAttributeEnable(),
193 // uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
194 //
195 //*****************************************************************************
196 #define UDMA_ATTR_USEBURST 0x00000001
197 #define UDMA_ATTR_ALTSELECT 0x00000002
198 #define UDMA_ATTR_HIGH_PRIORITY 0x00000004
199 #define UDMA_ATTR_REQMASK 0x00000008
200 #define UDMA_ATTR_ALL 0x0000000F
201 
202 //*****************************************************************************
203 //
204 // DMA control modes that can be passed to uDMAModeSet() and returned
205 // uDMAModeGet().
206 //
207 //*****************************************************************************
208 #define UDMA_MODE_STOP 0x00000000
209 #define UDMA_MODE_BASIC 0x00000001
210 #define UDMA_MODE_AUTO 0x00000002
211 #define UDMA_MODE_PINGPONG 0x00000003
212 #define UDMA_MODE_MEM_SCATTER_GATHER \
213  0x00000004
214 #define UDMA_MODE_PER_SCATTER_GATHER \
215  0x00000006
216 #define UDMA_MODE_ALT_SELECT 0x00000001
217 
218 //*****************************************************************************
219 //
220 // Flags to be OR'd with the channel ID to indicate if the primary or alternate
221 // control structure should be used.
222 //
223 //*****************************************************************************
224 #define UDMA_PRI_SELECT 0x00000000
225 #define UDMA_ALT_SELECT 0x00000020
226 
227 //*****************************************************************************
228 //
229 // uDMA interrupt sources, to be passed to uDMAIntRegister() and
230 // uDMAIntUnregister().
231 //
232 //*****************************************************************************
233 #define UDMA_INT_SW INT_UDMA
234 #define UDMA_INT_ERR INT_UDMAERR
235 
236 //*****************************************************************************
237 
238 //*****************************************************************************
239 //
240 // Channel configuration values that can be passed to uDMAControlSet().
241 //
242 //*****************************************************************************
243 #define UDMA_DST_INC_8 0x00000000
244 #define UDMA_DST_INC_16 0x40000000
245 #define UDMA_DST_INC_32 0x80000000
246 #define UDMA_DST_INC_NONE 0xc0000000
247 #define UDMA_SRC_INC_8 0x00000000
248 #define UDMA_SRC_INC_16 0x04000000
249 #define UDMA_SRC_INC_32 0x08000000
250 #define UDMA_SRC_INC_NONE 0x0c000000
251 #define UDMA_SIZE_8 0x00000000
252 #define UDMA_SIZE_16 0x11000000
253 #define UDMA_SIZE_32 0x22000000
254 #define UDMA_ARB_1 0x00000000
255 #define UDMA_ARB_2 0x00004000
256 #define UDMA_ARB_4 0x00008000
257 #define UDMA_ARB_8 0x0000c000
258 #define UDMA_ARB_16 0x00010000
259 #define UDMA_ARB_32 0x00014000
260 #define UDMA_ARB_64 0x00018000
261 #define UDMA_ARB_128 0x0001c000
262 #define UDMA_ARB_256 0x00020000
263 #define UDMA_ARB_512 0x00024000
264 #define UDMA_ARB_1024 0x00028000
265 #define UDMA_NEXT_USEBURST 0x00000008
266 
267 //*****************************************************************************
268 //
269 // Values that can be passed to uDMAChannelAssign() to select peripheral
270 // mapping for each channel. The channels named RESERVED may be assigned
271 // to a peripheral in future parts.
272 //
273 //*****************************************************************************
274 //
275 // Channel 0
276 //
277 #define UDMA_CH0_TIMERA0_A 0x00000000
278 #define UDMA_CH0_SHAMD5_CIN 0x00010000
279 #define UDMA_CH0_SW 0x00030000
280 
281 //
282 // Channel 1
283 //
284 #define UDMA_CH1_TIMERA0_B 0x00000001
285 #define UDMA_CH1_SHAMD5_DIN 0x00010001
286 #define UDMA_CH1_SW 0x00030001
287 
288 //
289 // Channel 2
290 //
291 #define UDMA_CH2_TIMERA1_A 0x00000002
292 #define UDMA_CH2_SHAMD5_COUT 0x00010002
293 #define UDMA_CH2_SW 0x00030002
294 
295 //
296 // Channel 3
297 //
298 #define UDMA_CH3_TIMERA1_B 0x00000003
299 #define UDMA_CH3_DES_CIN 0x00010003
300 #define UDMA_CH3_SW 0x00030003
301 
302 //
303 // Channel 4
304 //
305 #define UDMA_CH4_TIMERA2_A 0x00000004
306 #define UDMA_CH4_DES_DIN 0x00010004
307 #define UDMA_CH4_I2S_RX 0x00020004
308 #define UDMA_CH4_SW 0x00030004
309 
310 //
311 // Channel 5
312 //
313 #define UDMA_CH5_TIMERA2_B 0x00000005
314 #define UDMA_CH5_DES_DOUT 0x00010005
315 #define UDMA_CH5_I2S_TX 0x00020005
316 #define UDMA_CH5_SW 0x00030005
317 
318 //
319 // Channel 6
320 //
321 #define UDMA_CH6_TIMERA3_A 0x00000006
322 #define UDMA_CH6_GSPI_RX 0x00010006
323 #define UDMA_CH6_GPIOA2 0x00020006
324 #define UDMA_CH6_SW 0x00030006
325 
326 //
327 // Channel 7
328 //
329 #define UDMA_CH7_TIMERA3_B 0x00000007
330 #define UDMA_CH7_GSPI_TX 0x00010007
331 #define UDMA_CH7_GPIOA3 0x00020007
332 #define UDMA_CH7_SW 0x00030007
333 
334 
335 //
336 // Channel 8
337 //
338 #define UDMA_CH8_UARTA0_RX 0x00000008
339 #define UDMA_CH8_TIMERA0_A 0x00010008
340 #define UDMA_CH8_TIMERA2_A 0x00020008
341 #define UDMA_CH8_SW 0x00030008
342 
343 
344 //
345 // Channel 9
346 //
347 #define UDMA_CH9_UARTA0_TX 0x00000009
348 #define UDMA_CH9_TIMERA0_B 0x00010009
349 #define UDMA_CH9_TIMERA2_B 0x00020009
350 #define UDMA_CH9_SW 0x00030009
351 
352 
353 //
354 // Channel 10
355 //
356 #define UDMA_CH10_UARTA1_RX 0x0000000A
357 #define UDMA_CH10_TIMERA1_A 0x0001000A
358 #define UDMA_CH10_TIMERA3_A 0x0002000A
359 #define UDMA_CH10_SW 0x0003000A
360 
361 //
362 // Channel 11
363 //
364 #define UDMA_CH11_UARTA1_TX 0x0000000B
365 #define UDMA_CH11_TIMERA1_B 0x0001000B
366 #define UDMA_CH11_TIMERA3_B 0x0002000B
367 #define UDMA_CH11_SW 0x0003000B
368 
369 
370 //
371 // Channel 12
372 //
373 #define UDMA_CH12_LSPI_RX 0x0000000C
374 #define UDMA_CH12_SW 0x0003000C
375 
376 
377 //
378 // Channel 13
379 //
380 #define UDMA_CH13_LSPI_TX 0x0000000D
381 #define UDMA_CH13_SW 0x0003000D
382 
383 
384 //
385 // Channel 14
386 //
387 #define UDMA_CH14_ADC_CH0 0x0000000E
388 #define UDMA_CH14_SDHOST_RX 0x0002000E
389 #define UDMA_CH14_SW 0x0003000E
390 
391 
392 //
393 // Channel 15
394 //
395 #define UDMA_CH15_ADC_CH1 0x0000000F
396 #define UDMA_CH15_SDHOST_TX 0x0002000F
397 #define UDMA_CH15_SW 0x0003000F
398 
399 
400 //
401 // Channel 16
402 //
403 #define UDMA_CH16_ADC_CH2 0x00000010
404 #define UDMA_CH16_TIMERA2_A 0x00010010
405 #define UDMA_CH16_SW 0x00030010
406 
407 
408 //
409 // Channel 17
410 //
411 #define UDMA_CH17_ADC_CH3 0x00000011
412 #define UDMA_CH17_TIMERA2_B 0x00010011
413 #define UDMA_CH17_SW 0x00030011
414 
415 //
416 // Channel 18
417 //
418 #define UDMA_CH18_GPIOA0 0x00000012
419 #define UDMA_CH18_AES_CIN 0x00010012
420 #define UDMA_CH18_I2S_RX 0x00020012
421 #define UDMA_CH18_SW 0x00030012
422 
423 
424 //
425 // Channel 19
426 //
427 #define UDMA_CH19_GPOIA1 0x00000013
428 #define UDMA_CH19_AES_COUT 0x00010013
429 #define UDMA_CH19_I2S_TX 0x00020013
430 #define UDMA_CH19_SW 0x00030013
431 
432 
433 //
434 // Channel 20
435 //
436 #define UDMA_CH20_GPIOA2 0x00000014
437 #define UDMA_CH20_AES_DIN 0x00010014
438 #define UDMA_CH20_SW 0x00030014
439 
440 
441 //
442 // Channel 21
443 //
444 #define UDMA_CH21_GPIOA3 0x00000015
445 #define UDMA_CH21_AES_DOUT 0x00010015
446 #define UDMA_CH21_SW 0x00030015
447 
448 
449 //
450 // Channel 22
451 //
452 #define UDMA_CH22_CAMERA 0x00000016
453 #define UDMA_CH22_GPIOA4 0x00010016
454 #define UDMA_CH22_SW 0x00030016
455 
456 
457 //
458 // Channel 23
459 //
460 #define UDMA_CH23_SDHOST_RX 0x00000017
461 #define UDMA_CH23_TIMERA3_A 0x00010017
462 #define UDMA_CH23_TIMERA2_A 0x00020017
463 #define UDMA_CH23_SW 0x00030017
464 
465 
466 //
467 // Channel 24
468 //
469 #define UDMA_CH24_SDHOST_TX 0x00000018
470 #define UDMA_CH24_TIMERA3_B 0x00010018
471 #define UDMA_CH24_TIMERA2_B 0x00020018
472 #define UDMA_CH24_SW 0x00030018
473 
474 
475 //
476 // Channel 25
477 //
478 #define UDMA_CH25_SSPI_RX 0x00000019
479 #define UDMA_CH25_I2CA0_RX 0x00010019
480 #define UDMA_CH25_SW 0x00030019
481 
482 
483 //
484 // Channel 26
485 //
486 #define UDMA_CH26_SSPI_TX 0x0000001A
487 #define UDMA_CH26_I2CA0_TX 0x0001001A
488 #define UDMA_CH26_SW 0x0003001A
489 
490 
491 //
492 // Channel 27
493 //
494 #define UDMA_CH27_GPIOA0 0x0001001B
495 #define UDMA_CH27_SW 0x0003001B
496 
497 
498 //
499 // Channel 28
500 //
501 #define UDMA_CH28_GPIOA1 0x0001001C
502 #define UDMA_CH28_SW 0x0003001C
503 
504 
505 //
506 // Channel 29
507 //
508 #define UDMA_CH29_GPIOA4 0x0000001D
509 #define UDMA_CH29_SW 0x0003001D
510 
511 
512 //
513 // Channel 30
514 //
515 #define UDMA_CH30_GSPI_RX 0x0000001E
516 #define UDMA_CH30_SDHOST_RX 0x0001001E
517 #define UDMA_CH30_I2CA0_RX 0x0002001E
518 #define UDMA_CH30_SW 0x0003001E
519 
520 
521 //
522 // Channel 31
523 //
524 #define UDMA_CH31_GSPI_TX 0x0000001F
525 #define UDMA_CH31_SDHOST_TX 0x0001001F
526 #define UDMA_CH31_I2CA0_RX 0x0002001F
527 #define UDMA_CH31_SW 0x0003001F
528 
529 //*****************************************************************************
530 //
531 // The following are defines for the Micro Direct Memory Access (uDMA) offsets.
532 //
533 //*****************************************************************************
534 #define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
535  // Pointer
536 #define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
537  // End Pointer
538 #define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
539 
540 //*****************************************************************************
541 //
542 // The following are defines for the bit fields in the UDMA_O_SRCENDP register.
543 //
544 //*****************************************************************************
545 #define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
546 #define UDMA_SRCENDP_ADDR_S 0
547 
548 //*****************************************************************************
549 //
550 // The following are defines for the bit fields in the UDMA_O_DSTENDP register.
551 //
552 //*****************************************************************************
553 #define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
554 #define UDMA_DSTENDP_ADDR_S 0
555 
556 //*****************************************************************************
557 //
558 // The following are defines for the bit fields in the UDMA_O_CHCTL register.
559 //
560 //*****************************************************************************
561 #define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
562 #define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
563 #define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
564 #define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
565 #define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
566 #define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
567 #define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
568 #define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
569 #define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
570 #define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
571 #define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
572 #define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
573 #define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
574 #define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
575 #define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
576 #define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
577 #define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
578 #define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
579 #define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
580 #define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
581 #define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
582 #define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
583 #define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
584 #define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
585 #define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
586 #define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
587 #define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
588 #define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
589 #define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
590 #define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
591 #define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
592 #define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
593 #define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
594 #define UDMA_CHCTL_XFERMODE_STOP \
595  0x00000000 // Stop
596 #define UDMA_CHCTL_XFERMODE_BASIC \
597  0x00000001 // Basic
598 #define UDMA_CHCTL_XFERMODE_AUTO \
599  0x00000002 // Auto-Request
600 #define UDMA_CHCTL_XFERMODE_PINGPONG \
601  0x00000003 // Ping-Pong
602 #define UDMA_CHCTL_XFERMODE_MEM_SG \
603  0x00000004 // Memory Scatter-Gather
604 #define UDMA_CHCTL_XFERMODE_MEM_SGA \
605  0x00000005 // Alternate Memory Scatter-Gather
606 #define UDMA_CHCTL_XFERMODE_PER_SG \
607  0x00000006 // Peripheral Scatter-Gather
608 #define UDMA_CHCTL_XFERMODE_PER_SGA \
609  0x00000007 // Alternate Peripheral
610  // Scatter-Gather
611 #define UDMA_CHCTL_XFERSIZE_S 4
612 
613 
614 
615 //*****************************************************************************
616 //
617 // API Function prototypes
618 //
619 //*****************************************************************************
620 extern void uDMAEnable(void);
621 extern void uDMADisable(void);
622 extern unsigned long uDMAErrorStatusGet(void);
623 extern void uDMAErrorStatusClear(void);
624 extern void uDMAChannelEnable(unsigned long ulChannelNum);
625 extern void uDMAChannelDisable(unsigned long ulChannelNum);
626 extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum);
627 extern void uDMAControlBaseSet(void *pControlTable);
628 extern void *uDMAControlBaseGet(void);
629 extern void *uDMAControlAlternateBaseGet(void);
630 extern void uDMAChannelRequest(unsigned long ulChannelNum);
631 extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum,
632  unsigned long ulAttr);
633 extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum,
634  unsigned long ulAttr);
635 extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum);
636 extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex,
637  unsigned long ulControl);
638 extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex,
639  unsigned long ulMode, void *pvSrcAddr,
640  void *pvDstAddr,
641  unsigned long ulTransferSize);
642 extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum,
643  unsigned ulTaskCount, void *pvTaskList,
644  unsigned long ulIsPeriphSG);
645 extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex);
646 extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex);
647 extern void uDMAIntRegister(unsigned long ulIntChannel,
648  void (*pfnHandler)(void));
649 extern void uDMAIntUnregister(unsigned long ulIntChannel);
650 extern unsigned long uDMAIntStatus(void);
651 extern void uDMAIntClear(unsigned long ulChanMask);
652 extern void uDMAChannelAssign(unsigned long ulMapping);
653 
654 //*****************************************************************************
655 //
656 // Mark the end of the C bindings section for C++ compilers.
657 //
658 //*****************************************************************************
659 #ifdef __cplusplus
660 }
661 #endif
662 
663 #endif // __UDMA_H__
unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex)
Definition: udma.c:941
void * uDMAControlAlternateBaseGet(void)
Definition: udma.c:291
void uDMAChannelEnable(unsigned long ulChannelNum)
Definition: udma.c:153
void uDMAIntUnregister(unsigned long ulIntChannel)
Definition: udma.c:1121
unsigned long uDMAErrorStatusGet(void)
Definition: udma.c:107
void uDMAChannelRequest(unsigned long ulChannelNum)
Definition: udma.c:321
void uDMAChannelAttributeEnable(unsigned long ulChannelNum, unsigned long ulAttr)
Definition: udma.c:357
void uDMAChannelAssign(unsigned long ulMapping)
Definition: udma.c:1217
void uDMAIntClear(unsigned long ulChanMask)
Definition: udma.c:1183
void uDMAChannelControlSet(unsigned long ulChannelStructIndex, unsigned long ulControl)
Definition: udma.c:604
void uDMAChannelDisable(unsigned long ulChannelNum)
Definition: udma.c:180
void uDMAChannelTransferSet(unsigned long ulChannelStructIndex, unsigned long ulMode, void *pvSrcAddr, void *pvDstAddr, unsigned long ulTransferSize)
Definition: udma.c:712
void * uDMAControlBaseGet(void)
Definition: udma.c:270
tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum)
Definition: udma.c:207
void uDMAIntRegister(unsigned long ulIntChannel, void(*pfnHandler)(void))
Definition: udma.c:1084
void uDMAControlBaseSet(void *pControlTable)
Definition: udma.c:243
void uDMAEnable(void)
Definition: udma.c:68
void uDMAChannelAttributeDisable(unsigned long ulChannelNum, unsigned long ulAttr)
Definition: udma.c:430
Definition: udma.h:68
void uDMAErrorStatusClear(void)
Definition: udma.c:127
void uDMAChannelScatterGatherSet(unsigned long ulChannelNum, unsigned ulTaskCount, void *pvTaskList, unsigned long ulIsPeriphSG)
Definition: udma.c:863
unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex)
Definition: udma.c:1011
void uDMADisable(void)
Definition: udma.c:87
unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum)
Definition: udma.c:501
unsigned long uDMAIntStatus(void)
Definition: udma.c:1154