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37
38 package ti.sysbios.family.c66;
39
40 import xdc.rov.ViewInfo;
41
42 /*!
43 * ======== Cache ========
44 * Cache Module
45 *
46 * This Cache module provides C66 family-specific implementations of the
47 * APIs defined in {@link ti.sysbios.interfaces.ICache ICache}. It also
48 * provides additional C66 specific cache functions.
49 *
50 * Unconstrained Functions
51 * All functions
52 *
53 * @p(html)
54 * <h3> Calling Context </h3>
55 * <table border="1" cellpadding="3">
56 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
57 *
58 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
59 * <!-- -->
60 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
61 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
62 * <tr><td> {@link #getMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
63 * <tr><td> {@link #getMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
64 * <tr><td> {@link #getSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
65 * <tr><td> {@link #inv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
66 * <tr><td> {@link #invL1pAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
67 * <tr><td> {@link #setMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
68 * <tr><td> {@link #setMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
69 * <tr><td> {@link #setSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
70 * <tr><td> {@link #wait} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
71 * <tr><td> {@link #wb} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
72 * <tr><td> {@link #wbAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
73 * <tr><td> {@link #wbInv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
74 * <tr><td> {@link #wbInvAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
75 * <tr><td colspan="6"> Definitions: <br />
76 * <ul>
77 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
78 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
79 * <li> <b>Task</b>: API is callable from a Task thread. </li>
80 * <li> <b>Main</b>: API is callable during any of these phases: </li>
81 * <ul>
82 * <li> In your module startup after this module is started (e.g. Mod_Module_startupDone() returns TRUE). </li>
83 * <li> During xdc.runtime.Startup.lastFxns. </li>
84 * <li> During main().</li>
85 * <li> During BIOS.startupFxns.</li>
86 * </ul>
87 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
88 * <ul>
89 * <li> During xdc.runtime.Startup.firstFxns.</li>
90 * <li> In your module startup before this module is started (e.g. Mod_Module_startupDone() returns FALSE).</li>
91 * </ul>
92 * <li> <b>*</b>: These APIs are intended to be made at initialization time, but are not restricted to this. </li>
93 * </ul>
94 * </td></tr>
95 *
96 * </table>
97 * @p
98 */
99
100 @ModuleStartup
101
102 module Cache inherits ti.sysbios.interfaces.ICache
103 {
104
105
106 /*!
107 * ======== ModuleView ========
108 * @_nodoc
109 */
110 metaonly struct ModuleView {
111 String L1PCacheSize;
112 String L1PMode;
113 String L1DCacheSize;
114 String L1DMode;
115 String L2CacheSize;
116 String L2Mode;
117 };
118
119 /*!
120 * ======== MarRegisterView ========
121 * @_nodoc
122 */
123 metaonly struct MarRegisterView {
124 UInt number;
125 Ptr addr;
126 Ptr startAddrRange;
127 Ptr endAddrRange;
128 Bool cacheable;
129 Bool prefetchable;
130 String marRegisterValue;
131 };
132
133 /*!
134 * ======== rovViewInfo ========
135 * @_nodoc
136 */
137 @Facet
138 metaonly config ViewInfo.Instance rovViewInfo =
139 ViewInfo.create({
140 viewMap: [
141 ['Module',
142 {
143 type: ViewInfo.MODULE,
144 viewInitFxn: 'viewInitModule',
145 structName: 'ModuleView'
146 }
147 ],
148 ['EnableMARs',
149 {
150 type: xdc.rov.ViewInfo.MODULE_DATA,
151 viewInitFxn: 'viewInitMarRegisters',
152 structName: 'MarRegisterView'
153 }
154 ]
155 ]
156 });
157
158 /*! Lists of cache modes for L1/L2 caches */
159 enum Mode {
160 Mode_FREEZE, /*! No new cache lines are allocated */
161 Mode_BYPASS, /*! All access result in long-distance access */
162 Mode_NORMAL /*! Normal operation of cache */
163 };
164
165 /*! Level 1 cache size type definition. Can be used for both L1D & L1P */
166 enum L1Size {
167 L1Size_0K = 0, /*! Amount of cache is 0K, Amount of SRAM is 32K */
168 L1Size_4K = 1, /*! Amount of cache is 4K, Amount of SRAM is 28K */
169 L1Size_8K = 2, /*! Amount of cache is 8K, Amount of SRAM is 24K */
170 L1Size_16K = 3, /*! Amount of cache is 16K, Amount of SRAM is 16K */
171 L1Size_32K = 4 /*! Amount of cache is 32K, Amount of SRAM is 0K */
172 };
173
174 /*! Level 2 cache size type definition. */
175 enum L2Size {
176 L2Size_0K = 0, /*! L2 is all SRAM */
177 L2Size_32K = 1, /*! Amount of cache is 32K */
178 L2Size_64K = 2, /*! Amount of cache is 64K */
179 L2Size_128K = 3, /*! Amount of cache is 128K */
180 L2Size_256K = 4, /*! Amount of cache is 256K */
181 L2Size_512K = 5, /*! Amount of cache is 512K */
182 L2Size_1024K = 6 /*! Amount of cache is 1024K */
183 };
184
185 /*! MAR register setting type definition. */
186 enum Mar {
187 Mar_DISABLE = 0, /*! The Permit Copy bit of MAR register is disabled */
188 Mar_ENABLE = 1 /*! The Permit Copy bit of MAR register is enabled */
189 };
190
191 const UInt32 PC = 1; /*! Permit Caching */
192 const UInt32 WTE = 2; /*! Write through enabled */
193 const UInt32 PCX = 4; /*! Permit caching in external cache */
194 const UInt32 PFX = 8; /*! Prefetchable by external engines */
195
196 /*! Structure for specifying all cache sizes. */
197 struct Size {
198 L1Size l1pSize; /*! L1 Program cache size */
199 L1Size l1dSize; /*! L1 Data data size */
200 L2Size l2Size; /*! L2 cache size */
201 };
202
203 /*! Default sizes of caches.
204 * @_nodoc
205 */
206 config Size initSize = {
207 l1pSize: L1Size_32K,
208 l1dSize: L1Size_32K,
209 l2Size: L2Size_0K
210 };
211
212 /*! @_nodoc
213 * MAR 00 - 31 register bitmask. (for addresses 0x00000000 - 0x1FFFFFFF)
214 *
215 * If undefined by the user, this parameter is configured to match the
216 * memory map of the platform.
217 * Each memory region defined in the platform will have all of its
218 * corresponding MAR bits set.
219 *
220 * To override the default behavior you must initialize this parameter
221 * in your configuration script:
222 *
223 * @p(code)
224 * // disable MAR bits for addresses 0x00000000 to 0x1FFFFFFF
225 * Cache.MAR0_31 = 0x00000000;
226 * @p
227 */
228 metaonly config UInt32 MAR0_31;
229
230 /*! @_nodoc
231 * MAR 32 - 63 register bitmask (for addresses 0x20000000 - 0x3FFFFFFF)
232 *
233 * see {@link #MAR0_31} for more info
234 */
235 metaonly config UInt32 MAR32_63;
236
237 /*! @_nodoc
238 * MAR 64 - 95 register bitmask (for addresses 0x40000000 - 0x5FFFFFFF)
239 *
240 * see {@link #MAR0_31} for more info
241 */
242 metaonly config UInt32 MAR64_95;
243
244 /*! @_nodoc
245 * MAR 96 - 127 register bitmask (for addresses 0x60000000 - 0x7FFFFFFF)
246 *
247 * see {@link #MAR0_31} for more info
248 */
249 metaonly config UInt32 MAR96_127;
250
251 /*! @_nodoc
252 * MAR 128 - 159 register bitmask (for addresses 0x80000000 - 0x9FFFFFFF)
253 *
254 * see {@link #MAR0_31} for more info
255 */
256 metaonly config UInt32 MAR128_159;
257
258 /*! @_nodoc
259 * MAR 160 - 191 register bitmask (for addresses 0xA0000000 - 0xBFFFFFFF)
260 *
261 * see {@link #MAR0_31} for more info
262 */
263 metaonly config UInt32 MAR160_191;
264
265 /*! @_nodoc
266 * MAR 192 - 223 register bitmask (for addresses 0xC0000000 - 0xDFFFFFFF)
267 *
268 * see {@link #MAR0_31} for more info
269 */
270 metaonly config UInt32 MAR192_223;
271
272 /*! @_nodoc
273 * MAR 224 - 255 register bitmask (for addresses 0xE0000000 - 0xFFFFFFFF)
274 *
275 * see {@link #MAR0_31} for more info
276 */
277 metaonly config UInt32 MAR224_255;
278
279 /*! @_nodoc
280 *
281 * This parameter is used to break up large blocks into multiple
282 * small blocks which are done atomically. Each block of the
283 * specified size waits for the cache operation to finish before
284 * starting the next block. Setting this size to 0, means the
285 * cache operations are not done atomically.
286 */
287 config UInt32 atomicBlockSize = 1024;
288
289 /*!
290 * ======== getMarMeta ========
291 * Gets the current MAR value for the specified base address
292 *
293 * @param(baseAddr) address for which MAR value is requested
294 *
295 * @b(returns) MAR value for specified address
296 */
297 metaonly UInt32 getMarMeta(Ptr baseAddr);
298
299 /*!
300 * ======== setMarMeta ========
301 * Set MAR register(s) that corresponds to the specified address range.
302 *
303 * The 'pc' ("Permit Caching") field is enabled for all memory regions
304 * in the device platform. Only set the fields of the Mar structure
305 * which need to be modified. Any field not set retains its reset value.
306 *
307 * @a(Note)
308 * The 'wte' (Bit 1) and 'pcx' (Bit 2) MAR bits are reserved on
309 * C66x CorePac devices.
310 *
311 * @param(baseAddr) start address for which to set MAR
312 * @param(byteSize) size (in bytes) of memory block
313 * @param(value) value for setting MAR register
314 */
315 metaonly Void setMarMeta(Ptr baseAddr, SizeT byteSize, UInt32 value);
316
317 /*!
318 * ======== disable ========
319 * Disables the 'type' cache(s)
320 *
321 * Disabling of L2 cache is currently not supported.
322 */
323 @DirectCall
324 override Void disable(Bits16 type);
325
326 /*!
327 * ======== getMode ========
328 * Get mode of a cache
329 *
330 * @param(type) bit mask of cache type
331 * @b(returns) mode of specified level of cache
332 */
333 @DirectCall
334 Mode getMode(Bits16 type);
335
336 /*!
337 * ======== setMode ========
338 * Set mode of a cache
339 *
340 * @param(type) bit mask of cache type
341 * @param(mode) mode of cache
342 *
343 * @b(returns) previous mode of cache
344 */
345 @DirectCall
346 Mode setMode(Bits16 type, Mode mode);
347
348 /*!
349 * ======== getSize ========
350 * Get sizes of all caches
351 *
352 * @param(size) pointer to structure of type Cache_Size
353 */
354 @DirectCall
355 Void getSize(Size *size);
356
357 /*!
358 * ======== setSize ========
359 * Set sizes of all caches
360 *
361 * @param(size) pointer to structure of type Cache_Size
362 */
363 @DirectCall
364 Void setSize(Size *size);
365
366 /*!
367 * ======== getMar ========
368 * Gets the MAR register for the specified base address
369 *
370 * @param(baseAddr) address for which MAR is requested
371 *
372 * @b(returns) value of MAR register
373 */
374 @DirectCall
375 UInt32 getMar(Ptr baseAddr);
376
377 /*!
378 * ======== setMar ========
379 * Set MAR register(s) that corresponds to the specified address range.
380 *
381 * All cached entries in L1 and L2 are written back and invalidated.
382 *
383 * @a(Note)
384 * The 'wte' (Bit 1) and 'pcx' (Bit 2) MAR bits are reserved on
385 * C66x CorePac devices.
386 *
387 * @param(baseAddr) start address for which to set MAR
388 * @param(byteSize) size (in bytes) of memory block
389 * @param(value) value for setting MAR register
390 */
391 @DirectCall
392 Void setMar(Ptr baseAddr, SizeT byteSize, UInt32 value);
393
394 /*!
395 * ======== invL1pAll ========
396 * Invalidate all of L1 Program cache
397 *
398 * Performs a global invalidate of L1P cache.
399 * Polls the L1P invalidate register until done.
400 */
401 @DirectCall
402 Void invL1pAll();
403
404 /*!
405 * ======== wbAll ========
406 * Write back all caches
407 *
408 * Perform a global write back. There is no effect on L1P cache.
409 * All cache lines are left valid in L1D cache and the data in L1D cache
410 * is written back to L2 or external. All cache lines are left valid in
411 * L2 cache and the data in L2 cache is written back to external.
412 */
413 @DirectCall
414 override Void wbAll();
415
416 /*!
417 * ======== wbInvAll ========
418 * Write back invalidate all caches
419 *
420 * Performs a global write back and invalidate. All cache lines are
421 * invalidated in L1P cache. All cache lines are written back to L2 or
422 * external and then invalidated in L1D cache. All cache lines are
423 * written back to external and then invalidated in L2 cache.
424 */
425 @DirectCall
426 override Void wbInvAll();
427
428
429 internal:
430
431 /*!
432 * ======== invPrefetchBuffer ========
433 * Invalidate the prefetch buffer
434 */
435 Void invPrefetchBuffer();
436
437 438 439
440 Void all(volatile UInt32 *cacheReg);
441
442 443 444 445
446 Void block(Ptr blockPtr, SizeT byteCnt, Bool wait,
447 volatile UInt32 *barReg);
448
449
450 const UInt32 L2CFG = 0x01840000;
451 const UInt32 L1PCFG = 0x01840020;
452 const UInt32 L1PCC = 0x01840024;
453 const UInt32 L1DCFG = 0x01840040;
454 const UInt32 L1DCC = 0x01840044;
455 const UInt32 MAR = 0x01848000;
456
457
458 config UInt32 marvalues[256];
459 }