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37
38 package ti.sysbios.family.c64p;
39
40 import xdc.rov.ViewInfo;
41
42 /*!
43 * ======== Cache ========
44 * Cache Module
45 *
46 * This Cache module provides C64+ family-specific implementations of the
47 * APIs defined in {@link ti.sysbios.interfaces.ICache ICache}. It also
48 * provides additional C64+ specific cache functions.
49 *
50 * Unconstrained Functions
51 * All functions
52 *
53 * @p(html)
54 * <h3> Calling Context </h3>
55 * <table border="1" cellpadding="3">
56 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
57 *
58 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
59 * <!-- -->
60 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
61 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
62 * <tr><td> {@link #getMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
63 * <tr><td> {@link #getMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
64 * <tr><td> {@link #getSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
65 * <tr><td> {@link #inv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
66 * <tr><td> {@link #invL1pAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
67 * <tr><td> {@link #setMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
68 * <tr><td> {@link #setMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
69 * <tr><td> {@link #setSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
70 * <tr><td> {@link #wait} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
71 * <tr><td> {@link #wb} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
72 * <tr><td> {@link #wbAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
73 * <tr><td> {@link #wbInv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
74 * <tr><td> {@link #wbInvAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
75 * <tr><td colspan="6"> Definitions: <br />
76 * <ul>
77 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
78 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
79 * <li> <b>Task</b>: API is callable from a Task thread. </li>
80 * <li> <b>Main</b>: API is callable during any of these phases: </li>
81 * <ul>
82 * <li> In your module startup after this module is started (e.g. Mod_Module_startupDone() returns TRUE). </li>
83 * <li> During xdc.runtime.Startup.lastFxns. </li>
84 * <li> During main().</li>
85 * <li> During BIOS.startupFxns.</li>
86 * </ul>
87 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
88 * <ul>
89 * <li> During xdc.runtime.Startup.firstFxns.</li>
90 * <li> In your module startup before this module is started (e.g. Mod_Module_startupDone() returns FALSE).</li>
91 * </ul>
92 * <li> <b>*</b>: These APIs are intended to be made at initialization time, but are not restricted to this. </li>
93 * </ul>
94 * </td></tr>
95 *
96 * </table>
97 * @p
98 */
99
100 @ModuleStartup
101
102 module Cache inherits ti.sysbios.interfaces.ICache
103 {
104
105
106 /*!
107 * ======== ModuleView ========
108 * @_nodoc
109 */
110 metaonly struct ModuleView {
111 String L1PCacheSize;
112 String L1PMode;
113 String L1DCacheSize;
114 String L1DMode;
115 String L2CacheSize;
116 String L2Mode;
117 };
118
119 /*!
120 * ======== MarRegisterView ========
121 * @_nodoc
122 */
123 metaonly struct MarRegisterView {
124 UInt number;
125 Ptr addr;
126 Ptr startAddrRange;
127 Ptr endAddrRange;
128 };
129
130 /*!
131 * ======== rovViewInfo ========
132 * @_nodoc
133 */
134 @Facet
135 metaonly config ViewInfo.Instance rovViewInfo =
136 ViewInfo.create({
137 viewMap: [
138 ['Module',
139 {
140 type: ViewInfo.MODULE,
141 viewInitFxn: 'viewInitModule',
142 structName: 'ModuleView'
143 }
144 ],
145 ['EnableMARs',
146 {
147 type: xdc.rov.ViewInfo.MODULE_DATA,
148 viewInitFxn: 'viewInitMarRegisters',
149 structName: 'MarRegisterView'
150 }
151 ]
152 ]
153 });
154
155 /*! Lists of cache modes for L1/L2 caches */
156 enum Mode {
157 Mode_FREEZE, /*! No new cache lines are allocated */
158 Mode_BYPASS, /*! All access result in long-distance access */
159 Mode_NORMAL /*! Normal operation of cache */
160 };
161
162 /*! Level 1 cache size type definition. Can be used for both L1D & L1P */
163 enum L1Size {
164 L1Size_0K = 0, /*! Amount of cache is 0K, Amount of SRAM is 32K */
165 L1Size_4K = 1, /*! Amount of cache is 4K, Amount of SRAM is 28K */
166 L1Size_8K = 2, /*! Amount of cache is 8K, Amount of SRAM is 24K */
167 L1Size_16K = 3, /*! Amount of cache is 16K, Amount of SRAM is 16K */
168 L1Size_32K = 4 /*! Amount of cache is 32K, Amount of SRAM is 0K */
169 };
170
171 /*! Level 2 cache size type definition. */
172 enum L2Size {
173 L2Size_0K = 0, /*! L2 is all SRAM */
174 L2Size_32K = 1, /*! Amount of cache is 32K */
175 L2Size_64K = 2, /*! Amount of cache is 64K */
176 L2Size_128K = 3, /*! Amount of cache is 128K */
177 L2Size_256K = 4, /*! Amount of cache is 256K */
178 L2Size_512K = 5, /*! Amount of cache is 512K */
179 L2Size_1024K = 6 /*! Amount of cache is 1024K */
180 };
181
182 /*! MAR register setting type definition. */
183 enum Mar {
184 Mar_DISABLE = 0, /*! The Permit Copy bit of MAR register is disabled */
185 Mar_ENABLE = 1 /*! The Permit Copy bit of MAR register is enabled */
186 };
187
188 /*! Structure for specifying all cache sizes. */
189 struct Size {
190 L1Size l1pSize; /*! L1 Program cache size */
191 L1Size l1dSize; /*! L1 Data data size */
192 L2Size l2Size; /*! L2 cache size */
193 };
194
195 /*!
196 * Cache sizes.
197 *
198 * When this parameter is set in user's cfg script, user set cache sizes
199 * override those specified by the Cache module or the platform.
200 */
201 config Size initSize = {
202 l1pSize: L1Size_32K,
203 l1dSize: L1Size_32K,
204 l2Size: L2Size_0K
205 };
206
207 /*!
208 * EMIF A configuration address.
209 *
210 * By default, this is set to the physical address. On devices with
211 * a MMU where the physical address is mapped to a virtual address,
212 * the virtual address must be specified here.
213 */
214 config UInt *EMIFA_CFG;
215
216 /*!
217 * EMIF A base register address.
218 *
219 * By default, this is set to the emif A base register physical address.
220 * On devices with a MMU where the physical address is mapped to a virtual
221 * address, the virtual address must be specified here.
222 */
223 config UInt EMIFA_BASE;
224
225 /*!
226 * EMIF A address space length.
227 */
228 config UInt EMIFA_LENGTH;
229
230 /*!
231 * EMIF B configuration address.
232 *
233 * By default, this is set to the physical address. On devices with
234 * a MMU where the physical address is mapped to a virtual address,
235 * the virtual address must be specified here.
236 */
237 config UInt *EMIFB_CFG;
238
239 /*!
240 * EMIF B base register address.
241 *
242 * By default, this is set to the emif B base register physical address.
243 * On devices with a MMU where the physical address is mapped to a virtual
244 * address, the virtual address must be specified here.
245 */
246 config UInt EMIFB_BASE;
247
248 /*!
249 * EMIF B address space length.
250 */
251 config UInt EMIFB_LENGTH;
252
253 /*!
254 * EMIF C configuration address.
255 *
256 * By default, this is set to the physical address. On devices with
257 * a MMU where the physical address is mapped to a virtual address,
258 * the virtual address must be specified here.
259 */
260 config UInt *EMIFC_CFG;
261
262 /*!
263 * EMIF C base register address.
264 *
265 * By default, this is set to the emif C base register physical address.
266 * On devices with a MMU where the physical address is mapped to a virtual
267 * address, the virtual address must be specified here.
268 */
269 config UInt EMIFC_BASE;
270
271 /*!
272 * EMIF C address space length.
273 */
274 config UInt EMIFC_LENGTH;
275
276 /*!
277 * MAR 00 - 31 register bitmask. (for addresses 0x00000000 - 0x1FFFFFFF)
278 *
279 * If undefined by the user, this parameter is configured to match the
280 * memory map of the platform.
281 * Each memory region defined in the platform will have all of its
282 * corresponding MAR bits set.
283 *
284 * To override the default behavior you must initialize this parameter
285 * in your configuration script:
286 *
287 * @p(code)
288 * // disable MAR bits for addresses 0x00000000 to 0x1FFFFFFF
289 * Cache.MAR0_31 = 0x00000000;
290 * @p
291 */
292 config UInt32 MAR0_31;
293
294 /*!
295 * MAR 32 - 63 register bitmask (for addresses 0x20000000 - 0x3FFFFFFF)
296 *
297 * see {@link #MAR0_31} for more info
298 */
299 config UInt32 MAR32_63;
300
301 /*!
302 * MAR 64 - 95 register bitmask (for addresses 0x40000000 - 0x5FFFFFFF)
303 *
304 * see {@link #MAR0_31} for more info
305 */
306 config UInt32 MAR64_95;
307
308 /*!
309 * MAR 96 - 127 register bitmask (for addresses 0x60000000 - 0x7FFFFFFF)
310 *
311 * see {@link #MAR0_31} for more info
312 */
313 config UInt32 MAR96_127;
314
315 /*!
316 * MAR 128 - 159 register bitmask (for addresses 0x80000000 - 0x9FFFFFFF)
317 *
318 * see {@link #MAR0_31} for more info
319 */
320 config UInt32 MAR128_159;
321
322 /*!
323 * MAR 160 - 191 register bitmask (for addresses 0xA0000000 - 0xBFFFFFFF)
324 *
325 * see {@link #MAR0_31} for more info
326 */
327 config UInt32 MAR160_191;
328
329 /*!
330 * MAR 192 - 223 register bitmask (for addresses 0xC0000000 - 0xDFFFFFFF)
331 *
332 * see {@link #MAR0_31} for more info
333 */
334 config UInt32 MAR192_223;
335
336 /*!
337 * MAR 224 - 255 register bitmask (for addresses 0xE0000000 - 0xFFFFFFFF)
338 *
339 * see {@link #MAR0_31} for more info
340 */
341 config UInt32 MAR224_255;
342
343 /*!
344 * ======== disable ========
345 * Disables the 'type' cache(s)
346 *
347 * Disabling of L2 cache is currently not supported.
348 */
349 @DirectCall
350 override Void disable(Bits16 type);
351
352 /*!
353 * ======== setMode ========
354 * Set mode of a cache
355 *
356 * @param(type) bit mask of cache type
357 * @param(mode) mode of cache
358 *
359 * @b(returns) previous mode of cache
360 */
361 @DirectCall
362 Mode setMode(Bits16 type, Mode mode);
363
364 /*!
365 * ======== getMode ========
366 * Get mode of a cache
367 *
368 * @param(type) bit mask of cache type
369 * @b(returns) mode of specified level of cache
370 */
371 @DirectCall
372 Mode getMode(Bits16 type);
373
374 /*!
375 * ======== setSize ========
376 * Set sizes of all caches
377 *
378 * @param(size) pointer to structure of type Cache_Size
379 */
380 @DirectCall
381 Void setSize(Size *size);
382
383 /*!
384 * ======== getSize ========
385 * Get sizes of all caches
386 *
387 * @param(size) pointer to structure of type Cache_Size
388 */
389 @DirectCall
390 Void getSize(Size *size);
391
392 /*!
393 * ======== getMar ========
394 * Get the value of the MAR register defined for the specified
395 * base address
396 *
397 * @param(baseAddr) address for which MAR is requested
398 *
399 * @b(returns) value of MAR register associated with specified address
400 */
401 @DirectCall
402 Mar getMar(Ptr baseAddr);
403
404 /*!
405 * ======== setMar ========
406 * Set the MAR register(s) that corresponds to the specified
407 * address range.
408 *
409 * @param(baseAddr) start address for which to set MAR
410 * @param(byteSize) size (in bytes) of memory block
411 * @param(value) enum of type Cache_Mar
412 */
413 @DirectCall
414 Void setMar(Ptr baseAddr, SizeT byteSize, Mar value);
415
416 /*!
417 * ======== invL1pAll ========
418 * Invalidate all of L1 Program cache
419 *
420 * Performs a global invalidate of L1P cache.
421 * Polls the L1P invalidate register until done.
422 */
423 @DirectCall
424 Void invL1pAll();
425
426 /*!
427 * ======== wbAll ========
428 * Write back all caches
429 *
430 * Perform a global write back. There is no effect on L1P cache.
431 * All cache lines are left valid in L1D cache and the data in L1D cache
432 * is written back to L2 or external. All cache lines are left valid in
433 * L2 cache and the data in L2 cache is written back to external.
434 */
435 @DirectCall
436 override Void wbAll();
437
438 /*!
439 * ======== wbInvAll ========
440 * Write back invalidate all caches
441 *
442 * Performs a global write back and invalidate. All cache lines are
443 * invalidated in L1P cache. All cache lines are written back to L2 or
444 * external and then invalidated in L1D cache. All cache lines are
445 * written back to external and then invalidated in L2 cache.
446 */
447 @DirectCall
448 override Void wbInvAll();
449
450 internal:
451
452 Void all(volatile UInt32 *cacheReg);
453
454 455 456 457
458 Void block(Ptr blockPtr, SizeT byteCnt, Bool wait,
459 volatile UInt32 *barReg);
460
461 462 463 464
465 Void marInit(UInt32 mask, UInt32 index);
466
467
468 const UInt32 L2CFG = 0x01840000;
469 const UInt32 L1PCFG = 0x01840020;
470 const UInt32 L1PCC = 0x01840024;
471 const UInt32 L1DCFG = 0x01840040;
472 const UInt32 L1DCC = 0x01840044;
473 const UInt32 MAR = 0x01848000;
474
475 struct Module_State {
476 volatile UInt32 *emifAddr; /*! Emif configuration address */
477 }
478 }