1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
32 33 34 35
36 package ti.sysbios.family.arm.dm6446;
37
38 import xdc.rov.ViewInfo;
39
40 import xdc.runtime.Diags;
41 import xdc.runtime.Error;
42 import xdc.runtime.Log;
43
44 /*!
45 * ======== Hwi ========
46 * Hardware Interrupt Support Module.
47 *
48 * This Hwi module provides ARM family-specific implementations of the
49 * APIs defined in {@link ti.sysbios.interfaces.IHwi IHwi}.
50 *
51 * Additional ARM device-specific APIs are also provided.
52 *
53 * @a(NOTE)
54 * In this Hwi module implementation, the instance config parameter value
55 * {@link #MaskingOption_LOWER} is equivalent to {@link #MaskingOption_SELF}.
56 * Statically configuring a Hwi object's {@link #Params.maskSetting} to
57 * {@link #MaskingOption_LOWER} will result in the generation of a benign
58 * build warning. Dynamic usages of {@link #MaskingOption_LOWER} will be
59 * silently converted to {@link #MaskingOption_SELF}.
60 *
61 * @p(html)
62 * <h3> Calling Context </h3>
63 * <table border="1" cellpadding="3">
64 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
65 *
66 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
67 * <!-- -->
68 * <tr><td> {@link #clearInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
69 * <tr><td> {@link #create} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
70 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
71 * <tr><td> {@link #disableEINT0} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
72 * <tr><td> {@link #disableEINT1} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
73 * <tr><td> {@link #disableFIQ} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
74 * <tr><td> {@link #disableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
75 * <tr><td> {@link #disableIRQ} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
76 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> N </td><td> N </td></tr>
77 * <tr><td> {@link #enableEINT0} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
78 * <tr><td> {@link #enableEINT1} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
79 * <tr><td> {@link #enableFIQ} </td><td> Y </td><td> Y </td><td> Y </td><td> N </td><td> N </td></tr>
80 * <tr><td> {@link #enableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
81 * <tr><td> {@link #enableIRQ} </td><td> Y </td><td> Y </td><td> Y </td><td> N </td><td> N </td></tr>
82 * <tr><td> {@link #getHandle} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
83 * <tr><td> {@link #Params_init} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
84 * <tr><td> {@link #restore} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
85 * <tr><td> {@link #restoreEINT0} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
86 * <tr><td> {@link #restoreEINT1} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
87 * <tr><td> {@link #restoreFIQ} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
88 * <tr><td> {@link #restoreInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
89 * <tr><td> {@link #restoreIRQ} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
90 * <tr><td> {@link #setPriority} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
91 * <tr><td> {@link #construct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
92 * <tr><td> {@link #delete} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
93 * <tr><td> {@link #destruct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
94 * <tr><td> {@link #getHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
95 * <tr><td> {@link #reconfig} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
96 * <tr><td> {@link #setFunc} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
97 * <tr><td> {@link #setHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
98 * <tr><td colspan="6"> Definitions: <br />
99 * <ul>
100 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
101 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
102 * <li> <b>Task</b>: API is callable from a Task thread. </li>
103 * <li> <b>Main</b>: API is callable during any of these phases: </li>
104 * <ul>
105 * <li> In your module startup after this module is started (e.g. Hwi_Module_startupDone() returns TRUE). </li>
106 * <li> During xdc.runtime.Startup.lastFxns. </li>
107 * <li> During main().</li>
108 * <li> During BIOS.startupFxns.</li>
109 * </ul>
110 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
111 * <ul>
112 * <li> During xdc.runtime.Startup.firstFxns.</li>
113 * <li> In your module startup before this module is started (e.g. Hwi_Module_startupDone() returns FALSE).</li>
114 * </ul>
115 * </ul>
116 * </td></tr>
117 *
118 *
119 * </table>
120 * @p
121 */
122
123 @Template("./Hwi.xdt")
124 @ModuleStartup
125
126 module Hwi inherits ti.sysbios.interfaces.IHwi
127 {
128
129
130
131 /*! The DM6446 ARM Interrupt Controller supports 64 interrupts. */
132 const Int NUM_INTERRUPTS = 64;
133
134
135
136 /*! Hwi vector function type definition. */
137 typedef Void (*VectorFuncPtr)(void);
138
139 /*!
140 * ARM Interrupt Controller.
141 */
142 struct AINTC {
143 UInt32 FIQ0; /*! 0x00 Interrupt Status of INT [31:0] if mapped to FIQ */
144 UInt32 FIQ1; /*! 0x04 Interrupt Status of INT [63:32] if mapped to FIQ */
145 UInt32 IRQ0; /*! 0x08 Interrupt Status of INT [31:0] if mapped to IRQ */
146 UInt32 IRQ1; /*! 0x0C Interrupt Status of INT [63:32] if mapped to IRQ */
147 UInt32 FIQENTRY;/*! 0x10 Entry Address [28:0] for valid FIQ interrupt */
148 UInt32 IRQENTRY;/*! 0x14 Entry Address [28:0] for valid IRQ interrupt */
149 UInt32 EINT0; /*! 0x18 Interrupt Enable Register 0 */
150 UInt32 EINT1; /*! 0x1C Interrupt Enable Register 1 */
151 UInt32 INTCTL; /*! 0x20 Interrupt Operation Control Register */
152 UInt32 EABASE; /*! 0x24 Interrupt Entry Base Address */
153 UInt32 RES[2]; /*! 0x28 reserved */
154 UInt32 INTPR[8];/*! 0x30 Interrupt 0-7 Priority select */
155
156
157
158
159
160
161
162 };
163
164 /*!
165 * Physical ARM Interrupt Controller Device.
166 * Short name is "Hwi_aIntc"
167 * Long name is "ti_sysbios_family_arm_dm6446_Hwi_aIntc"
168 */
169 extern volatile AINTC aIntc;
170
171 /*!
172 * ======== BasicView ========
173 * @_nodoc
174 */
175 metaonly struct BasicView {
176 Ptr halHwiHandle;
177 String label;
178 Int intNum;
179 Int priority;
180 String fxn;
181 UArg arg;
182 Ptr irp;
183 String status;
184 };
185
186 /*!
187 * ======== ModuleView ========
188 * @_nodoc
189 */
190 metaonly struct ModuleView {
191 String options[4];
192 SizeT hwiStackPeak;
193 SizeT hwiStackSize;
194 Ptr hwiStackBase;
195 };
196
197 /*!
198 * ======== rovViewInfo ========
199 * @_nodoc
200 */
201 @Facet
202 metaonly config ViewInfo.Instance rovViewInfo =
203 ViewInfo.create({
204 viewMap: [
205 ['Basic', {type: ViewInfo.INSTANCE, viewInitFxn: 'viewInitBasic', structName: 'BasicView'}],
206 ['Module', {type: ViewInfo.MODULE, viewInitFxn: 'viewInitModule', structName: 'ModuleView'}]
207 ]
208 });
209
210
211
212 /*! Reset Handler. Default is c_int00 */
213 metaonly config VectorFuncPtr resetFunc;
214
215 /*! Undefined instruction exception handler. Default is self loop */
216 metaonly config VectorFuncPtr undefinedInstFunc;
217
218 /*! SWI Handler. Default is internal SWI handler */
219 metaonly config VectorFuncPtr swiFunc;
220
221 /*! Prefetch abort exception handler. Default is self loop */
222 metaonly config VectorFuncPtr prefetchAbortFunc;
223
224 /*! Data abort exception handler. Default is self loop */
225 metaonly config VectorFuncPtr dataAbortFunc;
226
227 /*! Reserved exception handler. Default is self loop */
228 metaonly config VectorFuncPtr reservedFunc;
229
230 /*! IRQ interrupt handler. Default is internal IRQ dispatcher */
231 metaonly config VectorFuncPtr irqFunc;
232
233 /*! FIQ interrupt handler. Default is internal FIQ dispatcher */
234 metaonly config VectorFuncPtr fiqFunc;
235
236 /*!
237 * FIQ stack pointer. Default = null.
238 * (Indicates that stack is to be created using
239 * staticPlace()
240 */
241 config Ptr fiqStack = null;
242
243 /*!
244 * FIQ stack size in MAUs.
245 * Default is 1024 bytes.
246 */
247 metaonly config SizeT fiqStackSize = 1024;
248
249 /*!
250 * Memory section used for FIQ stack
251 * Default is null.
252 */
253 metaonly config String fiqStackSection = null;
254
255 /*!
256 * EABASE Size Setting. Default is 4 bytes per entry.
257 * Options are 4, 8, 16, 32 bytes per entry.
258 */
259 config Bits32 eabaseSize = 4;
260
261 /*!
262 * Error raised when Hwi is already defined
263 */
264 config Error.Id E_alreadyDefined = {
265 msg: "E_alreadyDefined: Hwi already defined: intr# %d"
266 };
267
268 /*!
269 * Issued just prior to Hwi function invocation (with interrupts disabled)
270 */
271 config Log.Event LM_begin = {
272 mask: Diags.USER1 | Diags.USER2,
273 msg: "LM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x"
274 };
275
276 /*!
277 * Issued just after return from Hwi function (with interrupts disabled)
278 */
279 config Log.Event LD_end = {
280 mask: Diags.USER2,
281 msg: "LD_end: hwi: 0x%x"
282 };
283
284
285
286
287 /*!
288 * ======== disable ========
289 */
290 @Macro
291 override UInt disable();
292
293 /*!
294 * ======== enable ========
295 */
296 @Macro
297 override UInt enable();
298
299 /*!
300 * ======== restore ========
301 */
302 @Macro
303 override Void restore(UInt key);
304
305 /*!
306 * @_nodoc
307 * ======== inUseMeta ========
308 * Check for Hwi already in use.
309 * For internal SYS/BIOS use only.
310 * Should be called prior to any internal Hwi.create().
311 *
312 * @param(intNum) interrupt number
313 */
314 metaonly Bool inUseMeta(UInt intNum);
315
316 /*!
317 * ======== getHandle ========
318 * Returns pointer to Hwi instance object.
319 *
320 * @param(intNum) interrupt number
321 */
322 @DirectCall
323 Object *getHandle(UInt intNum);
324
325 /*!
326 * @_nodoc
327 * ======== getInstance ========
328 * Returns pointer to Hwi instance object.
329 *
330 * @param(intNum) interrupt number
331 */
332 @DirectCall
333 Object *getInstance(UInt intNum);
334
335 /*!
336 * ======== enableFIQ ========
337 * Enable FIQ interrupts.
338 *
339 * @b(returns) previous FIQ interrupt enable/disable state
340 */
341 @DirectCall
342 UInt enableFIQ();
343
344 /*!
345 * ======== disableFIQ ========
346 * Disable FIQ interrupts.
347 *
348 * @b(returns) previous FIQ interrupt enable/disable state
349 */
350 @DirectCall
351 UInt disableFIQ();
352
353 /*!
354 * ======== restoreFIQ ========
355 * Restore FIQ interrupts.
356 *
357 * @param(key) enable/disable state to restore
358 */
359 @DirectCall
360 Void restoreFIQ(UInt key);
361
362 /*!
363 * ======== enableIRQ ========
364 * Enable IRQ interrupts.
365 *
366 * @param(key) enable/disable state to restore
367 */
368 @DirectCall
369 UInt enableIRQ();
370
371 /*!
372 * ======== disableIRQ ========
373 * Disable IRQ interrupts.
374 *
375 * @b(returns) previous IRQ interrupt enable/disable state
376 */
377 @DirectCall
378 UInt disableIRQ();
379
380 /*!
381 * ======== restoreIRQ ========
382 * Restore IRQ interrupts.
383 *
384 * @param(key) enable/disable state to restore
385 */
386 @DirectCall
387 Void restoreIRQ(UInt key);
388
389 /*!
390 * ======== disableEINT0 ========
391 * Disable specific interrupts (0-31).
392 *
393 * Disables specific interrupts by clearing the bits specified by
394 * 'mask' in the EINT0.
395 *
396 * @param(mask) bitmask of interrupts to disable
397 * @b(returns) previous EINT0 settings bitmask
398 */
399 @DirectCall
400 Bits32 disableEINT0(Bits32 mask);
401
402 /*!
403 * ======== disableEINT1 ========
404 * Disable specific interrupts (32-63).
405 *
406 * Disables specific interrupts by clearing the bits specified by
407 * 'mask' in the EINT1.
408 *
409 * @param(mask) bitmask of interrupts to disable
410 * @b(returns) previous EINT1 settings bitmask
411 */
412 @DirectCall
413 Bits32 disableEINT1(Bits32 mask);
414
415 /*!
416 * ======== enableEINT0 ========
417 * Enable specific interrupts (0-31).
418 *
419 * Enables specific interrupts by clearing the bits specified by
420 * 'mask' in the EINT0.
421 *
422 * @param(mask) bitmask of interrupts to disable
423 * @b(returns) previous EINT0 settings bitmask
424 */
425 @DirectCall
426 Bits32 enableEINT0(Bits32 mask);
427
428 /*!
429 * ======== enableEINT1 ========
430 * Enable specific interrupts (32-63).
431 *
432 * Enables specific interrupts by clearing the bits specified by
433 * 'mask' in the EINT0.
434 *
435 * @param(mask) bitmask of interrupts to disable
436 * @b(returns) previous EINT0 settings bitmask
437 */
438 @DirectCall
439 Bits32 enableEINT1(Bits32 mask);
440
441 /*!
442 * ======== restoreEINT0 ========
443 * Restore maskable interrupts to the state they were in
444 * when either disableEINT0() or enableEINT0() was called.
445 *
446 * Simply writes mask to the EINT0 register.
447 *
448 * @param(mask) bitmask of interrupts to restore
449 * @b(returns) previous EINT0 settings bitmask
450 */
451 @DirectCall
452 Bits32 restoreEINT0(Bits32 mask);
453
454 /*!
455 * ======== restoreEINT1 ========
456 * Restore maskable interrupts to the state they were in
457 * when either disableEINT1() or enableEINT1() was called.
458 *
459 * Simply writes mask to the EINT1 register.
460 *
461 * @param(mask) bitmask of interrupts to restore
462 * @b(returns) previous EINT1 settings bitmask
463 */
464 @DirectCall
465 Bits32 restoreEINT1(Bits32 mask);
466
467 /*!
468 * ======== setPriority ========
469 * Set an interrupt's relative priority.
470 *
471 * Priority 0-1 define the interrupt as an FIQ interrupt
472 * Priority 2-7 define the interrupt as an IRQ interrupt
473 *
474 * @param(intNum) ID of interrupt
475 * @param(priority) priority
476 */
477 @DirectCall
478 Void setPriority(UInt intNum, UInt priority);
479
480 instance:
481
482 /*! disableMask0. default is derived from MaskingOption_SELF maskSetting. */
483 config Bits32 disableMask0 = 0;
484
485 /*! disableMask1. default is derived from MaskingOption_SELF maskSetting. */
486 config Bits32 disableMask1 = 0;
487
488 /*! restoreMask0. default is derived from MaskingOption_SELF maskSetting. */
489 config Bits32 restoreMask0 = 0;
490
491 /*! restoreMask1. default is derived from MaskingOption_SELF maskSetting. */
492 config Bits32 restoreMask1 = 0;
493
494 /*!
495 * Interrupt priority (0-7). Default is 7 which is the
496 * lowest priority IRQ interrupt.
497 */
498 override config Int priority = 7;
499
500 /*!
501 * ======== reconfig ========
502 * Reconfigure a dispatched interrupt.
503 */
504 @DirectCall
505 Void reconfig(FuncPtr fxn, const Params *params);
506
507 internal:
508
509 510 511 512 513 514
515 config UInt (*swiDisable)();
516 config Void (*swiRestoreHwi)(UInt);
517 config UInt (*taskDisable)();
518 config Void (*taskRestoreHwi)(UInt);
519
520 521 522 523
524 Int postInit(Object *hwi, Error.Block *eb);
525
526 527 528
529 Void initIntController();
530
531 532 533 534 535
536 UInt interruptType(UInt intNum);
537
538
539 Void init();
540
541
542 Void dispatchIRQ();
543
544
545 Void dispatchIRQC(Irp irp);
546
547
548 Void dispatchFIQC();
549
550 /*!
551 * const array to hold all HookSet objects.
552 */
553 config HookSet hooks[length] = [];
554
555 /*! Meta World Only Hwi Configuration Object. */
556 metaonly struct InterruptObj {
557 Bool used;
558 Bool useDispatcher;
559 FuncPtr fxn;
560 };
561
562 /*!
563 * Meta-only array of interrupt objects.
564 * This meta-only array of Hwi config objects is initialized
565 * in Hwi.xs:module$meta$init().
566 */
567 metaonly config InterruptObj interrupt[NUM_INTERRUPTS];
568
569 metaonly config Bool assignResetVector = true;
570
571 struct Instance_State {
572 UInt priority;
573 Bits32 disableMask0;
574 Bits32 disableMask1;
575 Bits32 restoreMask0;
576 Bits32 restoreMask1;
577 UArg arg;
578 FuncPtr fxn;
579 Int intNum;
580 Irp irp;
581 Ptr hookEnv[];
582 };
583
584 struct Module_State {
585 Bits32 eint0Mask;
586 Bits32 eint1Mask;
587 UInt irp;
588 Char *taskSP;
589
590
591
592 Char *isrStack;
593 Ptr isrStackBase;
594 Ptr isrStackSize;
595 Char fiqStack[];
596 SizeT fiqStackSize;
597
598 Handle dispatchTable[NUM_INTERRUPTS];
599
600 };
601 }
602