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36
37 package ti.sysbios.family.arm.arm9;
38
39 /*!
40 * ======== Cache ========
41 * ARM Cache Module
42 *
43 * This module manages the data and instruction caches on ARM processors.
44 * It provides a list of functions that perform cache operations. The
45 * functions operate on a per cache line except for the 'All' functions
46 * which operate on the entire cache specified. Any Address that is not
47 * aligned to a cache line gets rounded down to the address of
48 * the nearest cache line.
49 *
50 * The L1 data and program caches are enabled
51 * by default early during the startup sequence (prior to any Module_startup()s).
52 * Data caching requires the MMU to be enabled and the cacheable
53 * attribute of the section/page descriptor for a corresponding
54 * memory region to be enabled.
55 * Program caching does not require the MMU to be enabled and therefore
56 * occurs when the L1 program cache is enabled.
57 *
58 * Note: See the {@link ti.sysbios.family.arm.arm9.Mmu} module for
59 * information about the MMU.
60 *
61 * Unconstrained Functions
62 * All functions
63 *
64 * @p(html)
65 * <h3> Calling Context </h3>
66 * <table border="1" cellpadding="3">
67 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
68 *
69 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
70 * <!-- -->
71 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
72 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
73 * <tr><td> {@link #inv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
74 * <tr><td> {@link #invL1dAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
75 * <tr><td> {@link #invL1pAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
76 * <tr><td> {@link #wait} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
77 * <tr><td> {@link #wb} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
78 * <tr><td> {@link #wbInv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
79 * <tr><td> {@link #wbInvL1dAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
80 * <tr><td> {@link #wbL1dAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
81 * <tr><td colspan="6"> Definitions: <br />
82 * <ul>
83 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
84 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
85 * <li> <b>Task</b>: API is callable from a Task thread. </li>
86 * <li> <b>Main</b>: API is callable during any of these phases: </li>
87 * <ul>
88 * <li> In your module startup after this module is started (e.g. Cache_Module_startupDone() returns TRUE). </li>
89 * <li> During xdc.runtime.Startup.lastFxns. </li>
90 * <li> During main().</li>
91 * <li> During BIOS.startupFxns.</li>
92 * </ul>
93 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
94 * <ul>
95 * <li> During xdc.runtime.Startup.firstFxns.</li>
96 * <li> In your module startup before this module is started (e.g. Cache_Module_startupDone() returns FALSE).</li>
97 * </ul>
98 * </ul>
99 * </td></tr>
100 *
101 * </table>
102 * @p
103 */
104
105 module Cache inherits ti.sysbios.interfaces.ICache
106 {
107 /*!
108 * Size of L1 data cache Line
109 */
110 const UInt sizeL1dCacheLine = 32;
111
112 /*!
113 * Size of L1 program cache Line
114 */
115 const UInt sizeL1pCacheLine = 32;
116
117 /*!
118 * Enable L1 data and program caches.
119 *
120 * To enable a subset of the caches, set this parameter
121 * to 'false' and call Cache_enable() within main, passing it only
122 * the {@link Cache#Type Cache_Type(s)} to be enabled.
123 *
124 * Data caching requires the MMU and the memory section/page
125 * descriptor cacheable attribute to be enabled.
126 */
127 config Bool enableCache = true;
128
129 /*! @_nodoc
130 * ======== getEnabled ========
131 * Get the 'type' bitmask of cache(s) enabled.
132 */
133 @DirectCall
134 Bits16 getEnabled();
135
136 /*!
137 * ======== invL1dAll ========
138 * Invalidate all of L1 data cache.
139 *
140 * This function should be used with caution. In general, the
141 * L1 data cache may contain some stack variable or valid data
142 * that should not be invalidated. This function should be used
143 * only when all contents of L1 data cache is unwanted.
144 */
145 @DirectCall
146 Void invL1dAll();
147
148 /*!
149 * ======== invL1pAll ========
150 * Invalidate all of L1 program cache.
151 */
152 @DirectCall
153 Void invL1pAll();
154
155
156 internal:
157
158 /*!
159 * ======== startup ========
160 * startup function to enable cache early during climb-up
161 */
162 Void startup();
163
164 /*!
165 * ======== disableL1d ========
166 * Disable L1 data cache
167 *
168 * This function performs a write back invalidate all of
169 * L1 data cache before it disables the cache.
170 */
171 Void disableL1d();
172
173 /*!
174 * ======== disableL1p ========
175 * Disable L1 Program cache
176 *
177 * This function performs an invalidate all of L1 program cache
178 * before it disables the cache.
179 */
180 Void disableL1p();
181
182 /*!
183 * ======== enableL1d ========
184 * Enable L1 data cache.
185 */
186 Void enableL1d();
187
188 /*!
189 * ======== enableL1p ========
190 * Enable L1 program cache.
191 */
192 Void enableL1p();
193
194 /*!
195 * ======== invL1d ========
196 * Invalidates range in L1 data cache.
197 */
198 Void invL1d(Ptr blockPtr, SizeT byteCnt, Bool wait);
199
200 /*!
201 * ======== invL1p ========
202 * Invalidates range in L1 program cache.
203 */
204 Void invL1p(Ptr blockPtr, SizeT byteCnt, Bool wait);
205
206 }