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32 33 34 35
36 package ti.sysbios.family.arm.a8.intcps;
37
38 import xdc.rov.ViewInfo;
39
40 import xdc.runtime.Diags;
41 import xdc.runtime.Log;
42 import xdc.runtime.Error;
43
44 import ti.sysbios.BIOS;
45 import ti.sysbios.interfaces.IHwi;
46
47 /*!
48 * ======== Hwi ========
49 * Hardware Interrupt Support Module.
50 *
51 * This Hwi module provides ARM family-specific implementations of the
52 * APIs defined in {@link ti.sysbios.interfaces.IHwi IHwi}.
53 *
54 * Additional ARM device-specific APIs are also provided.
55 *
56 * @a(NOTE)
57 * In this Hwi module implementation, the instance config parameter value
58 * {@link #MaskingOption_LOWER} is equivalent to {@link #MaskingOption_SELF}.
59 * Statically configuring a Hwi object's {@link #Params.maskSetting} to
60 * {@link #MaskingOption_LOWER} will result in the generation of a benign
61 * build warning. Dynamic usages of {@link #MaskingOption_LOWER} will be
62 * silently converted to {@link #MaskingOption_SELF}.
63 *
64 */
65
66 @Template("./Hwi.xdt")
67 @ModuleStartup
68
69 module Hwi inherits ti.sysbios.interfaces.IHwi
70 {
71
72
73
74 /*! intcps supports 128 interrupts. */
75 const Int NUM_INTERRUPTS = 128;
76
77 /*!
78 * The device-specific number of priorities supported.
79 *
80 * The actual number supported is device specific and provided by
81 * the catalog device specification.
82 */
83 config Int NUM_PRIORITIES;
84
85
86
87 /*! Hwi vector function type definition. */
88 typedef Void (*VectorFuncPtr)(void);
89
90 /*!
91 * ======== BasicView ========
92 * @_nodoc
93 */
94 metaonly struct BasicView {
95 Ptr halHwiHandle;
96 String label;
97 Int intNum;
98 UInt priority;
99 String fxn;
100 UArg arg;
101 };
102
103 /*!
104 * ======== DetailedView ========
105 * @_nodoc
106 */
107 metaonly struct DetailedView {
108 Ptr halHwiHandle;
109 String label;
110 Int intNum;
111 UInt priority;
112 String fxn;
113 UArg arg;
114 Ptr irp;
115 Bool enabled;
116 Bool pending;
117 };
118
119 /*!
120 * ======== ModuleView ========
121 * @_nodoc
122 */
123 metaonly struct ModuleView {
124 String options[4];
125 UInt spuriousInterrupts;
126 UInt lastSpuriousInterrupt;
127 SizeT hwiStackPeak;
128 SizeT hwiStackSize;
129 Ptr hwiStackBase;
130 };
131
132 /*!
133 * ======== rovViewInfo ========
134 * @_nodoc
135 */
136 @Facet
137 metaonly config ViewInfo.Instance rovViewInfo =
138 ViewInfo.create({
139 viewMap: [
140 ['Basic', {type: ViewInfo.INSTANCE, viewInitFxn: 'viewInitBasic', structName: 'BasicView'}],
141 ['Detailed', {type: ViewInfo.INSTANCE, viewInitFxn: 'viewInitDetailed', structName: 'DetailedView'}],
142 ['Module', {type: ViewInfo.MODULE, viewInitFxn: 'viewInitModule', structName: 'ModuleView'}]
143 ]
144 });
145
146 /*! Interrupt type. IRQ or FIQ */
147 enum Type {
148 Type_IRQ, /*! IRQ interrupt. */
149 Type_FIQ /*! FIQ interrupt. */
150 };
151
152 /*! Interrupt Controller. Symbol "Hwi_intc" is physical device */
153 struct Intc {
154 UInt32 REVISION; /*! 0x00 Config Register */
155
156 UInt32 hole0[3]; /*! 0x04-0x0C */
157
158 UInt32 SYSCONFIG; /*! 0x10 Config Register */
159 UInt32 SYSSTATUS; /*! 0x14 Status Register */
160
161 UInt32 hole1[10]; /*! 0x18-0x3c */
162
163 UInt32 SIR_IRQ; /*! 0x40 Source IRQ Register */
164 UInt32 SIR_FIQ; /*! 0x44 Source FIQ Register */
165 UInt32 CONTROL; /*! 0x48 Control Register */
166 UInt32 PROTECTION; /*! 0x4C Protection Register */
167 UInt32 IDLE; /*! 0x50 Idle Register */
168
169 UInt32 hole2[3]; /*! 0x54-0x5C */
170
171 UInt32 IRQ_PRIORITY; /*! 0x60 IRQ Priority Register */
172 UInt32 FIQ_PRIORITY; /*! 0x64 IRQ Priority Register */
173 UInt32 THRESHOLD; /*! 0x68 Threshold Register */
174
175 UInt32 hole3[5]; /*! 0x6C-0x7C */
176
177 UInt32 ITR0; /*! 0x80 Interrupt Input Register */
178 UInt32 MIR0; /*! 0x84 Mask Interrupt Register */
179 UInt32 MIR_CLEAR0; /*! 0x88 MIR Clear Register */
180 UInt32 MIR_SET0; /*! 0x8C MIR Set Register */
181 UInt32 ISR_SET0; /*! 0x90 Interrupt Set Register */
182 UInt32 ISR_CLEAR0; /*! 0x94 Interrupt Clear Register */
183 UInt32 PENDING_IRQ0; /*! 0x98 Pending IRQ Register */
184 UInt32 PENDING_FIQ0; /*! 0x9C Pending FIQ Register */
185
186 UInt32 ITR1; /*! 0xA0 Interrupt Input Register */
187 UInt32 MIR1; /*! 0xA4 Mask Interrupt Register */
188 UInt32 MIR_CLEAR1; /*! 0xA8 MIR Clear Register */
189 UInt32 MIR_SET1; /*! 0xAC MIR Set Register */
190 UInt32 ISR_SET1; /*! 0xB0 Interrupt Set Register */
191 UInt32 ISR_CLEAR1; /*! 0xB4 Interrupt Clear Register */
192 UInt32 PENDING_IRQ1; /*! 0xB8 Pending IRQ Register */
193 UInt32 PENDING_FIQ1; /*! 0xBC Pending FIQ Register */
194
195 UInt32 ITR2; /*! 0xC0 Interrupt Input Register */
196 UInt32 MIR2; /*! 0xC4 Mask Interrupt Register */
197 UInt32 MIR_CLEAR2; /*! 0xC8 MIR Clear Register */
198 UInt32 MIR_SET2; /*! 0xCC MIR Set Register */
199 UInt32 ISR_SET2; /*! 0xD0 Interrupt Set Register */
200 UInt32 ISR_CLEAR2; /*! 0xD4 Interrupt Clear Register */
201 UInt32 PENDING_IRQ2; /*! 0xD8 Pending IRQ Register */
202 UInt32 PENDING_FIQ2; /*! 0xDC Pending FIQ Register */
203
204 UInt32 ITR3; /*! 0xE0 Interrupt Input Register */
205 UInt32 MIR3; /*! 0xE4 Mask Interrupt Register */
206 UInt32 MIR_CLEAR3; /*! 0xE8 MIR Clear Register */
207 UInt32 MIR_SET3; /*! 0xEC MIR Set Register */
208 UInt32 ISR_SET3; /*! 0xF0 Interrupt Set Register */
209 UInt32 ISR_CLEAR3; /*! 0xF4 Interrupt Clear Register */
210 UInt32 PENDING_IRQ3; /*! 0xF8 Pending IRQ Register */
211 UInt32 PENDING_FIQ3; /*! 0xFC Pending FIQ Register */
212
213 UInt32 ILR[128]; /*! 0x100 thru 0x2FC */
214 };
215
216 extern volatile Intc intc;
217
218
219
220 /*! Reset Handler. Default is c_int00 */
221 metaonly config VectorFuncPtr resetFunc;
222
223 /*!
224 * Undefined instruction exception handler.
225 * Default is an internal exception handler.
226 */
227 metaonly config VectorFuncPtr undefinedInstFunc;
228
229 /*!
230 * SWI Handler. Default is internal SWI handler.
231 * Default is an internal exception handler.
232 */
233 metaonly config VectorFuncPtr swiFunc;
234
235 /*!
236 * Prefetch abort exception handler.
237 * Default is an internal exception handler.
238 */
239 metaonly config VectorFuncPtr prefetchAbortFunc;
240
241 /*!
242 * Data abort exception handler.
243 * Default is an internal exception handler.
244 */
245 metaonly config VectorFuncPtr dataAbortFunc;
246
247 /*!
248 * Reserved exception handler.
249 * Default is an internal exception handler.
250 */
251 metaonly config VectorFuncPtr reservedFunc;
252
253 /*! IRQ interrupt handler. Default is internal IRQ dispatcher */
254 metaonly config VectorFuncPtr irqFunc;
255
256 /*! FIQ interrupt handler. Default is internal FIQ dispatcher */
257 metaonly config VectorFuncPtr fiqFunc;
258
259 /*!
260 * FIQ stack pointer. Default = null.
261 * (Indicates that stack is to be created internally)
262 */
263 config Ptr fiqStack = null;
264
265 /*!
266 * FIQ stack size in MAUs.
267 * Default is 1024 bytes.
268 */
269 metaonly config SizeT fiqStackSize = 1024;
270
271 /*!
272 * Memory section used for FIQ stack
273 * Default is null.
274 */
275 metaonly config String fiqStackSection = null;
276
277 /*! Initial MIR0 Interrupt Mask. Default is 0xffffffff */
278 config Bits32 mir0Mask = 0xffffffff;
279
280 /*! Initial MIR1 Interrupt Mask. Default is 0xffffffff */
281 config Bits32 mir1Mask = 0xffffffff;
282
283 /*! Initial MIR2 Interrupt Mask. Default is 0xffffffff */
284 config Bits32 mir2Mask = 0xffffffff;
285
286 /*! Initial MIR3 Interrupt Mask. Default is 0xffffffff */
287 config Bits32 mir3Mask = 0xffffffff;
288
289 /*!
290 * Error raised when an attempt is made to create a Hwi
291 * that has already been created.
292 */
293 config Error.Id E_alreadyDefined = {
294 msg: "E_alreadyDefined: Hwi already defined, intnum: %d"
295 };
296
297 /*!
298 * Error raised when Hwi handle referenced in Hwi_delete()
299 * is not found in the Hwi dispatch table
300 */
301 config Error.Id E_handleNotFound = {
302 msg: "E_handleNotFound: Hwi handle not found: 0x%x"
303 };
304
305 /*!
306 * Error raised when an undefined interrupt has fired.
307 */
308 config Error.Id E_undefined = {
309 msg: "E_undefined: Hwi undefined, intnum: %d"
310 };
311
312 /*!
313 * Error raised if an attempt is made to create a Hwi
314 * with an interrupt number greater than NUM_INTERRUPTS - 1.
315 */
316 config Error.Id E_badIntNum = {
317 msg: "E_badIntNum, intnum: %d is out of range"
318 };
319
320 /*!
321 * Issued just prior to Hwi function invocation (with interrupts disabled)
322 */
323 config Log.Event LM_begin = {
324 mask: Diags.USER1 | Diags.USER2,
325 msg: "LM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x"
326 };
327
328 /*!
329 * Issued just after return from Hwi function (with interrupts disabled)
330 */
331 config Log.Event LD_end = {
332 mask: Diags.USER2,
333 msg: "LD_end: hwi: 0x%x"
334 };
335
336
337
338
339 /*!
340 * ======== disable ========
341 */
342 @Macro
343 override UInt disable();
344
345 /*!
346 * ======== enable ========
347 */
348 @Macro
349 override UInt enable();
350
351 /*!
352 * ======== restore ========
353 */
354 @Macro
355 override Void restore(UInt key);
356
357 /*!
358 * ======== inUseMeta ========
359 * @_nodoc
360 * Check for Hwi already in use.
361 * For internal SYS/BIOS use only.
362 * Should be called prior to any internal Hwi.create().
363 *
364 * @param(intNum) interrupt number
365 */
366 metaonly Bool inUseMeta(UInt intNum);
367
368 /*!
369 * ======== getHandle ========
370 * Returns Hwi_Handle associated with intNum
371 *
372 * @param(intNum) interrupt number
373 */
374 @DirectCall
375 Handle getHandle(UInt intNum);
376
377 /*!
378 * ======== enableFIQ ========
379 * Enable FIQ interrupts.
380 *
381 * @b(returns) previous FIQ interrupt enable/disable state
382 */
383 @DirectCall
384 UInt enableFIQ();
385
386 /*!
387 * ======== disableFIQ ========
388 * Disable FIQ interrupts.
389 *
390 * @b(returns) previous FIQ interrupt enable/disable state
391 */
392 @DirectCall
393 UInt disableFIQ();
394
395 /*!
396 * ======== restoreFIQ ========
397 * Restore FIQ interrupts.
398 *
399 * @param(key) enable/disable state to restore
400 */
401 @DirectCall
402 Void restoreFIQ(UInt key);
403
404 /*!
405 * ======== enableIRQ ========
406 * Enable IRQ interrupts.
407 *
408 * @param(key) enable/disable state to restore
409 */
410 @DirectCall
411 UInt enableIRQ();
412
413 /*!
414 * ======== disableIRQ ========
415 * Disable IRQ interrupts.
416 *
417 * @b(returns) previous IRQ interrupt enable/disable state
418 */
419 @DirectCall
420 UInt disableIRQ();
421
422 /*!
423 * ======== restoreIRQ ========
424 * Restore IRQ interrupts.
425 *
426 * @param(key) enable/disable state to restore
427 */
428 @DirectCall
429 Void restoreIRQ(UInt key);
430
431 /*!
432 * ======== disableMIR0 ========
433 * Disable specific interrupts.
434 *
435 * Disables specific interrupts by setting the bits specified by
436 * mask in the Mask Interrupts Register (MIR).
437 *
438 * @param(mask) bitmask of interrupts to disable
439 * @b(returns) previous MIR0 settings bitmask
440 */
441 @DirectCall
442 Bits32 disableMIR0(Bits32 mask);
443 @DirectCall
444 Bits32 disableMIR1(Bits32 mask);
445 @DirectCall
446 Bits32 disableMIR2(Bits32 mask);
447 @DirectCall
448 Bits32 disableMIR3(Bits32 mask);
449
450 /*!
451 * ======== enableMIR ========
452 * Enable specific interrupts.
453 *
454 * Enables specific interrupts by clearing the bits specified by
455 * mask in the Mask Interrupts Register (MIR).
456 *
457 * @param(mask) bitmask of interrupts to enable
458 * @b(returns) previous MIR settings bitmask
459 */
460 @DirectCall
461 Bits32 enableMIR0(Bits32 mask);
462 @DirectCall
463 Bits32 enableMIR1(Bits32 mask);
464 @DirectCall
465 Bits32 enableMIR2(Bits32 mask);
466 @DirectCall
467 Bits32 enableMIR3(Bits32 mask);
468
469 /*!
470 * ======== restoreMIR0 ========
471 * Restore maskable interrupts to the state they were in
472 * when either disableMIR0() or enableMIR0() was called.
473 *
474 * Simply writes mask to the MIR register.
475 *
476 * @param(mask) bitmask of interrupts to restore
477 * @b(returns) previous MIR0 settings bitmask
478 */
479 @DirectCall
480 Bits32 restoreMIR0(Bits32 mask);
481 @DirectCall
482 Bits32 restoreMIR1(Bits32 mask);
483 @DirectCall
484 Bits32 restoreMIR2(Bits32 mask);
485 @DirectCall
486 Bits32 restoreMIR3(Bits32 mask);
487
488 /*!
489 * ======== setPriority ========
490 * Set an interrupt's priority.
491 *
492 * Valid priority values range from 0 to
493 * ({@link #NUM_PRIORITIES} - 1),
494 * 0 is the highest priority.
495 *
496 * @param(intNum) ID of interrupt
497 * @param(priority) priority
498 */
499 @DirectCall
500 Void setPriority(UInt intNum, UInt priority);
501
502 /*!
503 * ======== setType ========
504 * Set an interrupt's type (FIQ/IRQ).
505 *
506 * @param(intNum) ID of interrupt
507 * @param(type) type = FIQ/IRQ
508 */
509 @DirectCall
510 Void setType(UInt intNum, Type type);
511
512 instance:
513
514 /*! Interrupt type (IRQ/FIQ). Default is IRQ. */
515 config Type type = Type_IRQ;
516
517 518 519 520 521 522 523 524 525 526 527
528 override config Int priority = -1;
529
530 /*!
531 * The maskSetting parameter is ignored.
532 * Only Hwi_MaskingOption_LOWER is supported.
533 *
534 * The interrupt controller is designed for priority based interrupts
535 */
536 override config IHwi.MaskingOption maskSetting = IHwi.MaskingOption_LOWER;
537
538 /*!
539 * ======== reconfig ========
540 * Reconfigure a dispatched interrupt.
541 */
542 @DirectCall
543 Void reconfig(FuncPtr fxn, const Params *params);
544
545 internal:
546
547 548 549 550 551 552
553 config UInt (*swiDisable)();
554 config Void (*swiRestoreHwi)(UInt);
555 config UInt (*taskDisable)();
556 config Void (*taskRestoreHwi)(UInt);
557
558 559 560 561
562 Int postInit(Object *hwi, Error.Block *eb);
563
564 565 566
567 Void initIntController();
568
569
570 Void init(Ptr fiqStack);
571
572
573 Void initVbar();
574
575
576 Void dispatchIRQ();
577
578
579 Void dispatchIRQC(Irp irp);
580
581
582 Void dispatchFIQC();
583
584
585 Void nonPluggedHwiHandler(UArg arg);
586
587 /*!
588 * const array to hold all HookSet objects.
589 */
590 config HookSet hooks[length] = [];
591
592 /*! Meta World Only Hwi Configuration Object. */
593 metaonly struct InterruptObj {
594 Bool used;
595 FuncPtr fxn;
596 };
597
598 /*!
599 * Meta-only array of interrupt objects.
600 * This meta-only array of Hwi config objects is initialized
601 * in Hwi.xs:module$meta$init().
602 */
603 metaonly config InterruptObj interrupt[NUM_INTERRUPTS];
604
605 struct Instance_State {
606 Type type;
607 UInt priority;
608 UArg arg;
609 FuncPtr fxn;
610 Irp irp;
611 Ptr hookEnv[];
612 };
613
614 struct Module_State {
615 Bits32 mir0Mask;
616 Bits32 mir1Mask;
617 Bits32 mir2Mask;
618 Bits32 mir3Mask;
619 UInt spuriousInts;
620 UInt lastSpuriousInt;
621 UInt irp;
622 Char *taskSP;
623
624
625 Char *isrStack;
626 Ptr isrStackBase;
627 Ptr isrStackSize;
628 Char fiqStack[];
629 SizeT fiqStackSize;
630 Hwi.Object nonPluggedHwi;
631 Handle dispatchTable[NUM_INTERRUPTS];
632
633 };
634 }
635