| Benchmark | Cycles | (1) |
| Interrupt latency | 95 | (2) |
| Hwi_enable | 1 | |
| Hwi_disable | 3 | |
| Hwi dispatcher prolog | 92 | |
| Hwi dispatcher epilog | 189 | |
| Hwi dispatcher | 274 | |
| Hardware Interrupt to Blocked Task | 492 | |
| Hardware Interrupt to Software Interrupt | 332 | |
| Swi_enable | 44 | |
| Swi_disable | 10 | |
| Post Software Interrupt Again | 33 | |
| Post Software Interrupt without Context Switch | 106 | |
| Post Software Interrupt with Context Switch | 202 | |
| Create a New Task without Context Switch | 1692 | |
| Set a Task Priority without a Context Switch | 191 | |
| Task_yield | 191 | |
| Post Semaphore, No Waiting Task | 54 | |
| Post Semaphore No Task Switch | 196 | |
| Post Semaphore with Task Switch | 264 | |
| Pend on Semaphore, No Context Switchi | 55 | |
| Pend on Semaphore with Task Switch | 282 | |
| Clock_getTicks | 8 |
(1) The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: "-mcpu=cortex-m3 -mthumb -mabi=aapcs -mapcs -mcpu=cortex-m3 -mthumb -mabi=aapcs -mapcs-frame -ffunction-sections -fdata-sections -O3 -combine".
Timings were obtained using the Stellaris Blizzard LM4FSXLH5BB board running at 40MHz.
(2) The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.