| Benchmark | Cycles | (1) |
| Interrupt latency | 728 | |
| Hwi_enable | 12 | |
| Hwi_disable | 25 | |
| Hwi dispatcher prolog | 676 | |
| Hwi dispatcher epilog | 440 | |
| Hwi dispatcher | 801 | |
| Hardware Interrupt to Blocked Task | 1133 | |
| Hardware Interrupt to Software Interrupt | 879 | |
| Swi_enable | 210 | |
| Swi_disable | 30 | |
| Post Software [CortxA8] Interrupt Again | 93 | |
| Post Software Interrupt without Context Switch | 206 | |
| Post Software Interrupt with Context Switch | 246 | |
| Create a New Task without Context Switch | 2058 | |
| Set a Task Priority without a Context Switch | 286 | |
| Task_yield | 385 | |
| Post Semaphore, No Wai[CortxA8] ting Task | 102 | |
| Post Semaphore No Task Switch | 331 | |
| Post Semaphore with Task Switch | 415 | |
| Pend on Semaphore, No Context Switchi | 121 | |
| Pend on Semaphore with Task Switch | 366 | |
| Clock_getTicks | 18 | |
(1) The benchmark application was built using BIOS.LibType_Custom with the following compiler options: "--endian=little -mv7A8 --abi=eabi --neon --float_support=vfpv3 -q -ms --opt_for_speed=2 --program_level_compile -o3".
Timings were obtained using the evmAM3359 development board.
The A8 core was running at 550MHz, with L1 & L2 caches enabled, and all code & data placed in OCMC0.
Furthermore, the first 64K bytes of OCMC0 memory are pulled in and locked into the L2 cache at startup to maximize cache performance.
Unlike other target benchmarks that are collected using flat memory simulators or hardware with zero wait-state memory and no cache, these A8Fnv numbers are collected on a real board with cache enabled. These numbers are effected by varying amounts of cache filling depending on the dynamics of the cache and the previous function calls.