1    /* 
     2     * Copyright (c) 2011, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     * */
    32    /*
    33     *  ======== Cache.xdc ========
    34     *
    35     *
    36     */
    37    
    38    package ti.sysbios.family.c64p;
    39    
    40    import xdc.rov.ViewInfo;
    41    
    42    /*!
    43     *  ======== Cache ========
    44     *  Cache Module
    45     *
    46     *  This Cache module provides C64+ family-specific implementations of the
    47     *  APIs defined in {@link ti.sysbios.interfaces.ICache ICache}.  It also
    48     *  provides additional C64+ specific cache functions.
    49     *
    50     *  Unconstrained Functions
    51     *  All functions
    52     *
    53     *  @p(html)
    54     *  <h3> Calling Context </h3>
    55     *  <table border="1" cellpadding="3">
    56     *    <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
    57     *
    58     *    <tr><th> Function                 </th><th>  Hwi   </th><th>  Swi   </th><th>  Task  </th><th>  Main  </th><th>  Startup  </th></tr>
    59     *    <!--                                                                                                                 -->
    60     *    <tr><td> {@link #disable}    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    61     *    <tr><td> {@link #enable}     </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    62     *    <tr><td> {@link #getMar*}    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    63     *    <tr><td> {@link #getMode*}   </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    64     *    <tr><td> {@link #getSize*}   </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    65     *    <tr><td> {@link #inv}        </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    66     *    <tr><td> {@link #invL1pAll*} </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    67     *    <tr><td> {@link #setMar*}    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    68     *    <tr><td> {@link #setMode*}   </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    69     *    <tr><td> {@link #setSize*}   </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    70     *    <tr><td> {@link #wait}       </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    71     *    <tr><td> {@link #wb}         </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    72     *    <tr><td> {@link #wbAll*}     </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    73     *    <tr><td> {@link #wbInv}      </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    74     *    <tr><td> {@link #wbInvAll}   </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td></tr>
    75     *    <tr><td colspan="6"> Definitions: <br />
    76     *       <ul>
    77     *         <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
    78     *         <li> <b>Swi</b>: API is callable from a Swi thread. </li>
    79     *         <li> <b>Task</b>: API is callable from a Task thread. </li>
    80     *         <li> <b>Main</b>: API is callable during any of these phases: </li>
    81     *           <ul>
    82     *             <li> In your module startup after this module is started (e.g. Mod_Module_startupDone() returns TRUE). </li>
    83     *             <li> During xdc.runtime.Startup.lastFxns. </li>
    84     *             <li> During main().</li>
    85     *             <li> During BIOS.startupFxns.</li>
    86     *           </ul>
    87     *         <li> <b>Startup</b>: API is callable during any of these phases:</li>
    88     *           <ul>
    89     *             <li> During xdc.runtime.Startup.firstFxns.</li>
    90     *             <li> In your module startup before this module is started (e.g. Mod_Module_startupDone() returns FALSE).</li>
    91     *           </ul>
    92     *       <li> <b>*</b>: These APIs are intended to be made at initialization time, but are not restricted to this. </li>
    93     *       </ul>
    94     *    </td></tr>
    95     *
    96     *  </table>
    97     *  @p
    98     */
    99    
   100    @ModuleStartup
   101    
   102    module Cache inherits ti.sysbios.interfaces.ICache
   103    {
   104        // -------- Module Types --------
   105    
   106        metaonly struct ModuleView {
   107            String  L1PCacheSize;
   108            String  L1PMode;
   109            String  L1DCacheSize;
   110            String  L1DMode;
   111            String  L2CacheSize;
   112            String  L2Mode;
   113        };
   114        
   115        metaonly struct MarRegisterView {
   116            UInt    number;
   117            Ptr     addr;
   118            Ptr     startAddrRange;
   119            Ptr     endAddrRange;
   120        };
   121    
   122        @Facet
   123        metaonly config ViewInfo.Instance rovViewInfo = 
   124            ViewInfo.create({
   125                viewMap: [
   126                    ['Module',
   127                        {
   128                            type: ViewInfo.MODULE,
   129                            viewInitFxn: 'viewInitModule',
   130                            structName: 'ModuleView'
   131                        }
   132                    ],
   133                    ['EnableMARs',
   134                        {
   135                            type: xdc.rov.ViewInfo.MODULE_DATA,
   136                            viewInitFxn: 'viewInitMarRegisters',
   137                            structName: 'MarRegisterView'
   138                        }
   139                    ]
   140                ]
   141            });
   142            
   143        /*! Lists of cache modes for L1/L2 caches */
   144        enum Mode {
   145            Mode_FREEZE,    /*! No new cache lines are allocated */
   146            Mode_BYPASS,    /*! All access result in long-distance access */
   147            Mode_NORMAL     /*! Normal operation of cache */
   148        };
   149    
   150        /*! Level 1 cache size type definition. Can be used for both L1D & L1P */
   151        enum L1Size {
   152            L1Size_0K = 0,  /*! Amount of cache is 0K, Amount of SRAM is 32K */
   153            L1Size_4K = 1,  /*! Amount of cache is 4K, Amount of SRAM is 28K */
   154            L1Size_8K = 2,  /*! Amount of cache is 8K, Amount of SRAM is 24K */
   155            L1Size_16K = 3, /*! Amount of cache is 16K, Amount of SRAM is 16K */
   156            L1Size_32K = 4  /*! Amount of cache is 32K, Amount of SRAM is 0K */
   157        };
   158    
   159        /*! Level 2 cache size type definition. */
   160        enum L2Size {
   161            L2Size_0K = 0,   /*! L2 is all SRAM */
   162            L2Size_32K = 1,  /*! Amount of cache is 32K */
   163            L2Size_64K = 2,  /*! Amount of cache is 64K */
   164            L2Size_128K = 3, /*! Amount of cache is 128K */
   165            L2Size_256K = 4, /*! Amount of cache is 256K */
   166            L2Size_512K = 5, /*! Amount of cache is 512K */
   167            L2Size_1024K = 6 /*! Amount of cache is 1024K */
   168        };
   169    
   170        /*! MAR register setting type definition. */
   171        enum Mar {
   172            Mar_DISABLE = 0, /*! The Permit Copy bit of MAR register is disabled */
   173            Mar_ENABLE = 1   /*! The Permit Copy bit of MAR register is enabled */
   174        };
   175    
   176        /*! Structure for specifying all cache sizes. */
   177        struct Size {
   178            L1Size l1pSize;         /*! L1 Program cache size */
   179            L1Size l1dSize;         /*! L1 Data data size */
   180            L2Size l2Size;          /*! L2 cache size */
   181        };
   182    
   183        /*! 
   184         * Cache sizes.
   185         *
   186         * When this parameter is set in user's cfg script, user set cache sizes
   187         * override those specified by the Cache module or the platform.
   188         */
   189        config Size initSize = {
   190            l1pSize: L1Size_32K,
   191            l1dSize: L1Size_32K,
   192            l2Size: L2Size_0K
   193        };
   194    
   195        /*! 
   196         *  MAR 00 - 31 register bitmask. (for addresses 0x00000000 - 0x1FFFFFFF)
   197         *
   198         *  If undefined by the user, this parameter is configured to match the 
   199         *  memory map of the platform.
   200         *  Each memory region defined in the platform will have all of its 
   201         *  corresponding MAR bits set.
   202         *
   203         *  To override the default behavior you must initialize this parameter
   204         *  in your configuration script:
   205         *
   206         *  @p(code)
   207         *  // disable MAR bits for addresses 0x00000000 to 0x1FFFFFFF
   208         *  Cache.MAR0_31 = 0x00000000;
   209         *  @p
   210         */
   211        config UInt32 MAR0_31;
   212    
   213        /*! 
   214         *  MAR 32 - 63 register bitmask (for addresses 0x20000000 - 0x3FFFFFFF)
   215         *
   216         *  see {@link #MAR0_31} for more info
   217         */
   218        config UInt32 MAR32_63;
   219    
   220        /*! 
   221         *  MAR 64 - 95 register bitmask (for addresses 0x40000000 - 0x5FFFFFFF)
   222         *
   223         *  see {@link #MAR0_31} for more info
   224         */
   225        config UInt32 MAR64_95;
   226    
   227        /*! 
   228         *  MAR 96 - 127 register bitmask (for addresses 0x60000000 - 0x7FFFFFFF)
   229         *
   230         *  see {@link #MAR0_31} for more info
   231         */
   232        config UInt32 MAR96_127;
   233    
   234        /*! 
   235         *  MAR 128 - 159 register bitmask (for addresses 0x80000000 - 0x9FFFFFFF)
   236         *
   237         *  see {@link #MAR0_31} for more info
   238         */
   239        config UInt32 MAR128_159;
   240    
   241        /*! 
   242         *  MAR 160 - 191 register bitmask (for addresses 0xA0000000 - 0xBFFFFFFF)
   243         *
   244         *  see {@link #MAR0_31} for more info
   245         */
   246        config UInt32 MAR160_191;
   247    
   248        /*! 
   249         *  MAR 192 - 223 register bitmask (for addresses 0xC0000000 - 0xDFFFFFFF)
   250         *
   251         *  see {@link #MAR0_31} for more info
   252         */
   253        config UInt32 MAR192_223;
   254    
   255        /*! 
   256         *  MAR 224 - 255 register bitmask (for addresses 0xE0000000 - 0xFFFFFFFF)
   257         *
   258         *  see {@link #MAR0_31} for more info
   259         */
   260        config UInt32 MAR224_255;
   261    
   262        /*!
   263         *  ======== disable ========
   264         *  Disables the 'type' cache(s)
   265         *
   266         *  Disabling of L2 cache is currently not supported.
   267         */
   268        @DirectCall
   269        override Void disable(Bits16 type);
   270    
   271        /*!
   272         *  ======== setMode ========
   273         *  Set mode of a cache
   274         *
   275         *  @param(type)    bit mask of cache type
   276         *  @param(mode)    mode of cache
   277         *
   278         *  @b(returns)     previous mode of cache
   279         */
   280        @DirectCall
   281        Mode setMode(Bits16 type, Mode mode);
   282    
   283        /*!
   284         *  ======== getMode ========
   285         *  Get mode of a cache
   286         *
   287         *  @param(type)     bit mask of cache type
   288         *  @b(returns)      mode of specified level of cache
   289         */
   290        @DirectCall
   291        Mode getMode(Bits16 type);
   292    
   293        /*!
   294         *  ======== setSize ========
   295         *  Set sizes of all caches
   296         *
   297         *  @param(size)    pointer to structure of type Cache_Size
   298         */
   299        @DirectCall
   300        Void setSize(Size *size);
   301    
   302        /*!
   303         *  ======== getSize ========
   304         *  Get sizes of all caches
   305         *
   306         *  @param(size)    pointer to structure of type Cache_Size
   307         */
   308        @DirectCall
   309        Void getSize(Size *size);
   310    
   311        /*!
   312         *  ======== getMar ========
   313         *  Get the value of the MAR register defined for the specified
   314         *  base address
   315         *
   316         *  @param(baseAddr)        address for which MAR is requested
   317         *
   318         *  @b(returns)     value of MAR register associated with  specified address
   319         */
   320        @DirectCall
   321        Mar getMar(Ptr baseAddr);
   322    
   323        /*!
   324         *  ======== setMar ========
   325         *  Set the MAR register(s) that corresponds to the specified
   326         *  address range.
   327         *
   328         *  @param(baseAddr)        start address for which to set MAR
   329         *  @param(byteSize)        size (in bytes) of memory block
   330         *  @param(value)           enum of type Cache_Mar
   331         */
   332        @DirectCall
   333        Void setMar(Ptr baseAddr, SizeT byteSize, Mar value);
   334    
   335        /*!
   336         *  ======== invL1pAll ========
   337         *  Invalidate all of L1 Program cache
   338         *
   339         *  Performs a global invalidate of L1P cache.
   340         *  Polls the L1P invalidate register until done.
   341         */
   342        @DirectCall
   343        Void invL1pAll();
   344    
   345        /*!
   346         *  ======== wbAll ========
   347         *  Write back all caches
   348         *
   349         *  Perform a global write back.  There is no effect on L1P cache.
   350         *  All cache lines are left valid in L1D cache and the data in L1D cache
   351         *  is written back to L2 or external.  All cache lines are left valid in
   352         *  L2 cache and the data in L2 cache is written back to external.
   353         */
   354        @DirectCall
   355        override Void wbAll();
   356    
   357        /*!
   358         *  ======== wbInvAll ========
   359         *  Write back invalidate all caches
   360         *
   361         *  Performs a global write back and invalidate.  All cache lines are
   362         *  invalidated in L1P cache.  All cache lines are written back to L2 or
   363         *  external and then invalidated in L1D cache.  All cache lines are
   364         *  written back to external and then invalidated in L2 cache.
   365         */
   366        @DirectCall
   367        override Void wbInvAll();
   368    
   369    internal:
   370    
   371        /* cache configuration registers */
   372        const UInt32 L2CFG  = 0x01840000;
   373        const UInt32 L1PCFG = 0x01840020;
   374        const UInt32 L1PCC  = 0x01840024;
   375        const UInt32 L1DCFG = 0x01840040;
   376        const UInt32 L1DCC  = 0x01840044;
   377        const UInt32 MAR    = 0x01848000;
   378    
   379        /*!
   380         * @_nodoc
   381         * EMIF register addresses.
   382         */
   383        config UInt EMIFA_BASE;
   384        config UInt EMIFA_LENGTH;
   385        config UInt EMIFB_BASE;
   386        config UInt EMIFB_LENGTH;
   387        config UInt EMIFC_BASE;
   388        config UInt EMIFC_LENGTH;
   389        config UInt *EMIFA_CFG;
   390        config UInt *EMIFB_CFG;
   391        config UInt *EMIFC_CFG;
   392    
   393        struct Module_State {
   394            volatile UInt32 *emifAddr;      /*! Emif configuration address */
   395        }
   396    }
   397    /*
   398     *  @(#) ti.sysbios.family.c64p; 2, 0, 0, 0,458; 5-5-2011 15:18:14; /db/vtree/library/trees/avala/avala-o31x/src/ xlibrary
   399    
   400     */
   401