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17
18 package ti.catalog.c2800.initF2837x;
19
20 import xdc.rov.ViewInfo;
21
22 /*!
23 * ======== Boot ========
24 * Soprano Boot Support.
25 *
26 * The Boot module supports boot initialization for the C28 Soprano cores.
27 * A special boot init function is created based on the configuration
28 * settings for this module. This function is hooked into the
29 * xdc.runtime.Reset.fxns[] array and called very early at boot time (prior
30 * to cinit processing).
31 *
32 * The code to support the boot module is placed in a separate section
33 * named `".text:.bootCodeSection"` to allow placement of this section in
34 * the linker .cmd file if necessary. This section is a subsection of the
35 * `".text"` section so this code will be placed into the .text section unless
36 * explicitly placed, either through
37 * `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
38 * command file.
39 */
40 @Template("./Boot.xdt")
41 @NoRuntime
42 module Boot
43 {
44 /*! System PLL Fractional Multiplier (SPLLFMULT) value */
45 metaonly enum FractMult {
46 Fract_0 = 0x000, /*! Fractional multiplier is 0 */
47 Fract_25 = 0x100, /*! Fractional multiplier is 0.25 */
48 Fract_50 = 0x200, /*! Fractional multiplier is 0.5 */
49 Fract_75 = 0x300 /*! Fractional multiplier is 0.75 */
50 }
51
52 /*! Oscillator Clock Source Select Bit for OSCCLK */
53 metaonly enum OscClk {
54 OscClk_INTOSC2 = 0x0, /*! internal oscillator 2 (default on reset) */
55 OscClk_XTAL = 0x1, /*! external oscillator */
56 OscClk_INTOSC1 = 0x2, /*! internal oscillator 1 */
57 OscClk_RESERVED = 0x3 /*! reserved (default to INTOSC1) */
58 }
59
60 metaonly struct ModuleView {
61 Bool configureClocks;
62 UInt OSCCLK;
63 UInt SPLLIMULT;
64 String SPLLFMULT;
65 String SYSCLKDIVSEL;
66 Bool bootCPU2;
67 }
68
69 @Facet
70 metaonly config ViewInfo.Instance rovViewInfo =
71 ViewInfo.create({
72 viewMap: [
73 [
74 'Module',
75 {
76 type: ViewInfo.MODULE,
77 viewInitFxn: 'viewInitModule',
78 structName: 'ModuleView'
79 }
80 ],
81 ]
82 });
83
84 /*!
85 * Clock configuration flag, default is false.
86 *
87 * Set to true to configure the PLL and system subsystem clock
88 * dividers.
89 */
90 config Bool configureClocks = false;
91
92 /*!
93 * Oscillator Clock source select bit for OSCCLK
94 *
95 * The default on reset is INTOSC2
96 */
97 metaonly config OscClk OSCCLKSRCSEL = OscClk_INTOSC2;
98
99 /*!
100 * Watchdog disable flag, default is false.
101 *
102 * Set to true to disable the watchdog timer.
103 */
104 metaonly config Bool disableWatchdog = false;
105
106 /*!
107 * OSCCLK input frequency to PLL, in MHz.
108 *
109 * This is the frequency of the oscillator clock (OSCCLK) input to the
110 * PLL. The default internal oscillator is 10 Mhz.
111 */
112 metaonly config UInt OSCCLK = 10;
113
114 /*! System PLL Integer Multiplier (SPLLIMULT) value */
115 metaonly config UInt SPLLIMULT = 1;
116
117 /*! System PLL Fractional Multiplier (SPLLFMULT) value */
118 metaonly config FractMult SPLLFMULT = Fract_0;
119
120 /*! System Clock Divider Select (SYSCLKDIVSEL) value */
121 metaonly config UInt SYSCLKDIVSEL = 2;
122
123 /*!
124 * Flash controller configuration flag, default is true.
125 *
126 * Set to true to enable the configuration of the Flash controller
127 * wait states, program and data cache.
128 */
129 metaonly config Bool configureFlashController = true;
130
131 /*!
132 * Flash controller wait states configuration flag, default is true.
133 *
134 * Set to true to configure the Flash controller wait states. The number
135 * of wait states is computed based upon the CPU frequency.
136 */
137 metaonly config Bool configureFlashWaitStates = true;
138
139 /*!
140 * Flash controller program cache enable flag, default is true.
141 *
142 * Set to true to enable the Flash controller's program cache.
143 */
144 metaonly config Bool enableFlashProgramCache = true;
145
146 /*!
147 * Flash controller data cache enable flag, default is true.
148 *
149 * Set to true to enable the Flash controller's data cache.
150 */
151 metaonly config Bool enableFlashDataCache = true;
152
153 /*!
154 * Function to be called when Limp mode is detected.
155 *
156 * This function is called when the Boot module is about to configure
157 * the PLL, but finds the device operating in Limp mode (i.e., the mode
158 * when a missing OSCCLK input has been detected).
159 *
160 * If this function is not specified by the application, a default
161 * function will be used, which spins in an infinite loop.
162 */
163 metaonly config Fxn limpAbortFunction;
164
165 /*!
166 * Boot from Flash flag. Default is true.
167 *
168 * Set to true to enable booting CPU1 from Flash.
169 */
170 metaonly config Bool bootFromFlash = true;
171
172 /*!
173 * Initiate booting of the CPU2 processor. Default is false.
174 *
175 * Set to true to enable CPU1 to initiate boot of CPU2.
176 *
177 * If enabled, this will occur after the optional clock configuration
178 * step, enabled by `{@link #configureClocks}`.
179 */
180 metaonly config Bool bootCPU2 = false;
181
182 /*!
183 * Configure Shared RAM regions before booting the C28 processor.
184 * Default is true.
185 *
186 * Set to true to enable Shared RAM regions S0-S7, to set the
187 * owner of each region and the write access permissions for the onwer.
188 */
189 metaonly config Bool configSharedRAMs = true;
190
191 /*!
192 * ======== sharedMemoryOwnerMask ========
193 * Shared RAM owner select mask.
194 *
195 * This parameter is used for writing the GSxMSEL register.
196 * By default, each value of each shared RAM select bit is '0'.
197 * This means the CPU1 is the owner and has write access.
198 * Setting a '1' in any bit position makes CPU2 the owner of that
199 * shared RAM segment.
200 */
201 metaonly config Bits32 sharedMemoryOwnerMask = 0;
202
203 /*!
204 * ======== loadSegment ========
205 * Specifies where to load the flash function (include the 'PAGE' number)
206 *
207 * If 'configureFlashWaitStates' is true, then this parameter
208 * determines where the ".ti_catalog_c2800_initF2837x_flashfuncs"
209 * section gets loaded.
210 */
211 metaonly config String loadSegment;
212
213 /*!
214 * ======== runSegment ========
215 * Specifies where to run the flash function (include the 'PAGE' number)
216 *
217 * If 'configureFlashWaitStates' is true then this parameter
218 * determines where the ".ti_catalog_c2800_initF2837x_flashfuncs"
219 * section gets executed at runtime.
220 */
221 metaonly config String runSegment;
222
223 /*!
224 * @_nodoc
225 * ======== getFrequency ========
226 * Gets the resulting CPU frequency (in Hz) given the Clock
227 * configuration parameters.
228 *
229 */
230 UInt32 getFrequency();
231
232 /*!
233 * @_nodoc
234 * ======== registerFreqListener ========
235 * Register a module to be notified whenever the frequency changes.
236 *
237 * The registered module must have a function named 'fireFrequencyUpdate'
238 * which takes the new frequency as an argument.
239 */
240 function registerFreqListener();
241
242 internal:
243
244
245 metaonly config UInt timestampFreq;
246
247
248 metaonly config String displayFrequency;
249
250
251 metaonly config UInt flashWaitStates = 3;
252
253 };
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257