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12 /*!
13 * ======== ADC12 ========
14 * MSP430 12-bit Analog to Digital Converter
15 */
16 metaonly module ADC12 inherits IADC {
17
18 /*! SHT1 Bits */
19 enum ADC12SHT1_t {
20 SHT1_0 = (0*0x1000u), /*! 4 ADC12CLK cycles */
21 SHT1_1 = (1*0x1000u), /*! 8 ADC12CLK cycles */
22 SHT1_2 = (2*0x1000u), /*! 16 ADC12CLK cycles */
23 SHT1_3 = (3*0x1000u), /*! 32 ADC12CLK cycles */
24 SHT1_4 = (4*0x1000u), /*! 64 ADC12CLK cycles */
25 SHT1_5 = (5*0x1000u), /*! 96 ADC12CLK cycles */
26 SHT1_6 = (6*0x1000u), /*! 128 ADC12CLK cycles */
27 SHT1_7 = (7*0x1000u), /*! 192 ADC12CLK cycles */
28 SHT1_8 = (8*0x1000u), /*! 256 ADC12CLK cycles */
29 SHT1_9 = (9*0x1000u), /*! 384 ADC12CLK cycles */
30 SHT1_10 = (10*0x1000u), /*! 512 ADC12CLK cycles */
31 SHT1_11 = (11*0x1000u), /*! 768 ADC12CLK cycles */
32 SHT1_12 = 12*0x1000u /*! 1024 ADC12CLK cycles */
33 };
34
35 /*! SHT0 Bits */
36 enum ADC12SHT0_t {
37 SHT0_0 = (0*0x1000u), /*! 4 ADC12CLK cycles */
38 SHT0_1 = (1*0x1000u), /*! 8 ADC12CLK cycles */
39 SHT0_2 = (2*0x1000u), /*! 16 ADC12CLK cycles */
40 SHT0_3 = (3*0x1000u), /*! 32 ADC12CLK cycles */
41 SHT0_4 = (4*0x1000u), /*! 64 ADC12CLK cycles */
42 SHT0_5 = (5*0x1000u), /*! 96 ADC12CLK cycles */
43 SHT0_6 = (6*0x1000u), /*! 128 ADC12CLK cycles */
44 SHT0_7 = (7*0x1000u), /*! 192 ADC12CLK cycles */
45 SHT0_8 = (8*0x1000u), /*! 256 ADC12CLK cycles */
46 SHT0_9 = (9*0x1000u), /*! 384 ADC12CLK cycles */
47 SHT0_10 = (10*0x1000u), /*! 512 ADC12CLK cycles */
48 SHT0_11 = (11*0x1000u), /*! 768 ADC12CLK cycles */
49 SHT0_12 = 12*0x1000u /*! 1024 ADC12CLK cycles */
50 };
51
52 /*! MSC Bit */
53 enum MSC_t {
54 MSC_OFF = 0x000, /*! The sampling timer requires a rising edge of the SHI
55 * signal to trigger each sample-and-conversion */
56 MSC = 0x080 /*! The first rising edge of the SHI signal triggers
57 * the sampling timer, but further sample-and-conversions
58 * are performed automatically as soon as the prior conversion
59 * is completed */
60 };
61
62 /*! REF2_5V Bit */
63 enum REF2_5V_t {
64 REF2_5V_OFF = 0x000, /*! 1.5V */
65 REF2_5V = 0x040 /*! 2.5V */
66 };
67
68 /*! REFON Bit */
69 enum REFON_t {
70 REFON_OFF = 0x000, /*! Reference off */
71 REFON = 0x020 /*! Reference on */
72 };
73
74 /*! ADC12ON Bit */
75 enum ADC12ON_t {
76 ADC12ON_OFF = 0x000, /*! ADC12 off */
77 ADC12ON = 0x010 /*! ADC12 on */
78 };
79
80 /*! ADC12OVIE Bit */
81 enum ADC12OVIE_t {
82 ADC12OVIE_OFF = 0x000, /*! Overflow interrupt disabled */
83 ADC12OVIE = 0x008 /*! Overflow interrupt enabled */
84 };
85
86 /*! ADC12TOVIE Bit */
87 enum ADC12TOVIE_t {
88 ADC12TOVIE_OFF = 0x000, /*! Conversion time overflow interrupt disabled */
89 ADC12TOVIE = 0x004 /*! Conversion time overflow interrupt disabled */
90 };
91
92 /*! ENC Bit */
93 enum ENC_t {
94 ENC_OFF = 0x000, /*! ADC12 disabled */
95 ENC = 0x002 /*! ADC12 enabled */
96 };
97
98 /*! ADC12SC Bit */
99 enum ADC12SC_t {
100 ADC12SC_OFF = 0x000, /*! No sample-and-conversion-start */
101 ADC12SC = 0x001 /*! Start sample-and-conversion */
102 };
103
104 /*! CSTARTADD Bits */
105 enum CSTARTADD_t {
106 CSTARTADD_0 = (0*0x1000u), /*! ADC12MEM0 */
107 CSTARTADD_1 = (1*0x1000u), /*! ADC12MEM1 */
108 CSTARTADD_2 = (2*0x1000u), /*! ADC12MEM2 */
109 CSTARTADD_3 = (3*0x1000u), /*! ADC12MEM3 */
110 CSTARTADD_4 = (4*0x1000u), /*! ADC12MEM4 */
111 CSTARTADD_5 = (5*0x1000u), /*! ADC12MEM5 */
112 CSTARTADD_6 = (6*0x1000u), /*! ADC12MEM6 */
113 CSTARTADD_7 = (7*0x1000u), /*! ADC12MEM7 */
114 CSTARTADD_8 = (8*0x1000u), /*! ADC12MEM8 */
115 CSTARTADD_9 = (9*0x1000u), /*! ADC12MEM9 */
116 CSTARTADD_10 = (10*0x1000u), /*! ADC12MEM10 */
117 CSTARTADD_11 = (11*0x1000u), /*! ADC12MEM11 */
118 CSTARTADD_12 = (12*0x1000u), /*! ADC12MEM12 */
119 CSTARTADD_13 = (13*0x1000u), /*! ADC12MEM13 */
120 CSTARTADD_14 = (14*0x1000u), /*! ADC12MEM14 */
121 CSTARTADD_15 = 15*0x1000u /*! ADC12MEM15 */
122 };
123
124 /*! SHS Bits */
125 enum SHS_t {
126 SHS_0 = (0*0x400u), /*! ADC12SC bit */
127 SHS_1 = (1*0x400u), /*! Timer_A.OUT1 */
128 SHS_2 = (2*0x400u), /*! Timer_B.OUT0 */
129 SHS_3 = 3*0x400u /*! Timer_B.OUT1 */
130 };
131
132 /*! SHP Bits */
133 enum SHP_t {
134 SHP_OFF = 0x0000, /*! SAMPCON signal is sourced from the sample-input signal */
135 SHP = 0x0200 /*! SAMPCON signal is sourced from the sampling timer. */
136 };
137
138 /*! ISSH Bits */
139 enum ISSH_t {
140 ISSH_OFF = 0x0000, /*! The sample-input signal is not inverted */
141 ISSH = 0x0100 /*! The sample-input signal is inverted */
142 };
143
144
145 /*! ADC12DIV Bits */
146 enum ADC12DIV_t {
147 ADC12DIV_0 = (0*0x20u), /*! Divide by 1 */
148 ADC12DIV_1 = (1*0x20u), /*! Divide by 2 */
149 ADC12DIV_2 = (2*0x20u), /*! Divide by 3 */
150 ADC12DIV_3 = (3*0x20u), /*! Divide by 4 */
151 ADC12DIV_4 = (4*0x20u), /*! Divide by 5 */
152 ADC12DIV_5 = (5*0x20u), /*! Divide by 6 */
153 ADC12DIV_6 = (6*0x20u), /*! Divide by 7 */
154 ADC12DIV_7 = 7*0x20u /*! Divide by 8 */
155 };
156
157 /*! ADC12SSEL Bits */
158 enum ADC12SSEL_t {
159 ADC12SSEL_0 = (0*8u), /*! ADC12OSC */
160 ADC12SSEL_1 = (1*8u), /*! ACLK */
161 ADC12SSEL_2 = (2*8u), /*! MCLK */
162 ADC12SSEL_3 = 3*8u /*! SMCLK */
163 };
164
165 /*! CONSEQ Bits */
166 enum CONSEQ_t {
167 CONSEQ_0 = (0*2u), /*! Single channel single conversion */
168 CONSEQ_1 = (1*2u), /*! Sequence of channels */
169 CONSEQ_2 = (2*2u), /*! Repeat single channel */
170 CONSEQ_3 = 3*2u /*! Repeat sequence of channels */
171 };
172
173 /*! ADC12 Busy Bit */
174 enum ADC12BUSY_t {
175 ADC12BUSY_OFF = 0x0000,
176 ADC12BUSY = 0x0001
177 };
178
179 /*! EOS Bit */
180 enum EOS_t {
181 EOS_OFF = 0x0000, /*! Not end of sequence */
182 EOS = 0x0080 /*! End of sequence */
183 };
184
185 /*! SREF Bits */
186 enum SREF_t {
187 SREF_0 = (0*0x10u), /*! VR+ = AVcc and VR-- = AVss */
188 SREF_1 = (1*0x10u), /*! VR+ = VREF+ and VR-- = AVss */
189 SREF_2 = (2*0x10u), /*! VR+ = VeREF+ and VR-- = AVss */
190 SREF_3 = (3*0x10u), /*! VR+ = VeREF+ and VR-- = AVss */
191 SREF_4 = (4*0x10u), /*! VR+ = AVcc and VR-- = VREF--/ VeREF-- */
192 SREF_5 = (5*0x10u), /*! VR+ = VREF+ and VR-- = VREF--/ VeREF-- */
193 SREF_6 = (6*0x10u), /*! VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
194 SREF_7 = 7*0x10u /*! VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
195 };
196
197 /*! ADC12 Interrupt Enable Bit 15 */
198 enum ADC12IE15_t {
199 ADC12IE15_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG15 bit */
200 ADC12IE15 = 0x8000 /*! Enable the interrupt request for the ADC12IFG15 bit */
201 };
202
203 /*! ADC12 Interrupt Enable Bit 14 */
204 enum ADC12IE14_t {
205 ADC12IE14_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG14 bit */
206 ADC12IE14 = 0x4000 /*! Enable the interrupt request for the ADC12IFG14 bit */
207 };
208
209 /*! ADC12 Interrupt Enable Bit 13 */
210 enum ADC12IE13_t {
211 ADC12IE13_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG13 bit */
212 ADC12IE13 = 0x2000 /*! Enable the interrupt request for the ADC12IFG13 bit */
213 };
214
215 /*! ADC12 Interrupt Enable Bit 12 */
216 enum ADC12IE12_t {
217 ADC12IE12_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG12 bit */
218 ADC12IE12 = 0x1000 /*! Enable the interrupt request for the ADC12IFG12 bit */
219 };
220
221 /*! ADC12 Interrupt Enable Bit 11 */
222 enum ADC12IE11_t {
223 ADC12IE11_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG11 bit */
224 ADC12IE11 = 0x0800 /*! Enable the interrupt request for the ADC12IFG11 bit */
225 };
226
227 /*! ADC12 Interrupt Enable Bit 10 */
228 enum ADC12IE10_t {
229 ADC12IE10_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG10 bit */
230 ADC12IE10 = 0x0400 /*! Enable the interrupt request for the ADC12IFG10 bit */
231 };
232
233 /*! ADC12 Interrupt Enable Bit 9 */
234 enum ADC12IE9_t {
235 ADC12IE9_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG9 bit */
236 ADC12IE9 = 0x0200 /*! Enable the interrupt request for the ADC12IFG9 bit */
237 };
238
239 /*! ADC12 Interrupt Enable Bit 8 */
240 enum ADC12IE8_t {
241 ADC12IE8_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG8 bit */
242 ADC12IE8 = 0x0100 /*! Enable the interrupt request for the ADC12IFG8 bit */
243 };
244
245 /*! ADC12 Interrupt Enable Bit 7 */
246 enum ADC12IE7_t {
247 ADC12IE7_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG7 bit */
248 ADC12IE7 = 0x0080 /*! Enable the interrupt request for the ADC12IFG7 bit */
249 };
250
251 /*! ADC12 Interrupt Enable Bit 6 */
252 enum ADC12IE6_t {
253 ADC12IE6_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG6 bit */
254 ADC12IE6 = 0x0040 /*! Enable the interrupt request for the ADC12IFG6 bit */
255 };
256
257 /*! ADC12 Interrupt Enable Bit 5 */
258 enum ADC12IE5_t {
259 ADC12IE5_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG5 bit */
260 ADC12IE5 = 0x0020 /*! Enable the interrupt request for the ADC12IFG5 bit */
261 };
262
263 /*! ADC12 Interrupt Enable Bit 4 */
264 enum ADC12IE4_t {
265 ADC12IE4_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG4 bit */
266 ADC12IE4 = 0x0010 /*! Enable the interrupt request for the ADC12IFG4 bit */
267 };
268
269 /*! ADC12 Interrupt Enable Bit 3 */
270 enum ADC12IE3_t {
271 ADC12IE3_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG3 bit */
272 ADC12IE3 = 0x0008 /*! Enable the interrupt request for the ADC12IFG3 bit */
273 };
274
275 /*! ADC12 Interrupt Enable Bit 2 */
276 enum ADC12IE2_t {
277 ADC12IE2_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG2 bit */
278 ADC12IE2 = 0x0004 /*! Enable the interrupt request for the ADC12IFG2 bit */
279 };
280
281 /*! ADC12 Interrupt Enable Bit 1 */
282 enum ADC12IE1_t {
283 ADC12IE1_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG1 bit */
284 ADC12IE1 = 0x0002 /*! Enable the interrupt request for the ADC12IFG1 bit */
285 };
286
287 /*! ADC12 Interrupt Enable Bit 0 */
288 enum ADC12IE0_t {
289 ADC12IE0_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG0 bit */
290 ADC12IE0 = 0x0001 /*! Enable the interrupt request for the ADC12IFG0 bit */
291 };
292
293 /*! INCH Bits */
294 enum INCH_t {
295 INCH_0 = (0), /*! A0 */
296 INCH_1 = (1), /*! A1 */
297 INCH_2 = (2), /*! A2 */
298 INCH_3 = (3), /*! A3 */
299 INCH_4 = (4), /*! A4 */
300 INCH_5 = (5), /*! A5 */
301 INCH_6 = (6), /*! A6 */
302 INCH_7 = (7), /*! A7 */
303 INCH_8 = (8), /*! VeREF+ */
304 INCH_9 = (9), /*! VREF--/VeREF- */
305 INCH_10 = (10), /*! Temperature diode */
306 INCH_11 = (11), /*! (AVcc - AVss) / 2 */
307 INCH_12 = (12), /*! GND */
308 INCH_13 = (13), /*! GND */
309 INCH_14 = (14), /*! GND */
310 INCH_15 = 15 /*! GND */
311 };
312
313
314 /*! ADC12IV Definitions */
315 enum ADC12IV_t {
316 ADC12IV_NONE = (0x0000), /*! No Interrupt pending */
317 ADC12IV_ADC12OVIFG = (0x0002), /*! ADC12OVIFG */
318 ADC12IV_ADC12TOVIFG = (0x0004), /*! ADC12TOVIFG */
319 ADC12IV_ADC12IFG0 = (0x0006), /*! ADC12IFG0 */
320 ADC12IV_ADC12IFG1 = (0x0008), /*! ADC12IFG1 */
321 ADC12IV_ADC12IFG2 = (0x000A), /*! ADC12IFG2 */
322 ADC12IV_ADC12IFG3 = (0x000C), /*! ADC12IFG3 */
323 ADC12IV_ADC12IFG4 = (0x000E), /*! ADC12IFG4 */
324 ADC12IV_ADC12IFG5 = (0x0010), /*! ADC12IFG5 */
325 ADC12IV_ADC12IFG6 = (0x0012), /*! ADC12IFG6 */
326 ADC12IV_ADC12IFG7 = (0x0014), /*! ADC12IFG7 */
327 ADC12IV_ADC12IFG8 = (0x0016), /*! ADC12IFG8 */
328 ADC12IV_ADC12IFG9 = (0x0018), /*! ADC12IFG9 */
329 ADC12IV_ADC12IFG10 = (0x001A), /*! ADC12IFG10 */
330 ADC12IV_ADC12IFG11 = (0x001C), /*! ADC12IFG11 */
331 ADC12IV_ADC12IFG12 = (0x001E), /*! ADC12IFG12 */
332 ADC12IV_ADC12IFG13 = (0x0020), /*! ADC12IFG13 */
333 ADC12IV_ADC12IFG14 = (0x0022), /*! ADC12IFG14 */
334 ADC12IV_ADC12IFG15 = 0x0024 /*! ADC12IFG15 */
335 };
336
337 /*! ADC12 Control Register 0 */
338 struct ADC12CTL0_t {
339 ADC12SHT1_t ADC12SHT1; /*! Sample-and-hold time. These bits define the number
340 * of ADC12CLK cycles in the sampling period for registers
341 * ADC12MEM8 to ADC12MEM15. */
342 ADC12SHT0_t ADC12SHT0; /*! Sample-and-hold time. These bits define the number
343 * of ADC12CLK cycles in the sampling period for registers
344 * ADC12MEM0 to ADC12MEM7. */
345 MSC_t MSC; /*! Multiple sample and conversion. Valid only for sequence
346 * or repeated modes.
347 * 0 The sampling timer requires a rising edge of the SHI signal
348 * to trigger each sample-and-conversion.
349 * 1 The first rising edge of the SHI signal triggers the sampling
350 * timer, but further sample-and-conversions are performed
351 * automatically as soon as the prior conversion is completed. */
352 REF2_5V_t REF2_5V; /*! Reference generator voltage. REFON must also be set.
353 * 0 1.5V
354 * 1 2.5V */
355 REFON_t REFON; /*! Reference generator on
356 * 0 Reference off
357 * 1 Reference on */
358 ADC12ON_t ADC12ON; /*! ADC12 on
359 * 0 ADC12 off
360 * 1 ADC12 on */
361 ADC12OVIE_t ADC12OVIE; /*! ADC12MEMx overflow-interrupt enable. The GIE bit must also be
362 * set to enable the interrupt.
363 * 0 Overflow interrupt disabled
364 * 1 Overflow interrupt enabled */
365 ADC12TOVIE_t ADC12TOVIE; /*! ADC12 conversion-time-overflow interrupt enable.
366 * The GIE bit must also be set to enable the interrupt.
367 * 0 Conversion time overflow interrupt disabled
368 * 1 Conversion time overflow interrupt enabled */
369 ENC_t ENC; /*! Enable conversion
370 * 0 ADC12 disabled
371 * 1 ADC12 enabled */
372 ADC12SC_t ADC12SC; /*! Start conversion. Software-controlled sample-and-conversion start.
373 * ADC12SC and ENC may be set together with one instruction. ADC12SC is
374 * reset automatically.
375 * 0 No sample-and-conversion-start
376 * 1 Start sample-and-conversion */
377 };
378
379 /*! ADC12 Control Register 1 */
380 struct ADC12CTL1_t {
381 CSTARTADD_t CSTARTADD; /*! Conversion start address. These bits select which ADC12
382 * conversion-memory register is used for a single conversion or for the first
383 * conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh,
384 * corresponding to ADC12MEM0 to ADC12MEM15. */
385 SHS_t SHS; /*! Sample-and-hold source select
386 * 00 ADC12SC bit
387 * 01 Timer_A.OUT1
388 * 10 Timer_B.OUT0
389 * 11 Timer_B.OUT1 */
390 SHP_t SHP; /*! Sample-and-hold pulse-mode select. This bit selects the source of the
391 * sampling signal (SAMPCON) to be either the output of the sampling timer or
392 * the sample-input signal directly.
393 * 0 SAMPCON signal is sourced from the sample-input signal.
394 * 1 SAMPCON signal is sourced from the sampling timer. */
395 ISSH_t ISSH; /*! Invert signal sample-and-hold
396 * 0 The sample-input signal is not inverted.
397 * 1 The sample-input signal is inverted. */
398 ADC12DIV_t ADC12DIV; /*! ADC12 clock divider
399 * 000 /1
400 * 001 /2
401 * 010 /3
402 * 011 /4
403 * 100 /5
404 * 101 /6
405 * 110 /7
406 * 111 /8 */
407 ADC12SSEL_t ADC12SSEL; /*! ADC12 clock source select
408 * 00 ADC12OSC
409 * 01 ACLK
410 * 10 MCLK
411 * 11 SMCLK */
412 CONSEQ_t CONSEQ; /*! Conversion sequence mode select
413 * 00 Single-channel, single-conversion
414 * 01 Sequence-of-channels
415 * 10 Repeat-single-channel
416 * 11 Repeat-sequence-of-channels */
417 ADC12BUSY_t ADC12BUSY; /*! ADC12 busy. This bit indicates an active sample or conversion operation.
418 * 0 No operation is active.
419 * 1 A sequence, sample, or conversion is active. */
420 };
421
422 /*! ADC12 Conversion Memory Control Registers */
423 struct ADC12MCTL_t {
424 EOS_t EOS; /*! End of sequence. Indicates the last conversion in a sequence.
425 * 0 Not end of sequence
426 * 1 End of sequence */
427 SREF_t SREF; /*! Select reference
428 * 000 VR+ = AVCC and VR-- = AVSS
429 * 001 VR+ = VREF+ and VR-- = AVSS
430 * 010 VR+ = VeREF+ and VR-- = AVSS
431 * 011 VR+ = VeREF+ and VR-- = AVSS
432 * 100 VR+ = AVCC and VR-- = VREF--/ VeREF--
433 * 101 VR+ = VREF+ and VR-- = VREF--/ VeREF--
434 * 110 VR+ = VeREF+ and VR-- = VREF--/ VeREF--
435 * 111 VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
436 INCH_t INCH; /*! Input channel select
437 * 0000 A0
438 * 0001 A1
439 * 0010 A2
440 * 0011 A3
441 * 0100 A4
442 * 0101 A5
443 * 0110 A6
444 * 0111 A7
445 * 1000 VeREF+
446 * 1001 VREF--/VeREF--
447 * 1010 Temperature diode
448 * 1011 (AVCC � AVSS) / * 1100 GND
449 * 1101 GND
450 * 1110 GND
451 * 1111 GND */
452 };
453
454 /*! ADC12 Interrupt Enable Register */
455 struct ADC12IE_t {
456 ADC12IE15_t ADC12IE15; /*! Enable or disable the interrupt request for the ADC12IFG15 bit.
457 * 0 Interrupt disabled
458 * 1 Interrupt enabled */
459 ADC12IE14_t ADC12IE14; /*! Enable or disable the interrupt request for the ADC12IFG14 bit.
460 * 0 Interrupt disabled
461 * 1 Interrupt enabled */
462 ADC12IE13_t ADC12IE13; /*! Enable or disable the interrupt request for the ADC12IFG13 bit.
463 * 0 Interrupt disabled
464 * 1 Interrupt enabled */
465 ADC12IE12_t ADC12IE12; /*! Enable or disable the interrupt request for the ADC12IFG12 bit.
466 * 0 Interrupt disabled
467 * 1 Interrupt enabled */
468 ADC12IE11_t ADC12IE11; /*! Enable or disable the interrupt request for the ADC12IFG11 bit.
469 * 0 Interrupt disabled
470 * 1 Interrupt enabled */
471 ADC12IE10_t ADC12IE10; /*! Enable or disable the interrupt request for the ADC12IFG10 bit.
472 * 0 Interrupt disabled
473 * 1 Interrupt enabled */
474 ADC12IE9_t ADC12IE9; /*! Enable or disable the interrupt request for the ADC12IFG9 bit.
475 * 0 Interrupt disabled
476 * 1 Interrupt enabled */
477 ADC12IE8_t ADC12IE8; /*! Enable or disable the interrupt request for the ADC12IFG8 bit.
478 * 0 Interrupt disabled
479 * 1 Interrupt enabled */
480 ADC12IE7_t ADC12IE7; /*! Enable or disable the interrupt request for the ADC12IFG7 bit.
481 * 0 Interrupt disabled
482 * 1 Interrupt enabled */
483 ADC12IE6_t ADC12IE6; /*! Enable or disable the interrupt request for the ADC12IFG6 bit.
484 * 0 Interrupt disabled
485 * 1 Interrupt enabled */
486 ADC12IE5_t ADC12IE5; /*! Enable or disable the interrupt request for the ADC12IFG5 bit.
487 * 0 Interrupt disabled
488 * 1 Interrupt enabled */
489 ADC12IE4_t ADC12IE4; /*! Enable or disable the interrupt request for the ADC12IFG4 bit.
490 * 0 Interrupt disabled
491 * 1 Interrupt enabled */
492 ADC12IE3_t ADC12IE3; /*! Enable or disable the interrupt request for the ADC12IFG3 bit.
493 * 0 Interrupt disabled
494 * 1 Interrupt enabled */
495 ADC12IE2_t ADC12IE2; /*! Enable or disable the interrupt request for the ADC12IFG2 bit.
496 * 0 Interrupt disabled
497 * 1 Interrupt enabled */
498 ADC12IE1_t ADC12IE1; /*! Enable or disable the interrupt request for the ADC12IFG1 bit.
499 * 0 Interrupt disabled
500 * 1 Interrupt enabled */
501 ADC12IE0_t ADC12IE0; /*! Enable or disable the interrupt request for the ADC12IFG0 bit.
502 * 0 Interrupt disabled
503 * 1 Interrupt enabled */
504 };
505
506 instance:
507 /*! ADC12CTL0 Register */
508 config ADC12CTL0_t ADC12CTL0 = {
509 ADC12SHT1 : SHT1_0,
510 ADC12SHT0 : SHT0_0,
511 MSC : MSC_OFF,
512 REF2_5V : REF2_5V_OFF,
513 REFON : REFON_OFF,
514 ADC12ON : ADC12ON_OFF,
515 ADC12OVIE : ADC12OVIE_OFF,
516 ADC12TOVIE : ADC12TOVIE_OFF,
517 ENC : ENC_OFF,
518 ADC12SC : ADC12SC_OFF
519 };
520
521 /*! ADC12CTL1 Register */
522 config ADC12CTL1_t ADC12CTL1 = {
523 CSTARTADD : CSTARTADD_0,
524 SHS : SHS_0,
525 SHP : SHP_OFF,
526 ISSH : ISSH_OFF,
527 ADC12DIV : ADC12DIV_0,
528 ADC12SSEL : ADC12SSEL_0,
529 CONSEQ : CONSEQ_0,
530 ADC12BUSY : ADC12BUSY_OFF
531 };
532
533 /*! ADC12MCTL0 Register */
534 config ADC12MCTL_t ADC12MCTL0 = {
535 EOS : EOS_OFF,
536 SREF : SREF_0,
537 INCH : INCH_0
538 };
539
540 /*! ADC12MCTL1 Register */
541 config ADC12MCTL_t ADC12MCTL1 = {
542 EOS : EOS_OFF,
543 SREF : SREF_0,
544 INCH : INCH_0
545 };
546
547 /*! ADC12MCTL2 Register */
548 config ADC12MCTL_t ADC12MCTL2 = {
549 EOS : EOS_OFF,
550 SREF : SREF_0,
551 INCH : INCH_0
552 };
553
554 /*! ADC12MCTL3 Register */
555 config ADC12MCTL_t ADC12MCTL3 = {
556 EOS : EOS_OFF,
557 SREF : SREF_0,
558 INCH : INCH_0
559 };
560
561 /*! ADC12MCTL4 Register */
562 config ADC12MCTL_t ADC12MCTL4 = {
563 EOS : EOS_OFF,
564 SREF : SREF_0,
565 INCH : INCH_0
566 };
567
568 /*! ADC12MCTL5 Register */
569 config ADC12MCTL_t ADC12MCTL5 = {
570 EOS : EOS_OFF,
571 SREF : SREF_0,
572 INCH : INCH_0
573 };
574
575 /*! ADC12MCTL6 Register */
576 config ADC12MCTL_t ADC12MCTL6 = {
577 EOS : EOS_OFF,
578 SREF : SREF_0,
579 INCH : INCH_0
580 };
581
582 /*! ADC12MCTL7 Register */
583 config ADC12MCTL_t ADC12MCTL7 = {
584 EOS : EOS_OFF,
585 SREF : SREF_0,
586 INCH : INCH_0
587 };
588
589 /*! ADC12MCTL8 Register */
590 config ADC12MCTL_t ADC12MCTL8 = {
591 EOS : EOS_OFF,
592 SREF : SREF_0,
593 INCH : INCH_0
594 };
595
596 /*! ADC12MCTL9 Register */
597 config ADC12MCTL_t ADC12MCTL9 = {
598 EOS : EOS_OFF,
599 SREF : SREF_0,
600 INCH : INCH_0
601 };
602
603 /*! ADC12MCTL10 Register */
604 config ADC12MCTL_t ADC12MCTL10 = {
605 EOS : EOS_OFF,
606 SREF : SREF_0,
607 INCH : INCH_0
608 };
609
610 /*! ADC12MCTL11 Register */
611 config ADC12MCTL_t ADC12MCTL11 = {
612 EOS : EOS_OFF,
613 SREF : SREF_0,
614 INCH : INCH_0
615 };
616
617 /*! ADC12MCTL12 Register */
618 config ADC12MCTL_t ADC12MCTL12 = {
619 EOS : EOS_OFF,
620 SREF : SREF_0,
621 INCH : INCH_0
622 };
623
624 /*! ADC12MCTL13 Register */
625 config ADC12MCTL_t ADC12MCTL13 = {
626 EOS : EOS_OFF,
627 SREF : SREF_0,
628 INCH : INCH_0
629 };
630
631 /*! ADC12MCTL14 Register */
632 config ADC12MCTL_t ADC12MCTL14 = {
633 EOS : EOS_OFF,
634 SREF : SREF_0,
635 INCH : INCH_0
636 };
637
638 /*! ADC12MCTL15 Register */
639 config ADC12MCTL_t ADC12MCTL15 = {
640 EOS : EOS_OFF,
641 SREF : SREF_0,
642 INCH : INCH_0
643 };
644
645 /*! ADC12 Interrupt Enable Register */
646 config ADC12IE_t ADC12IE = {
647 ADC12IE15 : ADC12IE15_OFF,
648 ADC12IE14 : ADC12IE14_OFF,
649 ADC12IE13 : ADC12IE13_OFF,
650 ADC12IE12 : ADC12IE12_OFF,
651 ADC12IE11 : ADC12IE11_OFF,
652 ADC12IE10 : ADC12IE10_OFF,
653 ADC12IE9 : ADC12IE9_OFF,
654 ADC12IE8 : ADC12IE8_OFF,
655 ADC12IE7 : ADC12IE7_OFF,
656 ADC12IE6 : ADC12IE6_OFF,
657 ADC12IE5 : ADC12IE5_OFF,
658 ADC12IE4 : ADC12IE4_OFF,
659 ADC12IE3 : ADC12IE3_OFF,
660 ADC12IE2 : ADC12IE2_OFF,
661 ADC12IE1 : ADC12IE1_OFF,
662 ADC12IE0 : ADC12IE0_OFF
663 };
664
665
666 /*! ADC12MEM0 Register */
667 config Bits16 ADC12MEM0 = 0;
668
669 /*! ADC12MEM1 Register */
670 config Bits16 ADC12MEM1 = 0;
671
672 /*! ADC12MEM2 Register */
673 config Bits16 ADC12MEM2 = 0;
674
675 /*! ADC12MEM3 Register */
676 config Bits16 ADC12MEM3 = 0;
677
678 /*! ADC12MEM4 Register */
679 config Bits16 ADC12MEM4 = 0;
680
681 /*! ADC12MEM5 Register */
682 config Bits16 ADC12MEM5 = 0;
683
684 /*! ADC12MEM6 Register */
685 config Bits16 ADC12MEM6 = 0;
686
687 /*! ADC12MEM7 Register */
688 config Bits16 ADC12MEM7 = 0;
689
690 /*! ADC12MEM8 Register */
691 config Bits16 ADC12MEM8 = 0;
692
693 /*! ADC12MEM9 Register */
694 config Bits16 ADC12MEM9 = 0;
695
696 /*! ADC12MEM10 Register */
697 config Bits16 ADC12MEM10 = 0;
698
699 /*! ADC12MEM11 Register */
700 config Bits16 ADC12MEM11 = 0;
701
702 /*! ADC12MEM12 Register */
703 config Bits16 ADC12MEM12 = 0;
704
705 /*! ADC12MEM13 Register */
706 config Bits16 ADC12MEM13 = 0;
707
708 /*! ADC12MEM14 Register */
709 config Bits16 ADC12MEM14 = 0;
710
711 /*! ADC12MEM15 Register */
712 config Bits16 ADC12MEM15 = 0;
713
714 /*! ADC12IV Register */
715 config Bits16 ADC12IV = ADC12IV_NONE;
716
717 /*! ADC12IFG Register */
718 config Bits16 ADC12IFG = 0;
719
720 /*! ADC12 has 16 interrupt enable */
721 config regIntVect_t interruptSource[16];
722
723 /*! Determine if each Register needs to be forced set or not */
724 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
725 [
726 { register : "ADC12CTL0" , regForceSet : false },
727 { register : "ADC12CTL1" , regForceSet : false },
728 { register : "ADC12IFG" , regForceSet : false },
729 { register : "ADC12IV" , regForceSet : false },
730 { register : "ADC12IE" , regForceSet : false },
731 { register : "ADC12MCTL0" , regForceSet : false },
732 { register : "ADC12MCTL1" , regForceSet : false },
733 { register : "ADC12MCTL2" , regForceSet : false },
734 { register : "ADC12MCTL3" , regForceSet : false },
735 { register : "ADC12MCTL4" , regForceSet : false },
736 { register : "ADC12MCTL5" , regForceSet : false },
737 { register : "ADC12MCTL6" , regForceSet : false },
738 { register : "ADC12MCTL7" , regForceSet : false },
739 { register : "ADC12MCTL8" , regForceSet : false },
740 { register : "ADC12MCTL9" , regForceSet : false },
741 { register : "ADC12MCTL10" , regForceSet : false },
742 { register : "ADC12MCTL11" , regForceSet : false },
743 { register : "ADC12MCTL12" , regForceSet : false },
744 { register : "ADC12MCTL13" , regForceSet : false },
745 { register : "ADC12MCTL14" , regForceSet : false },
746 { register : "ADC12MCTL15" , regForceSet : false },
747 { register : "ADC12MEM0" , regForceSet : false },
748 { register : "ADC12MEM1" , regForceSet : false },
749 { register : "ADC12MEM2" , regForceSet : false },
750 { register : "ADC12MEM3" , regForceSet : false },
751 { register : "ADC12MEM4" , regForceSet : false },
752 { register : "ADC12MEM5" , regForceSet : false },
753 { register : "ADC12MEM6" , regForceSet : false },
754 { register : "ADC12MEM7" , regForceSet : false },
755 { register : "ADC12MEM8" , regForceSet : false },
756 { register : "ADC12MEM9" , regForceSet : false },
757 { register : "ADC12MEM10" , regForceSet : false },
758 { register : "ADC12MEM11" , regForceSet : false },
759 { register : "ADC12MEM12" , regForceSet : false },
760 { register : "ADC12MEM13" , regForceSet : false },
761 { register : "ADC12MEM14" , regForceSet : false },
762 { register : "ADC12MEM15" , regForceSet : false },
763 ];
764 }
765 766 767
768