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18 package ti.catalog.arm.cortexm3.concertoInit;
19
20 import xdc.rov.ViewInfo;
21
22 /*!
23 * ======== Boot ========
24 * Concerto M3 Boot Support.
25 *
26 * The Boot module supports boot initialization for the Concerto M3 core.
27 * A special boot init function is created based on the configuration
28 * settings for this module. This function is hooked into the
29 * xdc.runtime.Reset.fxns[] array and called very early at boot time (prior
30 * to cinit processing).
31 *
32 * The code to support the boot module is placed in a separate section
33 * named `".text:.bootCodeSection"` to allow placement of this section in
34 * the linker .cmd file if necessary. This section is a subsection of the
35 * `".text"` section so this code will be placed into the .text section unless
36 * explicitly placed, either through
37 * `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
38 * command file.
39 */
40 @Template("./Boot.xdt")
41 @NoRuntime
42 module Boot
43 {
44 /*! System PLL Fractional Multiplier (SPLLFMULT) value */
45 metaonly enum FractMult {
46 Fract_0 = 0x000, /*! Fractional multiplier is 0 */
47 Fract_25 = 0x100, /*! Fractional multiplier is 0.25 */
48 Fract_50 = 0x200, /*! Fractional multiplier is 0.5 */
49 Fract_75 = 0x300 /*! Fractional multiplier is 0.75 */
50 }
51
52 /*! System Clock Divider (SYSDIVSEL) value */
53 metaonly enum SysDiv {
54 Div_1 = 0x0, /*! Divide by 1 */
55 Div_2 = 0x1, /*! Divide by 2 */
56 Div_4 = 0x2, /*! Divide by 4 */
57 Div_8 = 0x3 /*! Divide by 8 */
58 };
59
60 /*! M3 Subsystem Clock Divider (M3SSDIVSEL) value */
61 metaonly enum M3Div {
62 M3Div_1 = 0x0, /*! Divide by 1 */
63 M3Div_2 = 0x1, /*! Divide by 2 */
64 M3Div_4 = 0x2 /*! Divide by 4 */
65 };
66
67 metaonly struct ModuleView {
68 Bool configureClocks;
69 UInt OSCCLK;
70 UInt SPLLIMULT;
71 String SPLLFMULT;
72 String SYSDIVSEL;
73 String M3SSDIVSEL;
74 Bool bootC28;
75 }
76
77 @Facet
78 metaonly config ViewInfo.Instance rovViewInfo =
79 ViewInfo.create({
80 viewMap: [
81 [
82 'Module',
83 {
84 type: ViewInfo.MODULE,
85 viewInitFxn: 'viewInitModule',
86 structName: 'ModuleView'
87 }
88 ],
89 ]
90 });
91
92 /*!
93 * Flash controller configuration flag, default is true.
94 *
95 * Set to true to enable the configuration of the Flash controller
96 * wait states, program and data cache.
97 */
98 metaonly config Bool configureFlashController = true;
99
100 /*!
101 * Clock configuration flag, default is false.
102 *
103 * Set to true to configure the PLL and system and M3 subsystem clock
104 * dividers.
105 */
106 config Bool configureClocks = false;
107
108 /*!
109 * ======== sharedMemoryEnable ========
110 * Shared RAM memory enable mask.
111 *
112 * This parameter is used for writing the MEMCNF register.
113 * By default, all shared RAM segments will be enabled at runtime.
114 * To disable a shared RAM segment, set the corresponding bit to 0.
115 * If any data is loaded to a shared RAM segment, the segment must
116 * be enabled prior to loading the program through other means.
117 */
118 config Bits32 sharedMemoryEnable = 0xffffffff;
119
120 /*!
121 * ======== sharedMemoryOwnerMask ========
122 * Shared RAM owner select mask.
123 *
124 * This parameter is used for writing the MSxMSEL register.
125 * By default, each value of each shared RAM select bit is '0'.
126 * This means the M3 is the owner and has write access based upon
127 * the sharedMemoryAccess bits. Setting a '1' in any bit position
128 * makes the C28 the owner of that shared RAM segment.
129 */
130 config Bits32 sharedMemoryOwnerMask = 0;
131
132 /*!
133 * ======== sharedMemoryAccess ========
134 * Shared RAM M3 write access.
135 *
136 * This parameter is used for writing the MSxSRCR registers.
137 * It determines the M3 write access for each shared RAM segment only
138 * when the M3 is the owner of the shared RAM segment.
139 * By default, the M3 is allowed to CPU fetch, DMA write, and CPU write.
140 *
141 * Bit 0 is for CPU fetch. 0 - fetch allowed, 1 - fetch not allowed
142 * Bit 1 is for DMA write. 0 - write allowed, 1 - write not allowed
143 * Bit 2 is for CPU write. 0 - write allowed, 1 - write not allowed
144 */
145 config Bits32 sharedMemoryAccess[8];
146
147 /*!
148 * OSCCLK input frequency to PLL, in MHz. Default is 20 MHz.
149 *
150 * This is the frequency of the oscillator clock (OSCCLK) input to the
151 * PLL.
152 */
153 metaonly config UInt OSCCLK = 20;
154
155 /*! System PLL Integer Multiplier (SPLLIMULT) value */
156 metaonly config UInt SPLLIMULT = 1;
157
158 /*! System PLL Fractional Multiplier (SPLLFMULT) value */
159 metaonly config FractMult SPLLFMULT = Fract_0;
160
161 /*! System Clock Divider (SYSDIVSEL) value */
162 metaonly config SysDiv SYSDIVSEL = Div_8;
163
164 /*! M3 Subsystem Clock Divider (M3SSDIVSEL) value */
165 metaonly config M3Div M3SSDIVSEL = M3Div_4;
166
167 /*!
168 * Flash controller wait states configuration flag, default is true.
169 *
170 * Set to true to configure the Flash controller wait states. The number
171 * of wait states is computed based upon the CPU frequency.
172 */
173 metaonly config Bool configureFlashWaitStates = true;
174
175 /*!
176 * Flash controller program cache enable flag, default is true.
177 *
178 * Set to true to enable the Flash controller's program cache.
179 */
180 metaonly config Bool enableFlashProgramCache = true;
181
182 /*!
183 * Flash controller data cache enable flag, default is true.
184 *
185 * Set to true to enable the Flash controller's data cache.
186 */
187 metaonly config Bool enableFlashDataCache = true;
188
189 /*!
190 * Function to be called when Limp mode is detected.
191 *
192 * This function is called when the Boot module is about to configure
193 * the PLL, but finds the device operating in Limp mode (i.e., the mode
194 * when a missing OSCCLK input has been detected).
195 *
196 * If this function is not specified by the application, a default
197 * function will be used, which spins in an infinite loop.
198 */
199 metaonly config Fxn limpAbortFunction;
200
201 /*!
202 * Boot from Flash flag. Default is true.
203 *
204 * Set to true to enable booting the M3 from Flash.
205 */
206 metaonly config Bool bootFromFlash = true;
207
208 /*!
209 * Initiate booting of the C28 processor. Default is false.
210 *
211 * Set to true to enable the M3 to initiate boot of the C28.
212 *
213 * If enabled, this will occur after the optional clock configuration
214 * step, enabled by `{@link #configureClocks}`.
215 */
216 metaonly config Bool bootC28 = false;
217
218 /*!
219 * Initialize C28 RAM regions before booting the C28 processor.
220 * Default is true.
221 *
222 * Set to true to enable initialization of these C28 RAM regions: M1,
223 * CtoM, LO, L1, L2, and L3. RAM locations will be zeroed, and the ECC or
224 * parity bits will be initialized.
225 */
226 metaonly config Bool initC28RAMs = true;
227
228 /*!
229 * Configure Shared RAM regions before booting the C28 processor.
230 * Default is true.
231 *
232 * Set to true to enable Shared RAM regions S0-S7, to set the
233 * owner of each region and the write access permissions for the onwer.
234 */
235 metaonly config Bool configSharedRAMs = true;
236
237 /*!
238 * ======== loadSegment ========
239 * Specifies where to load the flash function
240 *
241 * If 'configureFlashWaitStates' is true, then this parameter
242 * determines where the ".ti_catalog_c2800_initF2837x_flashfuncs"
243 * section gets loaded.
244 */
245 metaonly config String loadSegment;
246
247 /*!
248 * ======== runSegment ========
249 * Specifies where to run the flash function
250 *
251 * If 'configureFlashWaitStates' is true then this parameter
252 * determines where the ".ti_catalog_c2800_initF2837x_flashfuncs"
253 * section gets executed at runtime.
254 */
255 metaonly config String runSegment;
256
257 /*!
258 * @_nodoc
259 * ======== getFrequency ========
260 * Gets the resulting M3 CPU frequency (in Hz) given the Clock
261 * configuration parameters.
262 *
263 */
264 UInt32 getFrequency();
265
266 /*!
267 * @_nodoc
268 * ======== registerFreqListener ========
269 * Register a module to be notified whenever the frequency changes.
270 *
271 * The registered module must have a function named 'fireFrequencyUpdate'
272 * which takes the new frequency as an argument.
273 */
274 function registerFreqListener();
275
276 internal:
277
278
279 metaonly config UInt timestampFreq;
280
281
282 metaonly config String displayFrequency;
283
284
285 metaonly config String displayFrequency28;
286
287
288 metaonly config UInt flashWaitStates = 3;
289
290
291 metaonly config Bits32 MSxSRCR[2];
292
293 };
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297