1    /* 
     2     *  Copyright (c) 2015 Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    /*!
    13     *  ======== Timer3_A5 ========
    14     *  MSP430 Timer3_A5 timer
    15     */
    16    metaonly module Timer3_A5 inherits ITimer_A {
    17    
    18    instance:
    19        /*! TA3CTL, Timer3_A5 Control Register */
    20        config TACTL_t TA3CTL = {
    21            TASSEL : TASSEL_0,
    22            ID : ID_0,
    23            MC : MC_0,
    24            TACLR : TACLR_OFF,
    25            TAIE : TAIE_OFF,
    26            TAIFG : TAIFG_OFF
    27        };
    28    
    29        /*! TA3CCTL0, Capture/Compare Control Register 0 */
    30        config TACCTLx_t TA3CCTL0 = {
    31            CM : CM_0,
    32            CCIS : CCIS_0,
    33            SCS : SCS_OFF,
    34            SCCI : SCCI_OFF,
    35            CAP : CAP_OFF,
    36            OUTMOD : OUTMOD_0,
    37            CCIE : CCIE_OFF,
    38            CCI : CCI_OFF,
    39            OUT : OUT_OFF,
    40            COV : COV_OFF,
    41            CCIFG : CCIFG_OFF
    42        };
    43    
    44        /*! TA3CCTL1, Capture/Compare Control Register 1 */
    45        config TACCTLx_t TA3CCTL1 = {
    46            CM : CM_0,
    47            CCIS : CCIS_0,
    48            SCS : SCS_OFF,
    49            SCCI : SCCI_OFF,
    50            CAP : CAP_OFF,
    51            OUTMOD : OUTMOD_0,
    52            CCIE : CCIE_OFF,
    53            CCI : CCI_OFF,
    54            OUT : OUT_OFF,
    55            COV : COV_OFF,
    56            CCIFG : CCIFG_OFF
    57        };
    58    
    59        /*! TA3CCTL2, Capture/Compare Control Register 2 */
    60        config TACCTLx_t TA3CCTL2 = {
    61            CM : CM_0,
    62            CCIS : CCIS_0,
    63            SCS : SCS_OFF,
    64            SCCI : SCCI_OFF,
    65            CAP : CAP_OFF,
    66            OUTMOD : OUTMOD_0,
    67            CCIE : CCIE_OFF,
    68            CCI : CCI_OFF,
    69            OUT : OUT_OFF,
    70            COV : COV_OFF,
    71            CCIFG : CCIFG_OFF
    72        };
    73    
    74        /*! TA3CCTL3, Capture/Compare Control Register 3 */
    75        config TACCTLx_t TA3CCTL3 = {
    76            CM : CM_0,
    77            CCIS : CCIS_0,
    78            SCS : SCS_OFF,
    79            SCCI : SCCI_OFF,
    80            CAP : CAP_OFF,
    81            OUTMOD : OUTMOD_0,
    82            CCIE : CCIE_OFF,
    83            CCI : CCI_OFF,
    84            OUT : OUT_OFF,
    85            COV : COV_OFF,
    86            CCIFG : CCIFG_OFF
    87        };
    88    
    89        /*! TA3CCTL4, Capture/Compare Control Register 4 */
    90        config TACCTLx_t TA3CCTL4 = {
    91            CM : CM_0,
    92            CCIS : CCIS_0,
    93            SCS : SCS_OFF,
    94            SCCI : SCCI_OFF,
    95            CAP : CAP_OFF,
    96            OUTMOD : OUTMOD_0,
    97            CCIE : CCIE_OFF,
    98            CCI : CCI_OFF,
    99            OUT : OUT_OFF,
   100            COV : COV_OFF,
   101            CCIFG : CCIFG_OFF
   102        };
   103    
   104        /*! TA3CCR0, Timer_A Capture/Compare Register 0 */
   105        config Bits16 TA3CCR0 = 0;
   106        /*! TA3CCR1, Timer_A Capture/Compare Register 1 */
   107        config Bits16 TA3CCR1 = 0;
   108        /*! TA3CCR2, Timer_A Capture/Compare Register 2 */
   109        config Bits16 TA3CCR2 = 0;
   110        /*! TA3CCR3, Timer_A Capture/Compare Register 3 */
   111        config Bits16 TA3CCR3 = 0;
   112        /*! TA3CCR4, Timer_A Capture/Compare Register 4 */
   113        config Bits16 TA3CCR4 = 0;
   114    
   115        /*! Timer interrupt enables */
   116        config regIntVect_t interruptSource[6];
   117    
   118        /*! Determine if each Register needs to be forced set or not */
   119        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   120        [
   121            { register : "TA3CTL"   , regForceSet : false },
   122            { register : "TA3CCTL0" , regForceSet : false },
   123            { register : "TA3CCTL1" , regForceSet : false },
   124            { register : "TA3CCR0"  , regForceSet : false },
   125            { register : "TA3CCR1"  , regForceSet : false },
   126            { register : "TA3CCR2"  , regForceSet : false },
   127            { register : "TA3CCR3"  , regForceSet : false },
   128            { register : "TA3CCR4"  , regForceSet : false }
   129        ];
   130    }
   131    /*
   132     *  @(#) ti.catalog.msp430.peripherals.timer; 1, 0, 0,; 8-14-2015 13:38:49; /db/ztree/library/trees/platform/platform-q07/src/
   133     */
   134