1    /*
     2     *  Copyright 2009 by Texas Instruments Incorporated.
     3     *
     4     *  All rights reserved. Property of Texas Instruments Incorporated.
     5     *  Restricted rights to use, duplicate or disclose this code are
     6     *  granted through contract.
     7     *
     8     */
     9    
    10    /*
    11     *  ======== TMS320C6454.xdc ========
    12     *
    13     */
    14    
    15    /*!
    16     *  ======== TMS320C6454 ========
    17     *  The 6454 device data sheet module.
    18     *
    19     *  This module implements the ICpuDataSheet interface and is 
    20     *  used by platforms to obtain "data sheet" information about this device.
    21     */
    22    metaonly module TMS320C6454 inherits ti.catalog.ICpuDataSheet
    23    {
    24        config long cacheSizeL1[string] = [
    25            ["0k",  0x0000],
    26            ["4k",  0x1000],
    27            ["8k",  0x2000],
    28            ["16k", 0x4000],
    29            ["32k", 0x8000],
    30        ];
    31    
    32        config long cacheSizeL2[string] = [
    33            ["0k",   0x00000],
    34            ["32k",  0x08000],
    35            ["64k",  0x10000],
    36            ["128k", 0x20000],
    37            ["256k", 0x40000]
    38        ];
    39    
    40        readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    41             ['l1PMode',{desc:"L1P Cache",
    42                         map : [["0k",0x0000],
    43                                ["4k",0x1000],
    44                                ["8k",0x2000],
    45                                ["16k",0x4000],
    46                                ["32k",0x8000]],
    47                         defaultValue: "0k",
    48                         memorySection: "L1PSRAM"}],
    49         
    50                     ['l1DMode',{desc:"L1D Cache",
    51                         map : [["0k",0x0000],
    52                                ["4k",0x1000],
    53                                ["8k",0x2000],
    54                                ["16k",0x4000],
    55                                ["32k",0x8000]],
    56                         defaultValue: "0k",
    57                         memorySection: "L1DSRAM"}],
    58                     
    59             ['l2Mode',{desc:"L2 Cache",
    60                         map : [["0k",0x0000],
    61                                ["32k",0x8000],
    62                                ["64k",0x10000],
    63                                ["128k",0x20000],
    64                                ["256k",0x40000]],
    65                         defaultValue: "0k",
    66                         memorySection: "IRAM"}], 
    67        ];
    68    
    69    instance:
    70    
    71        override config string   cpuCore        = "64x+";
    72        override config string   isa = "64P";
    73        override config string   cpuCoreRevision = "1.0";
    74    
    75        override config int     minProgUnitSize = 1;
    76        override config int     minDataUnitSize = 1;    
    77        override config int     dataWordSize    = 4;
    78    
    79        /*!
    80         *  ======== memMap ========
    81         *  The default memory map for this device
    82         */
    83        config xdc.platform.IPlatform.Memory memMap[string]  = [
    84            ["IRAM", {
    85                comment:    "Internal 1MB UMAP0 memory",
    86                name:       "IRAM",
    87                base:       0x800000,
    88                len:        0x100000,
    89                space:      "code/data",
    90                access:     "RWX"
    91            }],
    92    
    93            ["L1PSRAM", {
    94                comment:    "Internal 32KB RAM/CACHE L1 program memory",
    95                name:       "L1PSRAM",
    96                base:       0xE00000,
    97                len:        0x008000,
    98                space:      "code",
    99                access:     "RWX"
   100            }],
   101    
   102            ["L1DSRAM", {
   103                comment:    "Internal 32KB RAM/CACHE L1 data memory",
   104                name:       "L1DSRAM",
   105                base:       0xF00000,
   106                len:        0x008000,
   107                space:      "data",
   108                access:     "RW"
   109            }],
   110    
   111        ];
   112    };
   113    /*
   114     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,173; 6-4-2009 14:07:54; /db/ztree/library/trees/platform-k10x/src/
   115     */
   116