1 /*
2 * Copyright (c) 2014 Texas Instruments Incorporated - https://www.ti.com
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 /*
33 * ======== InterruptIpu.xdc ========
34 *
35 */
36
37 import ti.sdo.utils.MultiProc;
38
39 /*!
40 * ======== InterruptIpu ========
41 * IPU interrupt manager
42 */
43 module InterruptIpu inherits ti.sdo.ipc.notifyDrivers.IInterrupt
44 {
45 /*!
46 * Maximum number of cores
47 *
48 * @_nodoc
49 */
50 const UInt8 NUM_CORES = 5;
51
52 /*!
53 * Maximum number of EVE cores
54 *
55 * Although your device may have fewer EVE cores, `NUM_EVES` represents
56 * the maximum number of EVEs that may be present on a system.
57 */
58 const UInt8 NUM_EVES = 1;
59
60 /*!
61 * Maximum number of IPU cores
62 *
63 * @_nodoc
64 */
65 const UInt8 NUM_Ipu_CORES = 2;
66
67 /*!
68 * Number of internal EVE mailboxes
69 *
70 * Each EVE core has 3 mailboxes.
71 *
72 * Although your device may have fewer EVE cores, `NUM_EVE_MBX` represents
73 * the maximum number of EVE mailboxes (including all EVE cores) that may
74 * be present.
75 */
76 const UInt8 NUM_EVE_MBX = NUM_EVES * 2;
77
78 /*!
79 * Number of System mailboxes used by IPC
80 *
81 * This represents the number of System mailboxes used by IPC. IPC
82 * currently uses system mailboxes 5, 6, 7 and 8.
83 */
84 const UInt8 NUM_SYS_MBX = 1;
85
86 /*!
87 * Base address for the mailbox subsystems
88 *
89 * The `mailboxBaseAddr` array indicates the virtual addresses through
90 * which IPC will access various mailboxes.
91 *
92 * Note that these mailboxes are not accessible at their physical
93 * addresses (in the 0x4XXX_XXXX range). So default virtual addresses
94 * through which these mailboxes will be accessed are assigned in the
95 * 0x6XXX_XXXX range. Users must ensure these virtual addresses are
96 * correctly mapped to the 0x4XXX_XXXX-based phys addrs in each IPUs AMMU.
97 */
98 config UInt32 mailboxBaseAddr[NUM_EVE_MBX + NUM_SYS_MBX];
99
100 /*!
101 * Mailbox table for storing encoded Base Address, mailbox user Id,
102 * and sub-mailbox index.
103 *
104 * @_nodoc
105 */
106 config UInt32 mailboxTable[NUM_CORES * NUM_CORES];
107
108 /*!
109 * Base address for the Ducati CTRL register
110 */
111 config UInt32 ducatiCtrlBaseAddr = 0x40001000;
112
113 /*!
114 * Processor Id table
115 *
116 * @_nodoc
117 */
118 config UInt32 procIdTable[NUM_CORES];
119
120 internal:
121
122 /*! Statically retrieve procIds to avoid doing this at runtime */
123 config UInt eve1ProcId = MultiProc.INVALIDID;
124 config UInt dsp1ProcId = MultiProc.INVALIDID;
125 config UInt dsp2ProcId = MultiProc.INVALIDID;
126 config UInt ipu1_0ProcId = MultiProc.INVALIDID;
127 config UInt ipu1_1ProcId = MultiProc.INVALIDID;
128
129 /*! Function table */
130 struct FxnTable {
131 Fxn func;
132 UArg arg;
133 }
134
135 /*! Stub to be plugged for inter-ducati interrupts */
136 Void intShmDucatiStub(UArg arg);
137
138 /*! Stub to be plugged for intra-ducati interrupts */
139 Void intShmMbxStub(UInt16 idx);
140
141 struct Module_State {
142 /*
143 * Create a function table of length 8 (Total number of cores in the
144 * System) for each M4 core.
145 */
146 FxnTable fxnTable[NUM_CORES];
147 };
148 }